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* MIPS: Probe for presence of KScratch registers.David Daney2011-01-18
| | | | | | | | | Probe c0_config4 for KScratch registers and report them in /proc/cpuinfo. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1877/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix regression on BCM4710 processor detectionKevin Cernekee2010-12-16
| | | | | | | | | | BCM4710 uses the BMIPS32 core (like BCM6345), not the MIPS 4Kc core as was previously believed. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Tested-by: Alexandros C. Couloumbis <alex@ozo.com> Patchwork: https://patchwork.linux-mips.org/patch/1837/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Make TASK_SIZE reflect proper size for both 32 and 64 bit processes.David Daney2010-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TASK_SIZE macro should reflect the size of a user process virtual address space. Previously for 64-bit kernels, this was not the case. The immediate cause of pain was in hugetlbfs/inode.c:hugetlb_get_unmapped_area() where 32-bit processes trying to mmap a huge page would be served a page with an address outside of the 32-bit address range. But there are other uses of TASK_SIZE in the kernel as well that would like an accurate value. The new definition is nice because it now makes TASK_SIZE and TASK_SIZE_OF() yield the same value for any given process. For 32-bit kernels there should be no change, although I did factor out some code in asm/processor.h that became identical for the 32-bit and 64-bit cases. __UA_LIMIT is now set to ~((1 << SEGBITS) - 1) for 64-bit kernels. This should eliminate the possibility of getting a AddressErrorException in the kernel for addresses that pass the access_ok() test. With the patch applied, I can still run o32, n32 and n64 processes, and have an o32 shell fork/exec both n32 and n64 processes. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1701/
* MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC codeKevin Cernekee2010-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | BMIPS processor cores are used in 50+ different chipsets spread across 5+ product lines. In many cases the chipsets do not share the same peripheral register layouts, the same register blocks, the same interrupt controllers, the same memory maps, or much of anything else. But, across radically different SoCs that share nothing more than the same BMIPS CPU, a few things are still mostly constant: SMP operations Access to performance counters DMA cache coherency quirks Cache and memory bus configuration So, it makes sense to treat each BMIPS processor type as a generic "building block," rather than tying it to a specific SoC. This makes it easier to support a large number of BMIPS-based chipsets without unnecessary duplication of code, and provides the infrastructure needed to support BMIPS-proprietary features. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: mbizon@freebox.fr Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Tested-by: Florian Fainelli <ffainelli@freebox.fr> Patchwork: https://patchwork.linux-mips.org/patch/1706/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
* MIPS: Octeon: Probe for Octeon II CPUs.David Daney2010-10-29
| | | | | | | | | | The OCTEON II ISA extends the original OCTEON ISA, so give it its own __elf_platform string so optimized libraries can be selected in userspace. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1665/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Decode core number for R2 CPUs.David Daney2010-08-05
| | | | | | | | | | | The struct cpuinfo_mips.core field should be populated with the physical core number. For R2 CPUs, this is carried in the low 10 bits of Ebase. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1505/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: Add base support for Ingenic JZ4740 System-on-a-ChipLars-Peter Clausen2010-08-05
| | | | | | | | | | | | Adds a new cpu type for the JZ4740 to the Linux MIPS architecture code. It also adds the iomem addresses for the different components found on a JZ4740 SoC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1464/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: nofpu and nodsp only affect CPU0Kevin Cernekee2010-05-21
| | | | | | | | | | | | | | | | | | The "nofpu" and "nodsp" kernel command line options currently do not affect CPUs that are brought online later in the boot process or hotplugged at runtime. It is desirable to apply the nofpu/nodsp options to all CPUs in the system, so that surprising results are not seen when a process migrates from one CPU to another. [Ralf: Moved definitions of mips_fpu_disabled, fpu_disable, mips_dsp_disabled and dsp_disable from setup.c to cpu-probe.c to allow making mips_fpu_disabled and mips_dsp_disabled static.] Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: http://patchwork.linux-mips.org/patch/1169/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Give Octeon+ CPUs their own cputype.David Daney2010-02-27
| | | | | | | | | | This allows us to treat them differently at runtime. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/951/ Patchwork: http://patchwork.linux-mips.org/patch/987/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Set __elf_platform for Octeon.David Daney2010-02-27
| | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/892/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Allow the auxv's elf_platform entry to be set.David Daney2010-02-27
| | | | | | | | | | | | | | | The userspace runtime linker uses the elf_platform to find the libraries optimized for the current CPU archecture variant. First we need to allow it to be set to something other than NULL. Follow-on patches will set some values for specific CPUs. GLIBC already does the right thing. The kernel just needs to supply good data. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/891/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Cleanup switches with cases that can be mergedRoel Kluin2010-02-27
| | | | | | | | | Signed-off-by: Roel Kluin <roel.kluin@gmail.com> To: linux-mips@linux-mips.org To: Andrew Morton <akpm@linux-foundation.org> To: LKML <linux-kernel@vger.kernel.org> Patchwork: http://patchwork.linux-mips.org/patch/860/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Decode c0_config4 for large TLBs.David Daney2010-02-27
| | | | | | | | | | For processors that have more than 64 TLBs, we need to decode both config1 and config4 to determine the total number TLBs. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/866/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Don't probe reserved EntryHi bits.David Daney2010-02-10
| | | | | | | | | | | | | The patch that adds cpu_probe_vmbits is erroneously writing to reserved bit 12. Since we are really only probing high bits, don't write this bit with a one. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: Guenter Roeck <guenter.roeck@ericsson.com> Patchwork: http://patchwork.linux-mips.org/patch/949/ Acked-by: Guenter Roeck <guenter.roeck@ericsson.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: 64-bit: Detect virtual memory sizeGuenter Roeck2010-02-02
| | | | | | | | | | | | | | Linux kernel 2.6.32 and later allocate address space from the top of the kernel virtual memory address space. This patch implements virtual memory size detection for 64 bit MIPS CPUs to avoid resulting crashes. Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/935/ Reviewed-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson 2F: Add CPU frequency scaling supportWu Zhangjin2009-12-16
| | | | | | | | | | | | | | | | | | | | Loongson 2F supports CPU clock scaling. When put it into wait mode by setting the frequency as ZERO it will stay in this mode until an external interrupt wakes the CPU again. To enable clock scaling support, an external timer of a known stable rate is required. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: cpufreq@vger.kernel.org, Cc: Dave Jones <davej@redhat.com>, Cc: Dominik Brodowski <linux@dominikbrodowski.net>, Cc: yanh@lemote.com Cc: huhb@lemote.com, Patchwork: http://patchwork.linux-mips.org/patch/660/ Patchwork: http://patchwork.linux-mips.org/patch/751/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SPRAM: Clean up support code a littleChris Dearman2009-11-02
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63xx: Add Broadcom 63xx CPU definitions.Maxime Bizon2009-09-17
| | | | | | | Todo: Nothing ever detects CPU_BCM6338 but the code tests for it anyway. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove useless zero initializations.Ralf Baechle2009-09-17
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: get rid of allow_au1k_waitManuel Lauss2009-09-17
| | | | | | | | | | | | | | | Eliminate the 'allow_au1k_wait' variable. MIPS kernel installs the Alchemy-specific wait code before timer initialization; if the C0 timer must be used for timekeeping the wait function is set to NULL which means no wait implementation is available. As a sideeffect, the 'wait instruction available' output in /proc/cpuinfo now correctly indicates whether 'wait' is usable. Run-tested on DB1200. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.Ralf Baechle2009-06-24
| | | | | | | | | Some of the were relying into smp.h being dragged in by another header which of course is fragile. <asm/cpu-info.h> uses smp_processor_id() only in macros and including smp.h there leads to an include loop, so don't change cpu-info.h. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: unify CPU model constants.Manuel Lauss2009-03-30
| | | | | | | | | | | | | | | | | This patch removes the various CPU_AU1??? model constants in favor of a single CPU_ALCHEMY one. All currently existing Alchemy models are identical in terms of cpu core and cache size/organization. The parts of the mips kernel which need to know the exact CPU revision extract it from the c0_prid register already; and finally nothing else in-tree depends on those any more. Should a new variant with slightly different "company options" and/or "processor revision" bits in c0_prid appear, it will be supported immediately (minus an exact model string in cpuinfo). Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: NEC VR5500 processor support fixupShinya Kuribayashi2009-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | Current VR5500 processor support lacks of some functions which are expected to be configured/synthesized on arch initialization. Here're some VR5500A spec notes: * All execution hazards are handled in hardware. * Once VR5500A stops the operation of the pipeline by WAIT instruction, it could return from the standby mode only when either a reset, NMI request, or all enabled interrupts is/are detected. In other words, if interrupts are disabled by Status.IE=0, it keeps in standby mode even when interrupts are internally asserted. Notes on WAIT: The operation of the processor is undefined if WAIT insn is in the branch delay slot. The operation is also undefined if WAIT insn is executed when Status.EXL and Status.ERL are set to 1. * VR5500A core only implements the Load prefetch. With these changes, it boots fine. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: RTC counter clocksource / clockevent support.Manuel Lauss2009-01-11
| | | | | | | | | | | | Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent device. As a nice side effect, this also enables use of the 'wait' instruction for runtime idle power savings. If the counters aren't enabled/working properly, fall back on the cp0 counter clock code. Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add Cavium OCTEON processor constants and CPU probe.David Daney2009-01-11
| | | | | | | | | | Add OCTEON constants to asm/cpu.h and asm/module.h. Add probe function for Cavium OCTEON CPUs and hook it up. Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Sort out CPU type to name translation.Ralf Baechle2008-10-30
| | | | | | | | | | | | | As noticed by David Daney <ddaney@caviumnetworks.com>, the old long switch statement did not comply with the Linux C coding style. It was also yet another place of code to be changed when adding a new processor type leading to annoying bugs for example in /proc/cpuinfo. Fixed by moving the setting of the CPU type string into the core of the probing code and a few BUG_ON() test to ensure the CPU probing code indeed did its job and removing multiple now redundant tests. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Probe for watch registers on cores of all vendors, not just MTI.Ralf Baechle2008-10-30
| | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: David Daney <ddaney@caviumnetworks.com>
* MIPS: Probe watch registers and report configuration.David Daney2008-10-11
| | | | | | | Probe for watch register characteristics, and report them in /proc/cpuinfo. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Fix SMTC dyntick support.Kevin D. Kissell2008-10-03
| | | | | | | | | | | Rework of SMTC support to make it work with the new clock event system, allowing "tickless" operation, and to make it compatible with the use of the "wait_irqoff" idle loop. The new clocking scheme means that the previously optional IPI instant replay mechanism is now required, and has been made more robust. Signed-off-by: Kevin D. Kissell <kevink@paralogos.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix potential latency problem due to non-atomic cpu_wait.Atsushi Nemoto2008-09-21
| | | | | | | | If an interrupt happened between checking of NEED_RESCHED and WAIT instruction, adjust EPC to restart from checking of NEED_RESCHED. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Move arch/mips/philips to arch/mips/nxpDaniel Laird2008-04-28
| | | | | Signed-off-by: daniel.j.laird <daniel.j.laird@nxp.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add support for MIPS CMP platform.Ralf Baechle2008-04-28
| | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Basic SPRAM supportChris Dearman2008-04-28
| | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix loads of section missmatchesRalf Baechle2008-03-12
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Alchemy: Au1210/Au1250 CPU supportManuel Lauss2008-01-29
| | | | | | | | | | This patch adds IDs for new Au1200 variants: Au1210 and Au1250. They are essentially identical to the Au1200 except for the Au1210 which has a different SoC-ID in the PRId register [bits 31:24]. The Au1250 is a "Au1200 V0.2". Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix shadow register support.Ralf Baechle2007-11-15
| | | | | | | | | | | | | Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add BUG_ON assertion for attempt to run kernel on the wrong CPU type.Franck Bui-Huu2007-10-11
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Make facility to convert CPU types to strings generally available.Ralf Baechle2007-10-11
| | | | | | | So far /proc/cpuinfo has been the only user but human readable processor name are more useful than that for proc. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle2007-10-11
| | | | | | | | | | | It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Add support for BCM47XX CPUs.Aurelien Jarno2007-10-11
| | | | | | | | | | | | | | Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch <mb@bu3sch.de> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Florian Schirmer <jolt@tuxbox.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] 20Kc: Disable use of WAIT instruction.Ralf Baechle2007-09-14
| | | | | | | | Another issue with 20Kc's WAIT, waiting for more details. With the 2.6.23 release immindent simply disable the use of WAIT instead of a more fancy workaround. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Workaround for RM7000 WAIT instruction aka erratum 38Ralf Baechle2007-07-20
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] PMC MSP71xx mips commonMarc St-Jean2007-07-10
| | | | | | | Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang2007-07-10
| | | | | Signed-off-by: Fuxin Zhang <zhangfx@lemote.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Enable support for the userlocal hardware registerRalf Baechle2007-07-10
| | | | | | | | Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix scheduling latency issue on 24K, 34K and 74K coresRalf Baechle2007-07-06
| | | | | | | | | | | | | | | | | | | | | | | The idle loop goes to sleep using the WAIT instruction if !need_resched(). This has is suffering from from a race condition that if if just after need_resched has returned 0 an interrupt might set TIF_NEED_RESCHED but we've just completed the test so go to sleep anyway. This would be trivial to fix by just disabling interrupts during that sequence as in: local_irq_disable(); if (!need_resched()) __asm__("wait"); local_irq_enable(); but the processor architecture leaves it undefined if a processor calling WAIT with interrupts disabled will ever restart its pipeline and indeed some processors have made use of the freedom provided by the architecture definition. This has been resolved and the Config7.WII bit indicates that the use of WAIT is safe on 24K, 24KE and 34K cores. It also is safe on 74K starting revision 2.1.0 so enable the use of WAIT with interrupts disabled for 74K based on a c0_prid of at least that. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] 20K: Handle WAIT related bugs according to errata informationRalf Baechle2007-06-26
| | | | | | | | We used to avoid the WAIT entirely on the 20K but really only need to do this on early revs of the 20K. Without this a 20K was a bit of a power hog. Well, in the lower power power hog category ;-) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Make some __setup functions staticAtsushi Nemoto2007-02-19
| | | | | | | | This fixes some sparse warnings. ("warning: symbol 'foo' was not declared. Should it be static?") Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Include <asm/bugs> to for declaration of check_bugs32.Ralf Baechle2007-02-18
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Whitespace cleanups.Ralf Baechle2007-02-06
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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