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authorDavid Daney <ddaney@caviumnetworks.com>2010-10-07 19:03:45 -0400
committerRalf Baechle <ralf@linux-mips.org>2010-10-29 14:08:37 -0400
commit0e56b3852b1c3be83d1f07a82a86084fabacf789 (patch)
tree3120f4ae30ef5933dc0bc9bf4c9f30ff29a155d6 /arch/mips/kernel/cpu-probe.c
parentf8bf7e688c226ba83b35a1547146e296e14b33c7 (diff)
MIPS: Octeon: Probe for Octeon II CPUs.
The OCTEON II ISA extends the original OCTEON ISA, so give it its own __elf_platform string so optimized libraries can be selected in userspace. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1665/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
-rw-r--r--arch/mips/kernel/cpu-probe.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b1b304ea2128..b9378cd0ce0d 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -187,6 +187,7 @@ void __init check_wait(void)
187 case CPU_BCM6358: 187 case CPU_BCM6358:
188 case CPU_CAVIUM_OCTEON: 188 case CPU_CAVIUM_OCTEON:
189 case CPU_CAVIUM_OCTEON_PLUS: 189 case CPU_CAVIUM_OCTEON_PLUS:
190 case CPU_CAVIUM_OCTEON2:
190 case CPU_JZRISC: 191 case CPU_JZRISC:
191 cpu_wait = r4k_wait; 192 cpu_wait = r4k_wait;
192 break; 193 break;
@@ -953,6 +954,12 @@ platform:
953 if (cpu == 0) 954 if (cpu == 0)
954 __elf_platform = "octeon"; 955 __elf_platform = "octeon";
955 break; 956 break;
957 case PRID_IMP_CAVIUM_CN63XX:
958 c->cputype = CPU_CAVIUM_OCTEON2;
959 __cpu_name[cpu] = "Cavium Octeon II";
960 if (cpu == 0)
961 __elf_platform = "octeon2";
962 break;
956 default: 963 default:
957 printk(KERN_INFO "Unknown Octeon chip!\n"); 964 printk(KERN_INFO "Unknown Octeon chip!\n");
958 c->cputype = CPU_UNKNOWN; 965 c->cputype = CPU_UNKNOWN;