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* MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructionsMarkos Chandras2015-02-17
| | | | | | MIPS R6 uses the <R6 sdc2 opcode for the new BNEZC and JIALC instructions Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 BEQZC and JIC instructionsMarkos Chandras2015-02-17
| | | | | | MIPS R6 uses the <R6 ldc2 opcode for the new BEQZC and JIC instructions Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 BALC instructionMarkos Chandras2015-02-17
| | | | | | MIPS R6 uses the <R6 swc2 opcode for the new BALC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructionsMarkos Chandras2015-02-17
| | | | | | | MIPS R6 uses the <R6 DADDI opcode for the new BNVC, BNEC and BNEZLAC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructionsMarkos Chandras2015-02-17
| | | | | | | MIPS R6 uses the <R6 ADDI opcode for the new BOVC, BEQC and BEQZALC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 branch compact (BC) instructionMarkos Chandras2015-02-17
| | | | | | MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the BC1{EQ,NE}Z FPU instructionsMarkos Chandras2015-02-17
| | | | | | | | | MIPS R6 introduced the following two branch instructions for COP1: BC1EQZ: Branch if Cop1 (FPR) Register Bit 0 is Equal to Zero BC1NEZ: Branch if Cop1 (FPR) Register Bit 0 is Not Equal to Zero Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: mm: Add MIPS R6 instruction encodingsLeonid Yegoshin2015-02-16
| | | | | | | | MIPS R6 defines new opcodes for ll, sc, cache and pref instructions so we need to take these into consideration in the micro-assembler. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Add MFHC0 and MTHC0 instructions to uasm.Steven J. Hill2014-11-24
| | | | | | | | | New instructions for Extended Physical Addressing (XPA) functionality. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8453/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add SLT uasm instructionMarkos Chandras2014-06-26
| | | | | | | | | | It will be used later on by bpf-jit Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/7120/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add mflo uasm instructionMarkos Chandras2014-05-30
| | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: uasm: Add mul uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6736/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add wsbh uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6732/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add sltu uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6731/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add mfhi uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add divu uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add srlv uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Fixed conflict due to other preceeding conflicts.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6726/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add sllv uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Fixed conflict with 49e9529b9d43773307b8c73bd251b71784830c3d [MIPS: uasm: add jalr instruction]. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6725/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'wip-mips-pm' of https://github.com/paulburton/linux into ↵Ralf Baechle2014-05-29
|\ | | | | | | mips-for-linux-next
| * MIPS: inst.h: define microMIPS wait opPaul Burton2014-05-28
| | | | | | | | | | | | | | The opcode for the wait instruction within POOL32AXf was missing. This patch adds it for use by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: inst.h: define microMIPS sync opPaul Burton2014-05-28
| | | | | | | | | | | | | | The opcode for the sync instruction within POOL32AXf was missing. This patch adds it for use by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: inst.h: define MT yield opPaul Burton2014-05-28
| | | | | | | | | | | | | | The opcode for the MT ASE yield instruction within the spec3 group was missing. This patch adds it for use by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: inst.h: define COP0 wait opPaul Burton2014-05-28
| | | | | | | | | | | | | | The func field for the wait instruction was missing from inst.h - this patch adds it. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | MIPS: Move definition of __BITFIELD_FIELD to sharable header.Ralf Baechle2014-05-21
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: inst.h: Rename BITFIELD_FIELD to __BITFIELD_FIELD.Ralf Baechle2014-05-12
|/ | | | | | | <uapi/asm/inst.h> is exported to userland so the macro name BITFIELD_FIELD pollutes the namespace. Prefix the name with __ fixes this. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch '3.14-fixes' into mips-for-linux-nextRalf Baechle2014-03-31
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| * MIPS: math-emu: Fix prefx detection and COP1X function field definitionDeng-Cheng Zhu2014-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running applications which contain the instruction "prefx" on FPU-less CPUs, a message "Illegal instruction" will be seen. This instruction is supposed to be ignored by the FPU emulator. However, its current detection and function field encoding are incorrect. This patch fix the issue. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6608/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: uapi: inst: Add instruction format for SPECIAL3 instructionsLeonid Yegoshin2014-03-26
| | | | | | | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* | MIPS: uapi: inst: Add new EVA opcodesLeonid Yegoshin2014-03-26
|/ | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: microMIPS: mfhc1 & mthc1 support for the FPU emulatorSteven J. Hill2014-01-13
| | | | | | | | | | | | | This patch adds support for microMIPS encodings of the mfhc1 & mthc1 instructions introduced in release 2 of the mips32 & mips64 architectures, converting them to their mips32 equivalents for the FPU emulator. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6110/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Add mfhc1 & mthc1 support.Leonid Yegoshin2014-01-13
| | | | | | | | | | | | | | | | This patch adds support for the mfhc1 & mthc1 instructions to the FPU emulator. These instructions were introduced in release 2 of the MIPS32 & MIPS64 architectures and allow access to the most significant 32 bits of a 64-bit FP register. [ralf@linux-mips.org: Fix ifdef hell added by original patch.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6112/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: microMIPS: Fix POOL16C minor opcode enumTony Wu2013-06-21
| | | | | | | | | | | | | As pointed out by Maciej, POOL16C minor opcodes were mostly shifted by one bit. Correct those opcodes, and also add jraddiusp to the enum. Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: david.daney@cavium.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5527/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: MIPS16e: Add instruction formats.Steven J. Hill2013-05-09
| | | | | | | Add structures for all the MIPS16e instructions. Also add the enumerations for all the bit fields for opcodes, functions, etc. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
* MIPS: microMIPS: Floating point support.Leonid Yegoshin2013-05-09
| | | | | | | Add logic needed to do floating point emulation in microMIPS mode. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Steven J. Hill <Steven. Hill@imgtec.com>
* MIPS: microMIPS: Add instruction formats.Steven J. Hill2013-05-01
| | | | | | | | | | | | | | Add structures for all the microMIPS instructions. Also add the enumerations for all the bit fields for opcodes, functions, etc. Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: kevink@paralogos.com Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/4921/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit d7f19e43a4337d4d40ff5e241172912130d06a4c)
* MIPS: Whitespace cleanup.Ralf Baechle2013-02-01
| | | | | | | | Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: inst.h: Add MDMX and paired single instruction aka MIPS-3D formats.Ralf Baechle2013-02-01
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: inst.h: Eleminate per endianess structure definitions.Ralf Baechle2013-02-01
| | | | | | This makes space for further growth of the header without excessive bloat. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: UAPI: Split inst.h into exported and kernel-only part.Ralf Baechle2013-02-01
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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