Commit message (Expand) | Author | Age | |
---|---|---|---|
* | MIPS: Alchemy: remove SOC_AU1X00 in favor of MIPS_ALCHEMY | Manuel Lauss | 2010-08-05 |
* | MIPS: Loongson 2 needs no hazard barriers. | Zhang Le | 2009-05-14 |
* | MIPS: Alchemy: MIPS hazard workarounds are not required. | Manuel Lauss | 2009-03-30 |
* | MIPS: NEC VR5500 processor support fixup | Shinya Kuribayashi | 2009-03-11 |
* | MIPS: For Cavium OCTEON handle hazards as per the R10000 handling. | David Daney | 2009-01-11 |
* | MIPS: Move headfiles to new location below arch/mips/include | Ralf Baechle | 2008-10-11 |