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path: root/arch/mips/include/asm/cpu-features.h
Commit message (Expand)AuthorAge
* MIPS: Detect the MSA ASEPaul Burton2014-03-26
* MIPS: features: Add initial support for Segmentation Control registersSteven J. Hill2014-01-22
* MIPS: features: Add initial support for TLBINVF capable coresLeonid Yegoshin2014-01-22
* MIPS: cpu-features.h: s/MIPS53/MIPS64/Maciej W. Rozycki2013-09-24
* MIPS: Optimize current_cpu_type() for better code.Ralf Baechle2013-09-17
* MIPS: oprofile: Fix BUG due to smp_processor_id() in preemptible code.Ralf Baechle2013-08-05
* MIPS: Cleanup indentation and whitespaceTony Wu2013-07-01
* MIPS: Only set cpu_has_mmips if SYS_SUPPORTS_MICROMIPSDavid Daney2013-07-01
* MIPS: Get rid of MIPS I flag and test macros.Ralf Baechle2013-07-01
* MIPS: Build uasm-generated code only once to avoid CPU Hotplug problemHuacai Chen2013-05-07
* Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-j...Ralf Baechle2013-02-21
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| * MIPS: Probe for and report hardware virtualization support.David Daney2013-02-19
| * MIPS: Add support for the M14KEc core.Steven J. Hill2013-02-16
* | MIPS: Add printing of ISA version in cpuinfo.Steven J. Hill2013-02-15
* | MIPS: Whitespace cleanup.Ralf Baechle2013-02-01
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* MIPS: Add detection of DSP ASE Revision 2.Steven J. Hill2012-10-11
* MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)Al Cooper2012-10-11
* MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.Steven J. Hill2012-09-13
* MIPS: Add base architecture support for RI and XI.Steven J. Hill2012-09-13
* MIPS: Update comment for cpu_has_clo_clzRalf Baechle2010-08-05
* MIPS: Implement Read Inhibit/eXecute InhibitDavid Daney2010-02-27
* MIPS: 64-bit: Detect virtual memory sizeGuenter Roeck2010-02-02
* MIPS: Allow kernel use of LL/SC to be separate from the presence of LL/SC.David Daney2009-09-17
* MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.David Daney2009-06-17
* MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.David Daney2009-06-17
* MIPS: Enable CLO / CLZ instructions via separate CPU propertyRalf Baechle2009-05-14
* MIPS: Hook Cavium OCTEON cache init into cache.cDavid Daney2009-01-11
* MIPS: New feature test macro cpu_has_mips_rRalf Baechle2008-10-30
* MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle2008-10-11