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| | * | | | | | ARM: mm: proc-arm922: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: proc-arm920: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: proc-arm7tdmi: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: proc-arm740: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: proc-arm720: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: proc-arm6_7: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: proc-arm1026: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: proc-arm1022: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: proc-arm1020e: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: proc-arm1020: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: cache-v7: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: cache-v6: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: cache-v4wt: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: cache-v4wb: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: cache-v4: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: cache-v3: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: cache-fa: Use the new processor struct macrosDave Martin2011-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Martin <dave.martin@linaro.org>
| | * | | | | | ARM: mm: proc-macros: Add generic proc/cache/tlb struct definition macrosDave Martin2011-07-07
| | | |_|/ / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds some generic macros to reduce boilerplate when declaring certain common structures in arch/arm/mm/*.S Thanks to Russell King for outlining what the define_processor_functions macro could look like. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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| *-------------. | | | | | Merge branches 'btc', 'dma', 'entry', 'fixes', 'linker-layout', 'misc', ↵Russell King2011-07-22
| |\ \ \ \ \ \ \ \| | | | | | | | | | |_|_|_|_|/ / / / | | | | |/| | | | | / / / | | | |_|_|_|_|_|_|/ / / | | |/| | | | | | | | / | | | | | | | | |_|_|/ | | | | | | | |/| | | 'mmci', 'suspend' and 'vfp' into for-next
| | | | | | | | * | | ARM: pm: arrange for cpu_proc_init() to be called on resumeRussell King2011-06-24
| | | | | | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpu_proc_init() does processor specific initialization, which we do at boot time. We have been omitting to do this on resume, which causes some of this initialization to be skipped. We've also been skipping this on SMP initialization too. Ensure that cpu_proc_init() is always called appropriately by moving it into cpu_init(), and move cpu_init() to a more appropriate point in the boot initialization. Tested-by: Kevin Hilman <khilman@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | | ARM: 7000/1: LPAE: Use long long printk format for displaying the pudCatalin Marinas2011-07-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently using just long but this is not enough for the LPAE format (64-bit entries). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | | ARM: 6995/2: mm: remove unnecessary cache flush on v6 copypageHeechul Yun2011-07-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally introduced to maintain coherency between icache and dcache in v6 nonaliasing mode. This is now handled by __sync_icache_dcache since c0177800, therefore unnecessary in this function. Signed-off-by: Heechul Yun <heechul@illinois.edu> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | | ARM: 6996/1: mm: Poison freed init memoryStephen Boyd2011-07-08
| | | | | | | |_|/ | | | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Poisoning __init marked memory can be useful when tracking down obscure memory corruption bugs. Therefore, poison init memory with 0xe7fddef0 to catch bugs earlier. The poison value is an undefined instruction in ARM mode and branch to an undefined instruction in Thumb mode. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | | ARM: vmlinux.lds: move init sections between text and data sectionsRussell King2011-07-07
| | | | | | |_|/ | | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Place the init sections between the text and data sections. This means all code is grouped together at the beginning of the kernel image, and all data is at the end of the image. This avoids problems with the 24-bit branch instruction relocations becoming invalid with large initramfs images. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: entry: data abort: ensure r5 is preserved by abort functionsRussell King2011-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: entry: data abort: always use r6 for offsetRussell King2011-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: entry: data abort: use r2 as base of pt_regs rather than stackRussell King2011-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we pass r2 into these helper functions as the pointer to pt_regs, use r2 as the base of the registers on the stack rather than using the stack pointer directly. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: entry: data abort: tail-call the main data abort handlerRussell King2011-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tail-call the main C data abort handler code from the per-CPU helper code. Update the comments in the code wrt the new calling and return register state. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: entry: data abort: avoid using r2 in abort helpersRussell King2011-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to pass the pt_regs pointer in to these functions ready for tail-calling the abort handler. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: entry: data abort: arrange for CPU abort helpers to take pc/psr in r4/r5Russell King2011-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Re-jig the CPU abort helpers to take the PC/PSR in r4/r5 rather than r2/r3. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: entry: prefetch abort: tail-call the main prefetch abort handlerRussell King2011-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tail-call the main C prefetch abort handler code from the per-CPU helper code. Also note that the helper function becomes ABI compliant in terms of the registers preserved. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: entry: avoid enabling interrupts in prefetch/data abort handlersRussell King2011-07-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid enabling interrupts if the parent context had interrupts enabled in the abort handler assembly code, and move this into the breakpoint/ page/alignment fault handlers instead. This gets rid of some special-casing for the breakpoint fault handlers from the low level abort handler path. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: entry: prefetch abort helper: pass aborted pc in r4 rather than r0Russell King2011-06-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This avoids unnecessary instructions for CPUs which implement the IFAR (instruction fault address register). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: entry: abort-macro: simplify do_ldrd_abortRussell King2011-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can test bits 27:25 and 20 of the instruction at the same time; there's no need to separate out the check of bit 20. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | | | ARM: entry: abort-macro: specify registers to be used for macrosRussell King2011-06-29
| | | | |/ / / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Require all callers of abort macros to specify the registers to be used. This improves the documentation at the callsites as to which registers are being used by this assembly code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * / | | | ARM: dma: replace ISA_DMA_THRESHOLD with a variableRussell King2011-07-12
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ISA_DMA_THRESHOLD has been unused by non-arch code, so lets now get rid of it from ARM by replacing it with arm_dma_zone_mask. Move dma_supported() and dma_set_mask() out of line, and have dma_supported() check this new variable instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | / ARM: btc: avoid invalidating the branch target cache on kernel TLB maintanenceRussell King2011-07-19
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kernel space needs very little in the way of BTC maintanence as most mappings which are created and destroyed are non-executable, and so could never enter the instruction stream. The case which does warrant BTC maintanence is when a module is loaded. This creates a new executable mapping, but at that point the pages have not been initialized with code and data, so at that point they contain unpredictable information. Invalidating the BTC at this stage serves little useful purpose. Before we execute module code, we call flush_icache_range(), which deals with the BTC maintanence requirements. This ensures that we have a BTC maintanence operation before we execute code via the newly created mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | | Merge branch 'perf-core-for-linus' of ↵Linus Torvalds2011-07-22
|\ \ \ \ \ | |_|_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (123 commits) perf: Remove the nmi parameter from the oprofile_perf backend x86, perf: Make copy_from_user_nmi() a library function perf: Remove perf_event_attr::type check x86, perf: P4 PMU - Fix typos in comments and style cleanup perf tools: Make test use the preset debugfs path perf tools: Add automated tests for events parsing perf tools: De-opt the parse_events function perf script: Fix display of IP address for non-callchain path perf tools: Fix endian conversion reading event attr from file header perf tools: Add missing 'node' alias to the hw_cache[] array perf probe: Support adding probes on offline kernel modules perf probe: Add probed module in front of function perf probe: Introduce debuginfo to encapsulate dwarf information perf-probe: Move dwarf library routines to dwarf-aux.{c, h} perf probe: Remove redundant dwarf functions perf probe: Move strtailcmp to string.c perf probe: Rename DIE_FIND_CB_FOUND to DIE_FIND_CB_END tracing/kprobe: Update symbol reference when loading module tracing/kprobes: Support module init function probing kprobes: Return -ENOENT if probe point doesn't exist ...
| * | | | perf: Remove the nmi parameter from the swevent and overflow interfacePeter Zijlstra2011-07-01
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nmi parameter indicated if we could do wakeups from the current context, if not, we would set some state and self-IPI and let the resulting interrupt do the wakeup. For the various event classes: - hardware: nmi=0; PMI is in fact an NMI or we run irq_work_run from the PMI-tail (ARM etc.) - tracepoint: nmi=0; since tracepoint could be from NMI context. - software: nmi=[0,1]; some, like the schedule thing cannot perform wakeups, and hence need 0. As one can see, there is very little nmi=1 usage, and the down-side of not using it is that on some platforms some software events can have a jiffy delay in wakeup (when arch_irq_work_raise isn't implemented). The up-side however is that we can remove the nmi parameter and save a bunch of conditionals in fast paths. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Michael Cree <mcree@orcon.net.nz> Cc: Will Deacon <will.deacon@arm.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> Cc: Anton Blanchard <anton@samba.org> Cc: Eric B Munson <emunson@mgebm.net> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: David S. Miller <davem@davemloft.net> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Jason Wessel <jason.wessel@windriver.com> Cc: Don Zickus <dzickus@redhat.com> Link: http://lkml.kernel.org/n/tip-agjev8eu666tvknpb3iaj0fg@git.kernel.org Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | | ARM: 6987/1: l2x0: fix disabling function to avoid deadlockWill Deacon2011-07-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The l2x0_disable function attempts to writel with the l2x0_lock held. This results in deadlock when the writel contains an outer_sync call for the platform since the l2x0_lock is already held by the disable function. A further problem is that disabling the L2 without flushing it first can lead to the spin_lock operation becoming visible after the spin_unlock, causing any subsequent L2 maintenance to deadlock. This patch replaces the writel with a call to writel_relaxed in the disabling code and adds a flush before disabling in the control register, preventing livelock from occurring. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: move memory layout sanity checking before meminfo initializationRussell King2011-07-05
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure that the meminfo array is sanity checked before we pass the memory to memblock. This helps to ensure that memblock and meminfo agree on the dimensions of memory, especially when more memory is passed than the kernel can deal with. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: pm: ensure ARMv7 CPUs save and restore the TLS registerRussell King2011-06-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure that the TLS register is saved and restored over a suspend cycle, so that userspace programs don't see a corrupted TLS value. Tested-by: Kevin Hilman <khilman@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: pm: proc-v7: fix missing struct processor pointers for suspend codeRussell King2011-06-24
|/ / | | | | | | | | | | | | | | | | Add the missing suspend/resume pointers for the suspend code. This is needed when building for multiple CPUs. Tested-by: Kevin Hilman <khilman@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: initrd: disable initrds outside of memoryRussell King2011-06-10
| | | | | | | | | | | | | | | | We can't cope with initrds outside of memory, so check that the initrd is within some declared memory to the kernel before using it. Otherwise we're likely to OOPS during boot. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Revert "ARM: 6944/1: mm: allow ASID 0 to be allocated to tasks"Russell King2011-06-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 45b95235b0ac86cef2ad4480b0618b8778847479. Will Deacon reports that: In 52af9c6c ("ARM: 6943/1: mm: use TTBR1 instead of reserved context ID") I updated the ASID rollover code to use only the kernel page tables whilst updating the ASID. Unfortunately, the code to restore the user page tables was part of a later patch which isn't yet in mainline, so this leaves the code quite broken. We're also in the process of eliminating __ARCH_WANT_INTERRUPTS_ON_CTXSW from ARM, so lets revert these until we can properly sort out what we're doing with the context switching. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Revert "ARM: 6943/1: mm: use TTBR1 instead of reserved context ID"Russell King2011-06-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 52af9c6cd863fe37d1103035ec7ee22ac1296458. Will Deacon reports that: In 52af9c6c ("ARM: 6943/1: mm: use TTBR1 instead of reserved context ID") I updated the ASID rollover code to use only the kernel page tables whilst updating the ASID. Unfortunately, the code to restore the user page tables was part of a later patch which isn't yet in mainline, so this leaves the code quite broken. We're also in the process of eliminating __ARCH_WANT_INTERRUPTS_ON_CTXSW from ARM, so lets revert these until we can properly sort out what we're doing with the ARM context switching. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6951/1: include .bss in memory layout informationRabin Vincent2011-06-06
| | | | | | | | | | | | | | | | The "Virtual memory kernel layout" message at startup already prints .text and .data. Print .bss too. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6948/1: Fix .size directives for __arm{7,9}tdmi_proc_infoBen Hutchings2011-06-06
|/ | | | | | | | | | | | | gas used to accept (and ignore?) .size directives which referred to undefined symbols, as these do. In binutils 2.21 these are treated as fatal errors. The issue in proc-arm7tdmi.S was also fixed independently by Peter Chubb. Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
*-. Merge branches 'devel', 'devel-stable' and 'fixes' into for-linusRussell King2011-05-27
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| | * ARM: 6944/1: mm: allow ASID 0 to be allocated to tasksWill Deacon2011-05-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that ASID 0 is no longer used as a reserved value, allow it to be allocated to tasks. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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