ARM: entry: data abort: use r2 as base of pt_regs rather than stack

Now that we pass r2 into these helper functions as the pointer to pt_regs, use r2 as the base of the registers on the stack rather than using the stack pointer directly. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
author: Russell King <rmk+kernel@arm.linux.org.uk> 2011-06-27 04:52:54 -0400
committer: Russell King <rmk+kernel@arm.linux.org.uk> 2011-07-02 05:56:11 -0400
commit: e22c12f9146d50ee6b0cf97db46b3310409f64e6 (patch)
tree: 986b832e871dc9703d3b318fbf7c59f21f5c6a85 /arch/arm/mm
parent: da7404725781bc7c736e10cae5521e5604e222a5 (diff)
2 files changed, 19 insertions, 19 deletions
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index d432f31cdab5..921aaab0c8c5 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -73,11 +73,11 @@ ENTRY(v4t_late_abort)
        add     r6, r6, r6, lsr #4
        and     r6, r6, #15                     @ r6 = no. of registers to transfer.
        and     r5, r8, #15 << 16               @ Extract 'n' from instruction
-        ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
+        ldr     r7, [r2, r5, lsr #14]           @ Get register 'Rn'
        tst     r8, #1 << 23                    @ Check U bit
        subne   r7, r7, r6, lsl #2              @ Undo increment
        addeq   r7, r7, r6, lsl #2              @ Undo decrement
-        str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
+        str     r7, [r2, r5, lsr #14]           @ Put register 'Rn'
        b       do_DataAbort
 .data_arm_lateldrhpre:
@@ -88,14 +88,14 @@ ENTRY(v4t_late_abort)
        tst     r8, #1 << 22                    @ if (immediate offset)
        andne   r6, r8, #0xf00                  @ { immediate high nibble
        orrne   r6, r5, r6, lsr #4              @   combine nibbles } else
-        ldreq   r6, [sp, r5, lsl #2]            @ { load Rm value }
+        ldreq   r6, [r2, r5, lsl #2]            @ { load Rm value }
 .data_arm_apply_r6_and_rn:
        and     r5, r8, #15 << 16               @ Extract 'n' from instruction
-        ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
+        ldr     r7, [r2, r5, lsr #14]           @ Get register 'Rn'
        tst     r8, #1 << 23                    @ Check U bit
        subne   r7, r7, r6                      @ Undo incrmenet
        addeq   r7, r7, r6                      @ Undo decrement
-        str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
+        str     r7, [r2, r5, lsr #14]           @ Put register 'Rn'
        b       do_DataAbort
 .data_arm_lateldrpreconst:
@@ -105,11 +105,11 @@ ENTRY(v4t_late_abort)
        movs    r9, r8, lsl #20                 @ Get offset
        beq     do_DataAbort                    @ zero -> no fixup
        and     r5, r8, #15 << 16               @ Extract 'n' from instruction
-        ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
+        ldr     r7, [r2, r5, lsr #14]           @ Get register 'Rn'
        tst     r8, #1 << 23                    @ Check U bit
        subne   r7, r7, r9, lsr #20             @ Undo increment
        addeq   r7, r7, r9, lsr #20             @ Undo decrement
-        str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
+        str     r7, [r2, r5, lsr #14]           @ Put register 'Rn'
        b       do_DataAbort
 .data_arm_lateldrprereg:
@@ -117,7 +117,7 @@ ENTRY(v4t_late_abort)
        beq     do_DataAbort                    @ no writeback -> no fixup
 .data_arm_lateldrpostreg:
        and     r7, r8, #15                     @ Extract 'm' from instruction
-        ldr     r6, [sp, r7, lsl #2]            @ Get register 'Rm'
+        ldr     r6, [r2, r7, lsl #2]            @ Get register 'Rm'
        mov     r5, r8, lsr #7                  @ get shift count
        ands    r5, r5, #31
        and     r7, r8, #0x70                   @ get shift type
@@ -201,11 +201,11 @@ ENTRY(v4t_late_abort)
        movs    r7, r8, lsr #9                  @ C = r8 bit 8 (R bit)
        adc     r6, r6, r6, lsr #4              @ high + low nibble + R bit
        and     r6, r6, #15                     @ number of regs to transfer
-        ldr     r7, [sp, #13 << 2]
+        ldr     r7, [r2, #13 << 2]
        tst     r8, #1 << 11
        addeq   r7, r7, r6, lsl #2              @ increment SP if PUSH
        subne   r7, r7, r6, lsl #2              @ decrement SP if POP
-        str     r7, [sp, #13 << 2]
+        str     r7, [r2, #13 << 2]
        b       do_DataAbort
 .data_thumb_ldmstm:
@@ -217,8 +217,8 @@ ENTRY(v4t_late_abort)
        add     r6, r6, r9, lsr #2
        add     r6, r6, r6, lsr #4
        and     r5, r8, #7 << 8
-        ldr     r7, [sp, r5, lsr #6]
+        ldr     r7, [r2, r5, lsr #6]
        and     r6, r6, #15                     @ number of regs to transfer
        sub     r7, r7, r6, lsl #2              @ always decrement
-        str     r7, [sp, r5, lsr #6]
+        str     r7, [r2, r5, lsr #6]
        b       do_DataAbort
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index d755d5b83898..141906eae260 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -96,20 +96,20 @@ ENTRY(cpu_arm6_data_abort)
        add     r6, r6, r6, lsr #4
        and     r6, r6, #15                     @ r6 = no. of registers to transfer.
        and     r5, r8, #15 << 16               @ Extract 'n' from instruction
-        ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
+        ldr     r7, [r2, r5, lsr #14]           @ Get register 'Rn'
        tst     r8, #1 << 23                    @ Check U bit
        subne   r7, r7, r6, lsl #2              @ Undo increment
        addeq   r7, r7, r6, lsl #2              @ Undo decrement
-        str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
+        str     r7, [r2, r5, lsr #14]           @ Put register 'Rn'
        b       do_DataAbort
 .data_arm_apply_r6_and_rn:
        and     r5, r8, #15 << 16               @ Extract 'n' from instruction
-        ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
+        ldr     r7, [r2, r5, lsr #14]           @ Get register 'Rn'
        tst     r8, #1 << 23                    @ Check U bit
        subne   r7, r7, r6                      @ Undo incrmenet
        addeq   r7, r7, r6                      @ Undo decrement
-        str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
+        str     r7, [r2, r5, lsr #14]           @ Put register 'Rn'
        b       do_DataAbort
 .data_arm_lateldrpreconst:
@@ -119,11 +119,11 @@ ENTRY(cpu_arm6_data_abort)
        movs    r9, r8, lsl #20                 @ Get offset
        beq     do_DataAbort                    @ zero -> no fixup
        and     r5, r8, #15 << 16               @ Extract 'n' from instruction
-        ldr     r7, [sp, r5, lsr #14]           @ Get register 'Rn'
+        ldr     r7, [r2, r5, lsr #14]           @ Get register 'Rn'
        tst     r8, #1 << 23                    @ Check U bit
        subne   r7, r7, r9, lsr #20             @ Undo increment
        addeq   r7, r7, r9, lsr #20             @ Undo decrement
-        str     r7, [sp, r5, lsr #14]           @ Put register 'Rn'
+        str     r7, [r2, r5, lsr #14]           @ Put register 'Rn'
        b       do_DataAbort
 .data_arm_lateldrprereg:
@@ -131,7 +131,7 @@ ENTRY(cpu_arm6_data_abort)
        beq     do_DataAbort                    @ no writeback -> no fixup
 .data_arm_lateldrpostreg:
        and     r7, r8, #15                     @ Extract 'm' from instruction
-        ldr     r6, [sp, r7, lsl #2]            @ Get register 'Rm'
+        ldr     r6, [r2, r7, lsl #2]            @ Get register 'Rm'
        mov     r5, r8, lsr #7                  @ get shift count
        ands    r5, r5, #31
        and     r7, r8, #0x70                   @ get shift type
author	Russell King <rmk+kernel@arm.linux.org.uk>	2011-06-27 04:52:54 -0400
committer	Russell King <rmk+kernel@arm.linux.org.uk>	2011-07-02 05:56:11 -0400
commit	e22c12f9146d50ee6b0cf97db46b3310409f64e6 (patch)
tree	986b832e871dc9703d3b318fbf7c59f21f5c6a85 /arch/arm/mm
parent	da7404725781bc7c736e10cae5521e5604e222a5 (diff)

diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S index d432f31cdab5..921aaab0c8c5 100644 --- a/arch/arm/mm/abort-lv4t.S +++ b/arch/arm/mm/abort-lv4t.S
@@ -73,11 +73,11 @@ ENTRY(v4t_late_abort)
73	add r6, r6, r6, lsr #4	73	add r6, r6, r6, lsr #4
74	and r6, r6, #15 @ r6 = no. of registers to transfer.	74	and r6, r6, #15 @ r6 = no. of registers to transfer.
75	and r5, r8, #15 << 16 @ Extract 'n' from instruction	75	and r5, r8, #15 << 16 @ Extract 'n' from instruction
76	ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'	76	ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
77	tst r8, #1 << 23 @ Check U bit	77	tst r8, #1 << 23 @ Check U bit
78	subne r7, r7, r6, lsl #2 @ Undo increment	78	subne r7, r7, r6, lsl #2 @ Undo increment
79	addeq r7, r7, r6, lsl #2 @ Undo decrement	79	addeq r7, r7, r6, lsl #2 @ Undo decrement
80	str r7, [sp, r5, lsr #14] @ Put register 'Rn'	80	str r7, [r2, r5, lsr #14] @ Put register 'Rn'
81	b do_DataAbort	81	b do_DataAbort
82		82
83	.data_arm_lateldrhpre:	83	.data_arm_lateldrhpre:
@@ -88,14 +88,14 @@ ENTRY(v4t_late_abort)
88	tst r8, #1 << 22 @ if (immediate offset)	88	tst r8, #1 << 22 @ if (immediate offset)
89	andne r6, r8, #0xf00 @ { immediate high nibble	89	andne r6, r8, #0xf00 @ { immediate high nibble
90	orrne r6, r5, r6, lsr #4 @ combine nibbles } else	90	orrne r6, r5, r6, lsr #4 @ combine nibbles } else
91	ldreq r6, [sp, r5, lsl #2] @ { load Rm value }	91	ldreq r6, [r2, r5, lsl #2] @ { load Rm value }
92	.data_arm_apply_r6_and_rn:	92	.data_arm_apply_r6_and_rn:
93	and r5, r8, #15 << 16 @ Extract 'n' from instruction	93	and r5, r8, #15 << 16 @ Extract 'n' from instruction
94	ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'	94	ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
95	tst r8, #1 << 23 @ Check U bit	95	tst r8, #1 << 23 @ Check U bit
96	subne r7, r7, r6 @ Undo incrmenet	96	subne r7, r7, r6 @ Undo incrmenet
97	addeq r7, r7, r6 @ Undo decrement	97	addeq r7, r7, r6 @ Undo decrement
98	str r7, [sp, r5, lsr #14] @ Put register 'Rn'	98	str r7, [r2, r5, lsr #14] @ Put register 'Rn'
99	b do_DataAbort	99	b do_DataAbort
100		100
101	.data_arm_lateldrpreconst:	101	.data_arm_lateldrpreconst:
@@ -105,11 +105,11 @@ ENTRY(v4t_late_abort)
105	movs r9, r8, lsl #20 @ Get offset	105	movs r9, r8, lsl #20 @ Get offset
106	beq do_DataAbort @ zero -> no fixup	106	beq do_DataAbort @ zero -> no fixup
107	and r5, r8, #15 << 16 @ Extract 'n' from instruction	107	and r5, r8, #15 << 16 @ Extract 'n' from instruction
108	ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'	108	ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
109	tst r8, #1 << 23 @ Check U bit	109	tst r8, #1 << 23 @ Check U bit
110	subne r7, r7, r9, lsr #20 @ Undo increment	110	subne r7, r7, r9, lsr #20 @ Undo increment
111	addeq r7, r7, r9, lsr #20 @ Undo decrement	111	addeq r7, r7, r9, lsr #20 @ Undo decrement
112	str r7, [sp, r5, lsr #14] @ Put register 'Rn'	112	str r7, [r2, r5, lsr #14] @ Put register 'Rn'
113	b do_DataAbort	113	b do_DataAbort
114		114
115	.data_arm_lateldrprereg:	115	.data_arm_lateldrprereg:
@@ -117,7 +117,7 @@ ENTRY(v4t_late_abort)
117	beq do_DataAbort @ no writeback -> no fixup	117	beq do_DataAbort @ no writeback -> no fixup
118	.data_arm_lateldrpostreg:	118	.data_arm_lateldrpostreg:
119	and r7, r8, #15 @ Extract 'm' from instruction	119	and r7, r8, #15 @ Extract 'm' from instruction
120	ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'	120	ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
121	mov r5, r8, lsr #7 @ get shift count	121	mov r5, r8, lsr #7 @ get shift count
122	ands r5, r5, #31	122	ands r5, r5, #31
123	and r7, r8, #0x70 @ get shift type	123	and r7, r8, #0x70 @ get shift type
@@ -201,11 +201,11 @@ ENTRY(v4t_late_abort)
201	movs r7, r8, lsr #9 @ C = r8 bit 8 (R bit)	201	movs r7, r8, lsr #9 @ C = r8 bit 8 (R bit)
202	adc r6, r6, r6, lsr #4 @ high + low nibble + R bit	202	adc r6, r6, r6, lsr #4 @ high + low nibble + R bit
203	and r6, r6, #15 @ number of regs to transfer	203	and r6, r6, #15 @ number of regs to transfer
204	ldr r7, [sp, #13 << 2]	204	ldr r7, [r2, #13 << 2]
205	tst r8, #1 << 11	205	tst r8, #1 << 11
206	addeq r7, r7, r6, lsl #2 @ increment SP if PUSH	206	addeq r7, r7, r6, lsl #2 @ increment SP if PUSH
207	subne r7, r7, r6, lsl #2 @ decrement SP if POP	207	subne r7, r7, r6, lsl #2 @ decrement SP if POP
208	str r7, [sp, #13 << 2]	208	str r7, [r2, #13 << 2]
209	b do_DataAbort	209	b do_DataAbort
210		210
211	.data_thumb_ldmstm:	211	.data_thumb_ldmstm:
@@ -217,8 +217,8 @@ ENTRY(v4t_late_abort)
217	add r6, r6, r9, lsr #2	217	add r6, r6, r9, lsr #2
218	add r6, r6, r6, lsr #4	218	add r6, r6, r6, lsr #4
219	and r5, r8, #7 << 8	219	and r5, r8, #7 << 8
220	ldr r7, [sp, r5, lsr #6]	220	ldr r7, [r2, r5, lsr #6]
221	and r6, r6, #15 @ number of regs to transfer	221	and r6, r6, #15 @ number of regs to transfer
222	sub r7, r7, r6, lsl #2 @ always decrement	222	sub r7, r7, r6, lsl #2 @ always decrement
223	str r7, [sp, r5, lsr #6]	223	str r7, [r2, r5, lsr #6]
224	b do_DataAbort	224	b do_DataAbort


diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S index d755d5b83898..141906eae260 100644 --- a/arch/arm/mm/proc-arm6_7.S +++ b/arch/arm/mm/proc-arm6_7.S
@@ -96,20 +96,20 @@ ENTRY(cpu_arm6_data_abort)
96	add r6, r6, r6, lsr #4	96	add r6, r6, r6, lsr #4
97	and r6, r6, #15 @ r6 = no. of registers to transfer.	97	and r6, r6, #15 @ r6 = no. of registers to transfer.
98	and r5, r8, #15 << 16 @ Extract 'n' from instruction	98	and r5, r8, #15 << 16 @ Extract 'n' from instruction
99	ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'	99	ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
100	tst r8, #1 << 23 @ Check U bit	100	tst r8, #1 << 23 @ Check U bit
101	subne r7, r7, r6, lsl #2 @ Undo increment	101	subne r7, r7, r6, lsl #2 @ Undo increment
102	addeq r7, r7, r6, lsl #2 @ Undo decrement	102	addeq r7, r7, r6, lsl #2 @ Undo decrement
103	str r7, [sp, r5, lsr #14] @ Put register 'Rn'	103	str r7, [r2, r5, lsr #14] @ Put register 'Rn'
104	b do_DataAbort	104	b do_DataAbort
105		105
106	.data_arm_apply_r6_and_rn:	106	.data_arm_apply_r6_and_rn:
107	and r5, r8, #15 << 16 @ Extract 'n' from instruction	107	and r5, r8, #15 << 16 @ Extract 'n' from instruction
108	ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'	108	ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
109	tst r8, #1 << 23 @ Check U bit	109	tst r8, #1 << 23 @ Check U bit
110	subne r7, r7, r6 @ Undo incrmenet	110	subne r7, r7, r6 @ Undo incrmenet
111	addeq r7, r7, r6 @ Undo decrement	111	addeq r7, r7, r6 @ Undo decrement
112	str r7, [sp, r5, lsr #14] @ Put register 'Rn'	112	str r7, [r2, r5, lsr #14] @ Put register 'Rn'
113	b do_DataAbort	113	b do_DataAbort
114		114
115	.data_arm_lateldrpreconst:	115	.data_arm_lateldrpreconst:
@@ -119,11 +119,11 @@ ENTRY(cpu_arm6_data_abort)
119	movs r9, r8, lsl #20 @ Get offset	119	movs r9, r8, lsl #20 @ Get offset
120	beq do_DataAbort @ zero -> no fixup	120	beq do_DataAbort @ zero -> no fixup
121	and r5, r8, #15 << 16 @ Extract 'n' from instruction	121	and r5, r8, #15 << 16 @ Extract 'n' from instruction
122	ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'	122	ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
123	tst r8, #1 << 23 @ Check U bit	123	tst r8, #1 << 23 @ Check U bit
124	subne r7, r7, r9, lsr #20 @ Undo increment	124	subne r7, r7, r9, lsr #20 @ Undo increment
125	addeq r7, r7, r9, lsr #20 @ Undo decrement	125	addeq r7, r7, r9, lsr #20 @ Undo decrement
126	str r7, [sp, r5, lsr #14] @ Put register 'Rn'	126	str r7, [r2, r5, lsr #14] @ Put register 'Rn'
127	b do_DataAbort	127	b do_DataAbort
128		128
129	.data_arm_lateldrprereg:	129	.data_arm_lateldrprereg:
@@ -131,7 +131,7 @@ ENTRY(cpu_arm6_data_abort)
131	beq do_DataAbort @ no writeback -> no fixup	131	beq do_DataAbort @ no writeback -> no fixup
132	.data_arm_lateldrpostreg:	132	.data_arm_lateldrpostreg:
133	and r7, r8, #15 @ Extract 'm' from instruction	133	and r7, r8, #15 @ Extract 'm' from instruction
134	ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'	134	ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
135	mov r5, r8, lsr #7 @ get shift count	135	mov r5, r8, lsr #7 @ get shift count
136	ands r5, r5, #31	136	ands r5, r5, #31
137	and r7, r8, #0x70 @ get shift type	137	and r7, r8, #0x70 @ get shift type