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| * | ARM: mach-imx: clk-imx51-imx53: Retrieve base address and irq from dtFabio Estevam2013-10-20
| | | | | | | | | | | | | | | | | | | | | | | | As mx53 is a dt-only SoC, we should retrieve the gpt base address and irq from the device tree, instead of using the old MX53_IO_ADDRESS method. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: Include linux/err.hThierry Reding2013-10-20
| | | | | | | | | | | | | | | | | | | | | | | | The IS_ERR() macro is defined in the linux/err.h header file, so include it explicitly. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx6q: clock and Kconfig update for PCIe supportSean Cross2013-10-20
| | | | | | | | | | | | | | | | | | | | | Update imx6q clock initialization and Kconfig for PCIe support. Signed-off-by: Sean Cross <xobs@kosagi.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: Add LVDS general-purpose clocks to i.MX6QSean Cross2013-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX6 has two general-purpose LVDS clocks that can be driven from a variety of sources. This patch adds a mux and a gate for both of these clocks. Signed-off-by: Sean Cross <xobs@kosagi.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: remove stale mx53_display_revision() declarationShawn Guo2013-10-20
| | | | | | | | | | | | | | | | | | | | | The mx53_display_revision() declaration in common.h is stale and used nowhere, so remove it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx6: report soc info via soc deviceShawn Guo2013-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch enables soc bus infrastructure and adds a function imx_soc_device_init() to report soc info via soc device interface for imx6qdl and imx6sl. With the support, user space can get soc related info by looking at sysfs like below. $ cat /sys/devices/soc0/machine Freescale i.MX6 Quad SABRE Smart Device Board $ cat /sys/devices/soc0/family Freescale i.MX $ cat /sys/devices/soc0/soc_id i.MX6Q $ cat /sys/devices/soc0/revision 1.2 Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: use imx_init_revision_from_anatop() on imx6slShawn Guo2013-10-20
| | | | | | | | | | | | | | | | | | | | | Add imx6sl support into imx_init_revision_from_anatop(), so that it can be used to initialize cpu type and revision on imx6sl. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: add a common function to initialize revision from anatopShawn Guo2013-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | The patch creates a common function imx_init_revision_from_anatop() by merging imx6q_init_revision() and imx_anatop_get_digprog(), so that any SoC that encodes revision info in anatop can use it to initialize revision. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx6q: use common soc revision helpersShawn Guo2013-10-20
| | | | | | | | | | | | | | | | | | | | | | | | It calls imx_set_soc_revision() to set up soc revision in imx6q_init_revision(), and replaces all the occurrences of imx6q_revision() with common helper imx_get_soc_revision(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: add soc revision helper functionsShawn Guo2013-10-20
| | | | | | | | | | | | | | | | | | | | | | | | Similar to what we do for cpu type, the patch adds helper functions imx_set_soc_revision() and imx_get_soc_revision() to maintain imx_soc_revision in cpu.c. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx: remove IRQF_DISABLEDMichael Opdenacker2013-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This flag is a NOOP since 2.6.35 and can be removed. This is an update for 3.11 of a patch already sent for 3.10 Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx6sl: config iomux-gpr1 to select clock for fecFugang Duan2013-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | Config iomux-gpr1 to select clock source for fec system clock. Clear gpr1[14], gpr1[18-17] bit to select the fec clock source from internal anatop PLL. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: imx6q: Add pll4_audio_div to clock treeNicolin Chen2013-10-20
| | | | | | | | | | | | | | | | | | | | | | | | There's a pll4_audio_div clock, an extra divider for pll4, missing in current clock tree, thus add it. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | Merge remote-tracking branch 'shesselba/clk-of-init-v2_for-3.13' into imx/socShawn Guo2013-10-20
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* | | ARM: drop explicit selection of HAVE_CLK and CLKDEV_LOOKUPUwe Kleine-König2013-10-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CLKDEV_LOOKUP selects HAVE_CLK and COMMON_CLK selects CLKDEV_LOOKUP. So all symbols that select at least two of these symbols can be simplified. For imx, omap2 and ux500 some rearrangements were necessary before the simplification. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Pawel Moll <pawel.moll@arm.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Olof Johansson <olof@lixom.net>
* | | Merge branch 'clk-of-init-v2_for-3.13' of ↵Olof Johansson2013-10-07
|\ \ \ | |/ / |/| / | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/shesselba/linux-dove into next/cleanup From Sebastian Hasselbarth: This is a patch set based on an RFC [1][2] sent earlier to provide a common arch/arm init for DT clock providers. Currently, the call to of_clk_init(NULL) to initialize DT clock providers is spread among several mach-dirs. Since most machs require DT clocks initialized before timers, no initcall can be used. By adding of_clk_init(NULL) to arch/arm time_init(), we can remove all mach-specific .init_time hooks that basically called of_clk_init and clocksource_of_init. In contrast to the RFC version, of_clk_init(NULL) is now only called if no custom .init_time callback is set. This allows some machs to still call clock init themselves, as not all can be converted now. Therefore, this patch sets drops conversion of mach-mvebu and mach-zynq. New machs that were introduced with v3.12-rc1 are also converted, except mach-u300 that requires clocks before irqs. * 'clk-of-init-v2_for-3.13' of https://github.com/shesselba/linux-dove: (29 commits) ARM: vt8500: remove custom .init_time hook ARM: vexpress: remove custom .init_time hook ARM: tegra: remove custom .init_time hook ARM: sunxi: remove custom .init_time hook ARM: sti: remove custom .init_time hook ARM: socfpga: remove custom .init_time hook ARM: rockchip: remove custom .init_time hook ARM: prima2: remove custom .init_time hook ARM: nspire: remove custom .init_time hook ARM: nomadik: remove custom .init_time hook ARM: mxs: remove custom .init_time hook ARM: kirkwood: remove custom .init_time hook ARM: imx: remove custom .init_time hook ARM: highbank: remove custom .init_time hook ARM: exynos: remove custom .init_time hook ARM: dove: remove custom .init_time hook ARM: bcm2835: remove custom .init_time hook ARM: bcm: provide common arch init for DT clocks ARM: call of_clk_init from default time_init handler ARM: vt8500: prepare for arch-wide .init_time callback ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: imx: remove custom .init_time hookSebastian Hesselbarth2013-09-29
| | | | | | | | | | | | | | | | With arch/arm calling of_clk_init(NULL) from time_init(), we can now remove custom .init_time hooks. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Shawn Guo <shawn.guo@linaro.org>
* | Merge tag 'pm+acpi-3.12-rc2' of ↵Linus Torvalds2013-09-20
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull ACPI and power management fixes from Rafael Wysocki: 1) Four fixes for cpufreq regressions introduced by the changes that removed Device Tree parsing for CPU device nodes from cpufreq drivers from Sudeep KarkadaNagesha. 2) Two fixes for recent cpufreq regressions introduced by changes related to the preservation of sysfs attributes over system suspend/resume cycles from Viresh Kumar. 3) Fix for ACPI-based wakeup signaling in the PCI subsystem that fails to stop PME polling for devices put into the D3cold power state from Rafael J Wysocki. 4) Fix for bad interactions between cpufreq and udev on systems supporting intel_pstate where acpi-cpufreq is available as well from Yinghai Lu. * tag 'pm+acpi-3.12-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: cpufreq: return EEXIST instead of EBUSY for second registering PCI / ACPI / PM: Clear pme_poll for devices in D3cold on wakeup ARM: shmobile: change dev_id to cpu0 while registering cpu clock ARM: i.MX: change dev_id to cpu0 while registering cpu clock cpufreq: imx6q-cpufreq: assign cpu_dev correctly to cpu0 device cpufreq: cpufreq-cpu0: assign cpu_dev correctly to cpu0 device cpufreq: unlock correct rwsem while updating policy->cpu cpufreq: Clear policy->cpus bits in __cpufreq_remove_dev_finish()
| * | ARM: i.MX: change dev_id to cpu0 while registering cpu clockSudeep KarkadaNagesha2013-09-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently all clkdev registration use "cpufreq-cpu0.0" as dev_id for cpu clock which refers to virtual platform device. It needs to be "cpu0" instead which is actual cpu0 device id. This patch changes the dev_id from "cpufreq-cpu0.0" to "cpu0". Reported-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| * | cpufreq: imx6q-cpufreq: assign cpu_dev correctly to cpu0 deviceSudeep KarkadaNagesha2013-09-18
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit cdc58d602d2e657602a90c190cbf745886c95977 "cpufreq: imx6q-cpufreq: remove device tree parsing for cpu nodes" assumed the pdev->dev is set to cpu0 device in the platform code. But it actually points to the virtual cpufreq-cpu0 platform device which is not present in the device tree. Most of the information needed by cpufreq is stored in cpu0 DT node. So cpu_dev must point to cpu0 device. This patch fixes the wrong assignment to cpu_dev. Reported-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | ARM: imx: i.mx6d/q: disable the double linefill feature of PL310Jason Liu2013-09-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 But according to ARM PL310 errata: 752271 ID: 752271: Double linefill feature can cause data corruption Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 Workaround: The only workaround to this erratum is to disable the double linefill feature. This is the default behavior. without this patch, you will meet the following error when run the memtester application at: http://pyropus.ca/software/memtester/ FAILURE: 0x00100000 != 0x00200000 at offset 0x01365664. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365668. FAILURE: 0x00100000 != 0x00200000 at offset 0x0136566c. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365670. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365674. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365678. Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: mach-imx: clk-imx51-imx53: Fix 'spdif1_pred' clock registrationFabio Estevam2013-09-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit beb2d1c1ba (ARM i.MX5: Add S/PDIF clocks), the following clock error appears on mx51: TrustZone Interrupt Controller (TZIC) initialized i.MX51 clk 180: register failed with -17 i.MX5 clk 180: register failed with -17 sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms CPU identified as i.MX51, silicon rev 3.0 ... Clock 180 corresponds to 'spdif1_podf' and this clock is getting registered twice. Fix it, by properly registering the 'spdif1_pred' clock, which should not reference 'spdif1_podf'. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: imx: initialize clk_init_data.flags for clk-fixup-muxShawn Guo2013-09-16
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clk_init_data.flags of clk-fixup-mux is left there without initialization. It may hold some random data and cause clock framework interpret the clock in an unexpected way. At least on imx6sl, the following division by zero error with sched_clock is seen because of it. Division by zero in kernel. CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.11.0-rc3+ #19 Backtrace: [<80011af0>] (dump_backtrace+0x0/0x10c) from [<80011c90>] (show_stack+0x18/0x1c) r6:3b9aca00 r5:00000020 r4:00000000 r3:00000000 [<80011c78>] (show_stack+0x0/0x1c) from [<8055e02c>] (dump_stack+0x78/0x94) [<8055dfb4>] (dump_stack+0x0/0x94) from [<80011924>] (__div0+0x18/0x20) r4:00000000 r3:00000000 [<8001190c>] (__div0+0x0/0x20) from [<8026c408>] (Ldiv0_64+0x8/0x18) [<8006330c>] (clocks_calc_mult_shift+0x0/0xf8) from [<8072f604>] (setup_sched_clock+0x88/0x1f0) [<8072f57c>] (setup_sched_clock+0x0/0x1f0) from [<8071ad48>] (mxc_timer_init+0xe8/0x17c) [<8071ac60>] (mxc_timer_init+0x0/0x17c) from [<807290b0>] (imx6sl_clocks_init+0x1db8/0x1dc0) r8:807a9ca4 r7:00000000 r6:80777564 r5:8100c1f4 r4:c0820000 [<807272f8>] (imx6sl_clocks_init+0x0/0x1dc0) from [<807420ac>] (of_clk_init+0x40/0x6c) [<8074206c>] (of_clk_init+0x0/0x6c) from [<807290cc>] (imx6sl_timer_init+0x14/0x18) r5:807a8e80 r4:ffffffff [<807290b8>] (imx6sl_timer_init+0x0/0x18) from [<80716e1c>] (time_init+0x24/0x34) [<80716df8>] (time_init+0x0/0x34) from [<80713738>] (start_kernel+0x1b0/0x310) [<80713588>] (start_kernel+0x0/0x310) from [<80008074>] (0x80008074) r7:80770b08 r6:80754cd4 r5:8076c8c4 r4:10c53c7d sched_clock: 32 bits at 0 Hz, resolution 0ns, wraps every 0ms Fix the bug by initializing init.flags as zero. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2013-09-10
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull slave-dmaengine updates from Vinod Koul: "This pull brings: - Andy's DW driver updates - Guennadi's sh driver updates - Pl08x driver fixes from Tomasz & Alban - Improvements to mmp_pdma by Daniel - TI EDMA fixes by Joel - New drivers: - Hisilicon k3dma driver - Renesas rcar dma driver - New API for publishing slave driver capablities - Various fixes across the subsystem by Andy, Jingoo, Sachin etc..." * 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (94 commits) dma: edma: Remove limits on number of slots dma: edma: Leave linked to Null slot instead of DUMMY slot dma: edma: Find missed events and issue them ARM: edma: Add function to manually trigger an EDMA channel dma: edma: Write out and handle MAX_NR_SG at a given time dma: edma: Setup parameters to DMA MAX_NR_SG at a time dmaengine: pl330: use dma_set_max_seg_size to set the sg limit dmaengine: dma_slave_caps: remove sg entries dma: replace devm_request_and_ioremap by devm_ioremap_resource dma: ste_dma40: Fix potential null pointer dereference dma: ste_dma40: Remove duplicate const dma: imx-dma: Remove redundant NULL check dma: dmagengine: fix function names in comments dma: add driver for R-Car HPB-DMAC dma: k3dma: use devm_ioremap_resource() instead of devm_request_and_ioremap() dma: imx-sdma: Staticize sdma_driver_data structures pch_dma: Add MODULE_DEVICE_TABLE dmaengine: PL08x: Add cyclic transfer support dmaengine: PL08x: Fix reading the byte count in cctl dmaengine: PL08x: Add support for different maximum transfer size ...
| * ARM: i.MX: remove sdma script address arrays from platform dataSascha Hauer2013-08-26
| | | | | | | | | | | | | | | | | | Now that the sdma driver holds the address tables for i.MX25/5 they are no longer needed in platform_data. Remove them. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds2013-09-09
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull clock framework changes from Michael Turquette: "The common clk framework changes for 3.12 are dominated by clock driver patches, both new drivers and fixes to existing. A high percentage of these are for Samsung platforms like Exynos. Core framework fixes and some new features like automagical clock re-parenting round out the patches" * tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits) clk: only call get_parent if there is one clk: samsung: exynos5250: Simplify registration of PLL rate tables clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clocksource: samsung_pwm_timer: Get clock from device tree ARM: dts: exynos4: Specify PWM clocks in PWM node pwm: samsung: Update DT bindings documentation to cover clocks clk: Move symbol export to proper location clk: fix new_parent dereference before null check clk: wm831x: Initialise wm831x pointer on init ...
| * | clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan2013-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes being reparented during clk_set_rate. To avoid breaking existing platforms, all callers of clk_register_mux() are adjusted to pass the new flag. Platform maintainers are encouraged to remove the flag if they wish to allow mux reparenting on set_rate. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Chao Xie <xiechao.mail@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Andrew Chew <achew@nvidia.com> Cc: Doug Anderson <dianders@chromium.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Tomasz Figa <t.figa@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: spear-devel@list.st.com Cc: linux-tegra@vger.kernel.org Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> [tegra] Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi] Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq] Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | Merge tag 'soc-for-linus' of ↵Linus Torvalds2013-09-06
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Olof Johansson: "This branch contains mostly additions and changes to platform enablement and SoC-level drivers. Since there's sometimes a dependency on device-tree changes, there's also a fair amount of those in this branch. Pieces worth mentioning are: - Mbus driver for Marvell platforms, allowing kernel configuration and resource allocation of on-chip peripherals. - Enablement of the mbus infrastructure from Marvell PCI-e drivers. - Preparation of MSI support for Marvell platforms. - Addition of new PCI-e host controller driver for Tegra platforms - Some churn caused by sharing of macro names between i.MX 6Q and 6DL platforms in the device tree sources and header files. - Various suspend/PM updates for Tegra, including LP1 support. - Versatile Express support for MCPM, part of big little support. - Allwinner platform support for A20 and A31 SoCs (dual and quad Cortex-A7) - OMAP2+ support for DRA7, a new Cortex-A15-based SoC. The code that touches other architectures are patches moving MSI arch-specific functions over to weak symbols and removal of ARCH_SUPPORTS_MSI, acked by PCI maintainers" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits) tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list ARM: dts: vf610-twr: enable i2c0 device ARM: dts: i.MX51: Add one more I2C2 pinmux entry ARM: dts: i.MX51: Move pins configuration under "iomuxc" label ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX ARM: dts: i.MX27: Disable AUDMUX in the template ARM: dts: wandboard: Add support for SDIO bcm4329 ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template ARM: dts: imx53-qsb: Make USBH1 functional ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module ARM: dts: imx6qdl-sabresd: Add touchscreen support ARM: imx: add ocram clock for imx53 ARM: dts: imx: ocram size is different between imx6q and imx6dl ARM: dts: imx27-phytec-phycore-som: Fix regulator settings ARM: dts: i.MX27: Remove clock name from CPU node ...
| * | | ARM: imx: add ocram clock for imx53Shawn Guo2013-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing ocram gate clock for imx53 and also represent it in device tree ocram node. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx6q: remove board specific CLKO setupShawn Guo2013-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CLKO is widely used by imx6q board designs to clock audio codec. Since most codecs accept 24 MHz frequency, let's initially set up CLKO with OSC24M (cko <-- cko2 <-- osc). Then those board specific CLKO setup for audio codec can be removed. The board dts files also need an update on cko reference in codec node. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | phy: micrel: Add definitions for common Micrel PHY registersDinh Nguyen2013-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add defines for common Micrel PHY setups so that other platforms can use them. Update imx61 and sama5 hardware to use the micrel_phy.h PHY defines. Also add support for the KSZ9021RLRN PHY. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: David S. Miller <davem@davemloft.net> CC: Andrew Victor <linux@maxim.org.za> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: netdev@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx: Move anatop related from board file to anatop driverPeter Chen2013-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move anatop related (For USB) from board file to anatop driver Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: mx53: Allow suspend/resumeFabio Estevam2013-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current imx53_pm_init() implementation is incomplete as it lacks calling suspend_set_ops(). Use a single imx5_pm_init() function to handle both mx51 and mx53. This allows mx53 to enter in low-power mode. Tested on a mx53qsb: root@freescale /$ echo mem > /sys/power/state PM: Syncing filesystems ... done. mmc0: card e624 removed Freezing user space processes ... (elapsed 0.001 seconds) done. Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. Suspending console(s) (use no_console_suspend to debug) ... (Press Power button) PM: suspend of devices complete after 17.067 msecs PM: suspend devices took 0.020 seconds PM: late suspend of devices complete after 0.954 msecs PM: noirq suspend of devices complete after 1.288 msecs Disabling non-boot CPUs ... PM: noirq resume of devices complete after 0.680 msecs PM: early resume of devices complete after 0.914 msecs PM: resume of devices complete after 44.955 msecs PM: resume devices took 0.050 seconds Restarting tasks ... done. mmc0: host does not support reading read-only switch. assuming write-enable. mmc0: new SDHC card at address e624 mmcblk0: mmc0:e624 SU04G 3.69 GiB mmcblk0: p1 p2 p3 libphy: 63fec000.etherne:00 - Link is Down libphy: 63fec000.etherne:00 - Link is Up - 100/Full root@freescale /$ Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: mach-imx: Select ARM_CPU_SUSPEND at ARCH_MXC levelFabio Estevam2013-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of selecting ARM_CPU_SUSPEND only for mx6, we can select it for all SoCs from the ARCH_MXC family. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx6q: add vdoa gate clockShawn Guo2013-08-22
| | | | | | | | | | | | | | | | | | | | | | | | Add the missing vdoa gate clock for imx6q. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx6q: add the missing cko output selectionShawn Guo2013-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock output on imx6q CCM_CLKO1 pad is not always cko1 clock, and there is a multiplexer to select between cko1 and cko2. Add this missing selection as the clock cko. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx6q: add cko2 clocksShawn Guo2013-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It adds the missing cko2 clocks, including multiplexer, divider and gate. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx6q: add spdif gate clockShawn Guo2013-08-22
| | | | | | | | | | | | | | | | | | | | | | | | It adds the missing spdif gate clock into imx6q clock driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx: clk-pllv3: improve the timeout waiting methodPeter Chen2013-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two improvements for this commit: - Add comparing pll lock condition after while loop. It can fix potential fake timeout problem caused by the code is just scheduled out before compare the timeout, and the time of scheduling out are more than one jiffies. - Move timeout assignment more close to compare the timeout. It can reduce the possibility the code is scheduled out, and the timeout can be more precise. Signed-off-by: Peter Chen <peter.chen@freescale.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx6: change some clocks to fixup clocksLiu Ying2013-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the clocks controlled by the register 'CCM Serial Clock Multiplexer Register 1' should be fixup clocks. This patch changes those clocks from basic multiplexer or divider clocks to fixup clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx: add common clock support for fixup muxLiu Ying2013-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One register may have several fields to control some clocks. It is possible that the read/write values of some fields may map to different real functional values, so writing to the other fields in the same register may break a working clock tree. A real case is the aclk_podf field in the register 'CCM Serial Clock Multiplexer Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook for multiplexer clock which is called before writing a value to clock registers to support this kind of multiplexer clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx: add common clock support for fixup divLiu Ying2013-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One register may have several fields to control some clocks. It is possible that the read/write values of some fields may map to different real functional values, so writing to the other fields in the same register may break a working clock tree. A real case is the aclk_podf field in the register 'CCM Serial Clock Multiplexer Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook for divider clock which is called before writing a value to clock registers to support this kind of divider clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx: Select MIGHT_HAVE_CACHE_L2X0Fabio Estevam2013-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Select MIGHT_HAVE_CACHE_L2X0 for armv6 and armv7 i.MX SoCs. By selecting MIGHT_HAVE_CACHE_L2X0, the user still has the possibility to disable CACHE_L2X0 selection via menuconfig. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx: fix imx_init_l2cache storage classVincent Stehlé2013-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following compilation error: arch/arm/mach-imx/system.c:101:123: error: static declaration of ‘imx_init_l2cache’ follows non-static declaration In file included from arch/arm/mach-imx/system.c:32:0: arch/arm/mach-imx/common.h:165:13: note: previous declaration of ‘imx_init_l2cache’ was here arch/arm/mach-imx/system.c:101:123: warning: ‘imx_init_l2cache’ defined but not used [-Wunused-function] Signed-off-by: Vincent Stehlé <vincent.stehle@freescale.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx: use imx specific L2 init function on imx6slShawn Guo2013-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The optimized L2 prefect and power setting done in imx_init_l2cache() can also benefit imx6sl, so let's call the function on imx6sl as well. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
| * | | ARM: imx: let L2 initialization be a common functionShawn Guo2013-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move imx6q L2 initialization function imx6q_init_l2cache() into system.c, and rename it imx_init_l2cache(), so that other platforms other than imx6q can also use the function. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
| * | | ARM i.MX6DL: parent LDB DI clocks to PLL5 on i.MX6S/DLPhilipp Zabel2013-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX6S/DL have the Video PLL post dividers fixed already in revision 1.0 Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM i.MX6Q: Use ENET_CLK_SEL defines in imx6q_1588_initPhilipp Zabel2013-08-16
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: i.MX6: add ethernet phy fixup for KSZ9031Sascha Hauer2013-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The KSZ9031 is used on the i.MX6 based Data Modul eDM-QMX6 board. It needs the same fixup to the rx/tx delays as other i.MX6 boards. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: i.MX6: add ethernet phy fixup for AR8031Sascha Hauer2013-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AR8031 is used on the i.MX6 based sabreSD, sabreauto and wandboard. All need the same fixup, so add it for all i.MX6. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-05 07:54:27 -0400