diff options
author | Fabio Estevam <fabio.estevam@freescale.com> | 2013-09-30 23:21:12 -0400 |
---|---|---|
committer | Shawn Guo <shawn.guo@linaro.org> | 2013-10-20 21:27:55 -0400 |
commit | bfcc7bcef55dd9db82758f3ac755714a59db9529 (patch) | |
tree | 4e23ddfecfb2440a1a13d5c6babb326ab435957b /arch/arm/mach-imx | |
parent | a4de29044d1887543dd35a75ac666eac431e8765 (diff) |
ARM: mach-imx: clk-imx51-imx53: Retrieve base address and irq from dt
As mx53 is a dt-only SoC, we should retrieve the gpt base address and irq
from the device tree, instead of using the old MX53_IO_ADDRESS method.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r-- | arch/arm/mach-imx/clk-imx51-imx53.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index ceaac9cd7b42..ce37af26ff8c 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c | |||
@@ -14,6 +14,9 @@ | |||
14 | #include <linux/clk-provider.h> | 14 | #include <linux/clk-provider.h> |
15 | #include <linux/of.h> | 15 | #include <linux/of.h> |
16 | #include <linux/err.h> | 16 | #include <linux/err.h> |
17 | #include <linux/of.h> | ||
18 | #include <linux/of_address.h> | ||
19 | #include <linux/of_irq.h> | ||
17 | 20 | ||
18 | #include "crm-regs-imx5.h" | 21 | #include "crm-regs-imx5.h" |
19 | #include "clk.h" | 22 | #include "clk.h" |
@@ -472,8 +475,9 @@ CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt); | |||
472 | 475 | ||
473 | static void __init mx53_clocks_init(struct device_node *np) | 476 | static void __init mx53_clocks_init(struct device_node *np) |
474 | { | 477 | { |
475 | int i; | 478 | int i, irq; |
476 | unsigned long r; | 479 | unsigned long r; |
480 | void __iomem *base; | ||
477 | 481 | ||
478 | clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); | 482 | clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); |
479 | clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); | 483 | clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); |
@@ -559,14 +563,17 @@ static void __init mx53_clocks_init(struct device_node *np) | |||
559 | clk_set_rate(clk[esdhc_a_podf], 200000000); | 563 | clk_set_rate(clk[esdhc_a_podf], 200000000); |
560 | clk_set_rate(clk[esdhc_b_podf], 200000000); | 564 | clk_set_rate(clk[esdhc_b_podf], 200000000); |
561 | 565 | ||
562 | /* System timer */ | ||
563 | mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT); | ||
564 | |||
565 | clk_prepare_enable(clk[iim_gate]); | 566 | clk_prepare_enable(clk[iim_gate]); |
566 | imx_print_silicon_rev("i.MX53", mx53_revision()); | 567 | imx_print_silicon_rev("i.MX53", mx53_revision()); |
567 | clk_disable_unprepare(clk[iim_gate]); | 568 | clk_disable_unprepare(clk[iim_gate]); |
568 | 569 | ||
569 | r = clk_round_rate(clk[usboh3_per_gate], 54000000); | 570 | r = clk_round_rate(clk[usboh3_per_gate], 54000000); |
570 | clk_set_rate(clk[usboh3_per_gate], r); | 571 | clk_set_rate(clk[usboh3_per_gate], r); |
572 | |||
573 | np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"); | ||
574 | base = of_iomap(np, 0); | ||
575 | WARN_ON(!base); | ||
576 | irq = irq_of_parse_and_map(np, 0); | ||
577 | mxc_timer_init(base, irq); | ||
571 | } | 578 | } |
572 | CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); | 579 | CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); |