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* MIPS: asm: cmpxchg: Update ISA constraints for MIPS R6 supportMarkos Chandras2015-02-17
| | | | | | | | MIPS R6 changed the opcodes for LL/SC instructions so we need to set the correct ISA. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Use the new "ZC" constraint for MIPS R6Markos Chandras2015-02-17
| | | | | | | | | GCC versions supporting MIPS R6 use the ZC constraint to enforce a 9-bit offset for MIPS R6. We will use that for all MIPS R6 LL/SC instructions. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: Rename GCC_OFF12_ASM to GCC_OFF_SMALL_ASMMarkos Chandras2015-02-17
| | | | | | | | | The GCC_OFF12_ASM macro is used for 12-bit immediate constrains but we will also use it for 9-bit constrains on MIPS R6 so we rename it to something more appropriate. Cc: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: spram: Add new symbol for MIPS scratch pad storageMarkos Chandras2015-02-17
| | | | | | | | | MIPS R6, just like MIPS R2, have scratch pad storage, so add a new symbol which is selected by MIPS R2 and R6. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00389.html Cc: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: r4kcache: Add MIPS R6 cache unroll functionsMarkos Chandras2015-02-17
| | | | | | | | | MIPS R6 changed the 'cache' instruction opcode and reduced the offset field to 8 bits. This means we now have to adjust the base register every 256 bytes and as a result of which we can no longer use the previous cache functions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: irqflags: Add MIPS R6 related definitionsMarkos Chandras2015-02-17
| | | | | | Add the MIPS R6 related definitions to the IRQ related macros Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: hazards: Add MIPSR6 definitionsMarkos Chandras2015-02-17
| | | | | | Add the MIPSR6 related definitions to MIPS hazards Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: cpu: Add MIPSR6 ISA definitionsLeonid Yegoshin2015-02-17
| | | | | | | Add MIPS R6 to the ISA definitions Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Use generic checksum functions for MIPS R6Markos Chandras2015-02-17
| | | | | | | | | | | The following instructions have been removed from MIPS R6 ulw, ulh, swl, lwr, lwl, swr. However, all of them are used in the MIPS specific checksum implementation. As a result of which, we will use the generic checksum on MIPS R6 Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: asmmacro: Replace "add" instructions with "addu"Markos Chandras2015-02-17
| | | | | | | | | | | | | The "add" instruction is actually a macro in binutils and depending on the size of the immediate it can expand to an "addi" instruction. However, the "addi" instruction traps on overflows which is not something we want on address calculation. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00121.html Cc: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: <stable@vger.kernel.org> # v3.15+ Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: asmmacro: Add MIPS R6 support to the simple EI/DI variantsLeonid Yegoshin2015-02-17
| | | | | | | | EI/DI instructions are available in MIPS R6 so add the needed definitions. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: stackframe: Do not preserve the HI/LO registers on MIPS R6Leonid Yegoshin2015-02-17
| | | | | | | | | | | | | | The HI/LO registers have been removed from MIPS R6. Instructions such as MULT and DIV have been replaced with a new pair of instructions for the HI/LO operations for example: MULT -> MUL, MUH DIV -> DIV, MOD So we avoid preserving the pre-R6 HI/LO registers in MIPS R6 Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: module: define MODULE_PROC_FAMILY for MIPS R6Leonid Yegoshin2015-02-17
| | | | | | | Define the MODULE_PROC_FAMILY for the MIPS R6 ISA. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: asm: compiler: Add new macros to set ISA and arch asm annotationsMarkos Chandras2015-02-17
| | | | | | | | | There are certain places where the code uses .set mips32 or .set mips64 or .set arch=r4000. In preparation of MIPS R6 support, and in order to use as less #ifdefs as possible, we define new macros to set similar annotations for MIPS R6. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: mm: Add MIPS R6 instruction encodingsLeonid Yegoshin2015-02-16
| | | | | | | | MIPS R6 defines new opcodes for ll, sc, cache and pref instructions so we need to take these into consideration in the micro-assembler. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: mm: uasm: Add signed 9-bit immediate related macrosLeonid Yegoshin2015-02-16
| | | | | | | | MIPS R6 redefines several instructions and reduces the immediate field to 9-bits so add related macros for the microassembler. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Add build support for the MIPS R6 ISALeonid Yegoshin2015-02-16
| | | | | | | | | | Add build support for the latest revision (R6) of the MIPS ISA. microMIPS is not yet supported. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00386.html Cc: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Add MIPS generic QEMU probe supportLeonid Yegoshin2015-02-16
| | | | | | | Add a case in cpu_probe_mips for the MIPS generic QEMU processor ID. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Add cases for CPU_QEMU_GENERICLeonid Yegoshin2015-02-16
| | | | | | | Add a CPU_QEMU_GENERIC case to various switch statements. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Add generic QEMU PRid and cpu type identifiersLeonid Yegoshin2015-02-16
| | | | | | | | | Latest versions of QEMU added support for mips32r6-generic and mips64r6-generic cpu types so add related definitions in preparation of MIPS R6 support. This is also used for QEMU R2 generic cpus. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Makefile: Move the ASEs checks after setting the core's CFLAGSMarkos Chandras2015-02-16
| | | | | | | | | | | We need to check the ASEs support against the core's CFLAGS instead of depending to the default -march option from the toolchain. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9180/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: HTW: Prevent accidental HTW start due to nested htw_{start, stop}Markos Chandras2015-02-16
| | | | | | | | | | | | | | | | | | | | | activate_mm() and switch_mm() call get_new_mmu_context() which in turn can enable the HTW before the entryhi is changed with the new ASID. Since the latter will enable the HTW in local_flush_tlb_all(), then there is a small timing window where the HTW is running with the new ASID but with an old pgd since the TLBMISS_HANDLER_SETUP_PGD hasn't assigned a new one yet. In order to prevent that, we introduce a simple htw counter to avoid starting HTW accidentally due to nested htw_{start,stop}() sequences. Moreover, since various IPI calls can enforce TLB flushing operations on a different core, such an operation may interrupt another htw_{stop,start} in progress leading inconsistent updates of the htw_seq variable. In order to avoid that, we disable the interrupts whenever we update that variable. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # 3.17+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9118/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: asm: pgtable: Prevent HTW race when updating PTEsMarkos Chandras2015-02-16
| | | | | | | | | | | | | | | | Whenever we modify a page table entry, we need to ensure that the HTW will not fetch a stable entry. And for that to happen we need to ensure that HTW is stopped before we modify the said entry otherwise the HTW may already be in the process of reading that entry and fetching the old information. As a result of which, we replace the htw_reset() calls with htw_{stop,start} in more appropriate places. This also removes the remaining users of htw_reset() and as a result we drop that macro Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # 3.17+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9116/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: asm: pgtable: Add c0 hazards on HTW start/stop sequencesMarkos Chandras2015-02-16
| | | | | | | | | | | | When we use htw_{start,stop}() outside of htw_reset(), we need to ensure that c0 changes have been propagated properly before we attempt to continue with subsequence memory operations. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # 3.17+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9114/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: mm: Add debug information for userland SIGSEGV signals.Markos Chandras2015-02-16
| | | | | | | | | | | | | | | | Commit 41c594ab65fc ("[MIPS] MT: Improved multithreading support.") removed useful debug information for userland segmentation faults. This patch bring this back along with the ability to determine the name of the object file where the EPC and RA registers point at. Furthermore, we select the SYSCTL_EXCEPTION_TRACE symbol for MIPS which is the de facto solution to turn userland exception logging on and off via the /proc/sys/debug/exception-trace file. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9089/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS,prctl: add PR_[GS]ET_FP_MODE prctl options for MIPSPaul Burton2015-02-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Userland code may be built using an ABI which permits linking to objects that have more restrictive floating point requirements. For example, userland code may be built to target the O32 FPXX ABI. Such code may be linked with other FPXX code, or code built for either one of the more restrictive FP32 or FP64. When linking with more restrictive code, the overall requirement of the process becomes that of the more restrictive code. The kernel has no way to know in advance which mode the process will need to be executed in, and indeed it may need to change during execution. The dynamic loader is the only code which will know the overall required mode, and so it needs to have a means to instruct the kernel to switch the FP mode of the process. This patch introduces 2 new options to the prctl syscall which provide such a capability. The FP mode of the process is represented as a simple bitmask combining a number of mode bits mirroring those present in the hardware. Userland can either retrieve the current FP mode of the process: mode = prctl(PR_GET_FP_MODE); or modify the current FP mode of the process: err = prctl(PR_SET_FP_MODE, new_mode); Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8899/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: cevt-r4k: Drop GIC special caseJames Hogan2015-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cevt-r4k driver used to call into the GIC driver to find whether the timer was pending, but only with External Interrupt Controller (EIC) mode, where the Cause.IP bits can't be used as they encode the interrupt priority level (Cause.RIPL) instead. However commit e9de688dac65 ("irqchip: mips-gic: Support local interrupts") changed the condition from cpu_has_veic to gic_present. This fails on cores such as P5600 which have a GIC but the local interrupts aren't routable by the GIC, causing c0_compare_int_usable() to consider the interrupt unusable so r4k_clockevent_init() fails. The previous behaviour, added in commit 98b67c37db33 ("MIPS: Add EIC support for GIC."), wasn't really correct either as far as I can tell, since P5600 apparently supports EIC mode too, and in any case the use of Cause.TI with r2 should have been sufficient anyway since commit 010c108d7af7 ("MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs"). Therefore drop the call into the gic driver altogether, and add a comment in c0_compare_int_pending() to clarify that Cause.TI does get checked since MIPS r2. Signed-off-by: James Hogan <james.hogan@imgtec.com> Fixes: e9de688dac65 ("irqchip: mips-gic: Support local interrupts") Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Steven J. Hill <steven.hill@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9077/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: elf2ecoff: Fix warning due to dead code.Ralf Baechle2015-02-04
| | | | | | | | | HOSTCC arch/mips/boot/elf2ecoff arch/mips/boot/elf2ecoff.c: In function ‘main’: arch/mips/boot/elf2ecoff.c:271:8: warning: variable ‘shstrtab’ set but not used [-Wunused-but-set-variable] char *shstrtab; Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add struct pci_ops member names to initializationRob Herring2015-01-16
| | | | | | | | | | | | | | | | | Some instances of pci_ops initialization rely on the read/write members' location in the struct. This is fragile and may break when adding new members to the beginning of the struct. [ralf@linux-mips.org: indent = with tabs for consistency.] Signed-off-by: Rob Herring <robh@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Arnd Bergmann <arnd@arndb.de> Cc: linux-pci@vger.kernel.org Cc: Bjorn Helgaas <bhelgaas@google.com> Patchwork: https://patchwork.linux-mips.org/patch/8915/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove unused dt_setup_arch()Geert Uytterhoeven2015-01-16
| | | | | | | Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8928/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ARC: Add declarations for a few missing ARC firmware functions.Ralf Baechle2015-01-13
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ARC: Use __noreturn instead of open coded attributes in declarations.Ralf Baechle2015-01-13
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: IP27: Use __noreturn instead of open coded attributes in declarations.Ralf Baechle2015-01-13
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: IP32: Use __noreturn instead of open coded attributes in declarations.Ralf Baechle2015-01-13
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ARC: Use __noreturn / unreachable in ARC termination functions.Ralf Baechle2015-01-13
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use generic csum_tcpudp_magic for MIPS.Ralf Baechle2015-01-13
| | | | | | Its implementation is identical to MIPS. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use <asm-generic/checksum.h>Ralf Baechle2015-01-13
| | | | | | | Right now the MIPS <asm/checksum.h> still overrides all functions. This will change in the future. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Rewrite csum_fold to plain C.Ralf Baechle2015-01-13
| | | | | | | This isn't only short and easier to read and fully portable but also shrinks a Malta kernel's by 160 bytes. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* linux 3.19-rc4Linus Torvalds2015-01-11
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* Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds2015-01-11
|\ | | | | | | | | | | | | | | | | | | | | | | Pull ARM fixes from Russell King: "Three small fixes from over the Christmas period, and wiring up the new execveat syscall for ARM" * 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: ARM: 8275/1: mm: fix PMD_SECT_RDONLY undeclared compile error ARM: 8253/1: mm: use phys_addr_t type in map_lowmem() for kernel mem region ARM: 8249/1: mm: dump: don't skip regions ARM: wire up execveat syscall
| * ARM: 8275/1: mm: fix PMD_SECT_RDONLY undeclared compile errorVictor Kamensky2015-01-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In v3.19-rc3 tree when CONFIG_ARM_LPAE and CONFIG_DEBUG_RODATA are enabled image failed to compile with the following error: arch/arm/mm/init.c:661:14: error: ‘PMD_SECT_RDONLY’ undeclared here (not in a function) It seems that '80d6b0c ARM: mm: allow text and rodata sections to be read-only' and 'ded9477 ARM: 8109/1: mm: Modify pte_write and pmd_write logic for LPAE' commits crossed. 80d6b0c uses PMD_SECT_RDONLY macro but ded9477 renames it and uses software bits L_PMD_SECT_RDONLY instead. Fix is to use L_PMD_SECT_RDONLY instead PMD_SECT_RDONLY as ded9477 does in another places. Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 8253/1: mm: use phys_addr_t type in map_lowmem() for kernel mem regionGrygorii Strashko2015-01-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now local variables kernel_x_start and kernel_x_end defined using 'unsigned long' type which is wrong because they represent physical memory range and will be calculated wrongly if LPAE is enabled. As result, all following code in map_lowmem() will not work correctly. For example, Keystone 2 boot is broken because kernel_x_start == 0x0000 0000 kernel_x_end == 0x0080 0000 instead of kernel_x_start == 0x0000 0008 0000 0000 kernel_x_end == 0x0000 0008 0080 0000 and as result whole low memory will be mapped with MT_MEMORY_RW permissions by code (start > kernel_x_end): } else if (start >= kernel_x_end) { map.pfn = __phys_to_pfn(start); map.virtual = __phys_to_virt(start); map.length = end - start; map.type = MT_MEMORY_RW; create_mapping(&map); } Hence, fix it by using phys_addr_t type for variables kernel_x_start and kernel_x_end. Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 8249/1: mm: dump: don't skip regionsMark Rutland2015-01-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the arm page table dumping code starts dumping page tables from USER_PGTABLES_CEILING. This is unnecessary for skipping any entries related to userspace as the swapper_pg_dir does not contain such entries, and results in a couple of unfortuante side effects. Firstly, any kernel mappings which might exist below USER_PGTABLES_CEILING will not be accounted in the dump output. This masks any entries erroneously created below this address. Secondly, if the final page table entry walked is part of a valid mapping the page table dumping code will not log the region this entry is part of, as the final note_page call in walk_pgd will trigger an early return when 0 < USER_PGTABLES_CEILING. Luckily this isn't seen on contemporary systems as they typically don't have enough RAM to extend the linear mapping right to the end of the address space. Due to the way addr is constructed in the walk_* functions, it can never be less than USER_PGTABLES_CEILING when walking the page tables, so it is not necessary to avoid dereferencing invalid table addresses. The existing checks for st->current_prot and st->marker[1].start_address are sufficient to ensure we will not print and/or dereference garbage when trying to log information. This patch removes both problematic uses of USER_PGTABLES_CEILING from the arm page table dumping code, preventing both of these issues. We will now report any low mappings, and the final note_page call will not return early, ensuring all regions are logged. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Steve Capper <steve.capper@linaro.org> Cc: Kees Cook <keescook@chromium.org> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: wire up execveat syscallRussell King2015-01-07
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'x86-urgent-for-linus' of ↵Linus Torvalds2015-01-11
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Ingo Molnar: "Misc fixes: two vdso fixes, two kbuild fixes and a boot failure fix with certain odd memory mappings" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86, vdso: Use asm volatile in __getcpu x86/build: Clean auto-generated processor feature files x86: Fix mkcapflags.sh bash-ism x86: Fix step size adjustment during initial memory mapping x86_64, vdso: Fix the vdso address randomization algorithm
| * \ Merge tag 'pr-20141223-x86-vdso' of ↵Ingo Molnar2015-01-01
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/luto/linux into x86/urgent Pull VDSO fix from Andy Lutomirski: "This is hopefully the last vdso fix for 3.19. It should be very safe (it just adds a volatile). I don't think it fixes an actual bug (the __getcpu calls in the pvclock code may not have been needed in the first place), but discussion on that point is ongoing. It also fixes a big performance issue in 3.18 and earlier in which the lsl instructions in vclock_gettime got hoisted so far up the function that they happened even when the function they were in was never called. n 3.19, the performance issue seems to be gone due to the whims of my compiler and some interaction with a branch that's now gone. I'll hopefully have a much bigger overhaul of the pvclock code for 3.20, but it needs careful review." Signed-off-by: Ingo Molnar <mingo@kernel.org>
| | * | x86, vdso: Use asm volatile in __getcpuAndy Lutomirski2014-12-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Linux 3.18 and below, GCC hoists the lsl instructions in the pvclock code all the way to the beginning of __vdso_clock_gettime, slowing the non-paravirt case significantly. For unknown reasons, presumably related to the removal of a branch, the performance issue is gone as of e76b027e6408 x86,vdso: Use LSL unconditionally for vgetcpu but I don't trust GCC enough to expect the problem to stay fixed. There should be no correctness issue, because the __getcpu calls in __vdso_vlock_gettime were never necessary in the first place. Note to stable maintainers: In 3.18 and below, depending on configuration, gcc 4.9.2 generates code like this: 9c3: 44 0f 03 e8 lsl %ax,%r13d 9c7: 45 89 eb mov %r13d,%r11d 9ca: 0f 03 d8 lsl %ax,%ebx This patch won't apply as is to any released kernel, but I'll send a trivial backported version if needed. Fixes: 51c19b4f5927 x86: vdso: pvclock gettime support Cc: stable@vger.kernel.org # 3.8+ Cc: Marcelo Tosatti <mtosatti@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Andy Lutomirski <luto@amacapital.net>
| * | | x86/build: Clean auto-generated processor feature filesBjørn Mork2014-12-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 9def39be4e96 ("x86: Support compiling out human-friendly processor feature names") made two source file targets conditional. Such conditional targets will not be cleaned automatically by make mrproper. Fix by adding explicit clean-files targets for the two files. Fixes: 9def39be4e96 ("x86: Support compiling out human-friendly processor feature names") Signed-off-by: Bjørn Mork <bjorn@mork.no> Cc: Josh Triplett <josh@joshtriplett.org> Link: http://lkml.kernel.org/r/1419335863-10608-1-git-send-email-bjorn@mork.no Signed-off-by: Ingo Molnar <mingo@kernel.org>
| * | | x86: Fix mkcapflags.sh bash-ismSylvain BERTRAND2014-12-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chocked while compiling linux with dash shell instead of bash shell. See: http://pubs.opengroup.org/onlinepubs/9699919799/utilities/test.html Signed-off-by: Sylvain BERTRAND <sylvain.bertrand@gmail.com> Link: http://lkml.kernel.org/r/20141223123912.GA1386@localhost.localdomain Signed-off-by: Ingo Molnar <mingo@kernel.org>
| * | | x86: Fix step size adjustment during initial memory mappingJan Beulich2014-12-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The old scheme can lead to failure in certain cases - the problem is that after bumping step_size the next (non-final) iteration is only guaranteed to make available a memory block the size of what step_size was before. E.g. for a memory block [0,3004600000) we'd have: iter start end step amount 1 3004400000 30045fffff 2M 2M 2 3004000000 30043fffff 64M 4M 3 3000000000 3003ffffff 2G 64M 4 2000000000 2fffffffff 64G 64G Yet to map 64G with 4k pages (as happens e.g. under PV Xen) we need slightly over 128M, but the first three iterations made only about 70M available. The condition (new_mapped_ram_size > mapped_ram_size) for bumping step_size is just not suitable. Instead we want to bump it when we know we have enough memory available to cover a block of the new step_size. And rather than making that condition more complicated than needed, simply adjust step_size by the largest possible factor we know we can cover at that point - which is shifting it left by one less than the difference between page table level shifts. (Interestingly the original STEP_SIZE_SHIFT definition had a comment hinting at that having been the intention, just that it should have been PUD_SHIFT-PMD_SHIFT-1 instead of (PUD_SHIFT-PMD_SHIFT)/2, and of course for non-PAE 32-bit we can't really use these two constants as they're equal there.) Furthermore the comment in get_new_step_size() didn't get updated when the bottom-down mapping logic got added. Yet while an overflow (flushing step_size to zero) of the shift doesn't matter for the top-down method, it does for bottom-up because round_up(x, 0) = 0, and an upper range boundary of zero can't really work well. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Yinghai Lu <yinghai@kernel.org> Link: http://lkml.kernel.org/r/54945C1E020000780005114E@mail.emea.novell.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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