| Commit message (Collapse) | Author | Age |
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There currently aren't bindings for the Tegra PCIe controller. Work on
this is in progress, but not yet complete. Manually initialize PCIe when
booting from device tree, in order to bring DT support to the same
feature level as board files, which will in turn allow board files to be
deprecated.
PCIe hosts the wired Ethernet controller on TrimSlice.
To support this, add infra-structure to board-dt-tegra20.c for board-
specific initialization code. Once device tree support for the relevant
features is in place, this code will be removed.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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The Seaboard device tree supports all the features that the Seaboard
board files support. Hence, there's no need to keep the board files
around any more; all users should convert to device tree.
MACH_KAEN and MACH_WARIO are also removed. While tegra-seaboard.dts
doesn't support those explicitly, it would be trivial to create device
trees for those boards if anyone cares.
The Seaboard device tree is now compiled if Tegra2 support is enabled,
rather than when Seaboard support is enabled.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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* Make ARCH_TEGRA select USE_OF; DT is the way forward.
* Build board-dt-tegra*.c when the relevant Tegra SoC support is enabled,
rather than requiring a specific config option for this.
* The board-specific config options already build board-*-pinmux.o, and
when booting from device tree these files are no longer needed, so we
can remove some Makefile commands related to those files.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Update Makefile.boot to compile *.dts when the appropriate Tegra SoC
support is enabled, rather than requiring Kconfig to list each board
individually. Remove CONFIG_MACH_VENTANA now that it has no use.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc defconfig updates from Arnd Bergmann:
"These are changes to the default configuration files, to account for
kernel changes and new hardware."
* tag 'defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: exynos_defconfig: enable more platforms in defconfig
ARM: imx_v4_v5_defconfig: update features
ARM: imx_v6_v7_defconfig: update features
ARM: mxs: defconfig: Enable CONFIG_COMMON_CLK_DEBUG
ARM: mxs_defconfig: Enable RTC driver
ARM: LPC32xx: Defconfig update
ARM: mxs_defconfig: Let AUART driver be built by default
ARM: mxs: Enable MACH_APX4DEVKIT
ARM: mxs: Let GPMI driver be built by default
ARM: tegra: defconfig updates
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From Kukjin Kim <kgene.kim@samsung.com>:
It is including new exynos_defconfig for DT configuration of exynos4
and exynos5 together. The old exynos4_defconfig will be used for non-DT
for a while and we will try to move on using exynos_defconfig for only DT.
* samsung/defconfig:
ARM: exynos_defconfig: enable more platforms in defconfig
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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This enables the new EXYNOS5 platforms in the defconfig, and enables DT
support on EXYNOS4.
Other options enabled: USB host, EXT3/4, regulators and tps65090,
networking and a few of the common usb ethernet adapters as well as the
smsc911x controller used on some boards.
I enabled EFI_PARTITION, since it's used on some filesystem images I'm
using. I didn't see a need to keep Solaris and BSD partition format
still enabled.
Finally, framebuffer console, logo and fonts were enabled.
Note that enabling some of these options introduces build coverage
previously missing, thus introducing a few build errors and warnings
for which fixes have been sent out already.
Signed-off-by: Olof Johansson <olof@lixom.net>
[kgene.kim@samsung.com: restored exynos4_defconfig from original]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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next/defconfig
From Sascha Hauer <s.hauer@pengutronix.de>:
ARM i.MX defconfig updates for v3.6
* tag 'imx-defconfig' of git://git.pengutronix.de/git/imx/linux-2.6:
ARM: imx_v4_v5_defconfig: update features
ARM: imx_v6_v7_defconfig: update features
Includes an update to v3.5-rc5
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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- reenable CONFIG_MFD_MC13XXX_SPI
- Allow booting from MMC card.
- Enable mc13783 Codec support
- Enable sgtl5000 Codec support
- Enable mc13783 RTC
- Enable Control Group support for systemd
- Enable clk debugfs support
- Enable i.MX keypad driver
- Enable MC13783 touchscreen
- Enable i.MX PATA driver
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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- Add sound support
- Enable mtd support
- Enable i.MX NAND support
- Enable NOR flash support
- Enable JFFS2/UBI
- Enable clk debugfs support
- Disable iommu support which is not present on i.MX
- Enable MC13xxx RTC
- Enable RNGA random number generator
- Enable SPI EEPROM support
- Enable I2C EEPROM support
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/defconfig
From Stephen Warren <swarren@wwwdotorg.org>:
This branch contains a single commit which adjusts tegra_defconfig to
enable new kernel features, driven by new device tree file content and drivers.
* 'for-3.6/defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: defconfig updates
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Enable:
* SND_SOC_TEGRA_WM8753 (new feature)
* TPS65910 (Cardhu regulator)
* CONFIG_I2C_MUX (dependency of:)
* CONFIG_I2C_MUX_PINCTRL (for Seaboard)
Remove some deleted options:
* MACH_KAEN
* MACH_VENTANA
* MACH_WARIO
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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git://git.linaro.org/people/shawnguo/linux-2.6 into next/defconfig
From Shawn Guo <shawn.guo@linaro.org>:
* 'mxs/defconfig-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: mxs: defconfig: Enable CONFIG_COMMON_CLK_DEBUG
ARM: mxs_defconfig: Enable RTC driver
ARM: mxs_defconfig: Let AUART driver be built by default
ARM: mxs: Enable MACH_APX4DEVKIT
ARM: mxs: Let GPMI driver be built by default
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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With the common clock framework in place, it is useful to enable
CONFIG_COMMON_CLK_DEBUG option, in order to easily inspect the clock tree.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Let RTC driver driver be built by default.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Let AUART driver be built by default.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Enable MACH_APX4DEVKIT to be built by default.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Let GPMI driver be built by default.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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next/defconfig
defconfig updates for lpc32xx, depends on the earlier lpc32xx-next
branch.
* 'lpc32xx/defconfig' of git://git.antcom.de/linux-2.6:
ARM: LPC32xx: Defconfig update
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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This defconfig update for LPC32xx adds interrupt and polled gpio keyboard
drivers.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
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Pull support for three new arm SoC types from Arnd Bergmann:
- The mvebu platform includes Marvell's Armada XP and Armada 370 chips,
made by the mvebu business unit inside of Marvell. Since the same
group also made the older but similar platforms we call "orion5x",
"kirkwood", "mv78xx0" and "dove", we plan to move all of them into
the mach-mvebu directory in the future.
- socfpga is Altera's platform based on Cortex-A9 cores and a lot of
FPGA space. This is similar to the Xilinx zynq platform we already
support. The code is particularly clean, which is helped by the fact
that the hardware doesn't do much besides the parts that are expected
to get added in the FPGA.
- The OMAP subarchitecture gains support for the latest generation, the
OMAP5 based on the new Cortex-A15 core. Support is rather
rudimentary for now, but will be extended in the future.
* tag 'newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (25 commits)
ARM: socfpga: initial support for Altera's SOCFPGA platform
arm: mvebu: generate DTBs for supported SoCs
ARM: mvebu: MPIC: read number of interrupts from control register
arm: mach-mvebu: add entry to MAINTAINERS
arm: mach-mvebu: add compilation/configuration change
arm: mach-mvebu: add defconfig
arm: mach-mvebu: add documentation for new device tree bindings
arm: mach-mvebu: add support for Armada 370 and Armada XP with DT
arm: mach-mvebu: add source files
arm: mach-mvebu: add header
clocksource: time-armada-370-xp: Marvell Armada 370/XP SoC timer driver
ARM: Kconfig update to support additional GPIOs in OMAP5
ARM: OMAP5: Add the build support
arm/dts: OMAP5: Add omap5 dts files
ARM: OMAP5: board-generic: Add device tree support
ARM: omap2+: board-generic: clean up the irq data from board file
ARM: OMAP5: Add SMP support
ARM: OMAP5: Add the WakeupGen IP updates
ARM: OMAP5: l3: Add l3 error handler support for omap5
ARM: OMAP5: gpmc: Update gpmc_init()
...
Conflicts:
Documentation/devicetree/bindings/arm/omap/omap.txt
arch/arm/mach-omap2/Makefile
drivers/clocksource/Kconfig
drivers/clocksource/Makefile
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Adding core definitions for Altera's SOCFPGA ARM platform.
Mininum support for Altera's SOCFPGA Cyclone 5 hardware.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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One more addition from Thomas Petazzoni:
* mvebu/newsoc:
arm: mvebu: generate DTBs for supported SoCs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add the necessary dtb-$(CONFIG_...) entries so that "make dtbs"
generates the Device Tree Blobs that correspond to the selected mvebu
SoCs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/newsoc
From Tony Lindgren <tony@atomide.com>:
This branch contains minimal support for omap5 to boot to a
console without clock framework support. This branch depends
on omap-cleanup-part2-for-v3.6.
* 'devel-omap5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: Kconfig update to support additional GPIOs in OMAP5
ARM: OMAP5: Add the build support
arm/dts: OMAP5: Add omap5 dts files
ARM: OMAP5: board-generic: Add device tree support
ARM: omap2+: board-generic: clean up the irq data from board file
ARM: OMAP5: Add SMP support
ARM: OMAP5: Add the WakeupGen IP updates
ARM: OMAP5: l3: Add l3 error handler support for omap5
ARM: OMAP5: gpmc: Update gpmc_init()
ARM: OMAP5: timer: Add clocksource, clockevent support
ARM: OMAP5: Add minimal support for OMAP5430 SOC
ARM: OMAP5: id: Add cpu id for ES versions
ARM: OMAP: counter-32k: Select the CR register offset using the IP scheme
ARM: OMAP2+: Move stubbed secure_sram_reserve function to a common.c and call it __weak
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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OMAP5 has 8 GPIO banks so that there are 32x8 = 256 GPIOs.
In order for the gpiolib to detect and initialize these
additional GPIOs and other TWL GPIOs, ARCH_NR_GPIO is set
to 512 instead of present 256.
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Cousson, Benoit <b-cousson@ti.com>
Reported-by: Govindraj.R <govindraj.raja@ti.com>
Tested-by: Govindraj.R <govindraj.raja@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Adding the build support required for OMAP5 soc
in to omap2+ config.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Adding the minimum device tree files required for
OMAP5 to boot.
Reviewed-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Adding the minimal support for OMAP5 evm board
with device tree.
Reviewed-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Move the irq_match arrays and the irq init functions of OMAP 2,3
and 4 based boards out of board-generic.c file and also rename the
irq init function to match the interrupt controller present in
the SOCs.
This is a preparatory patch to add the OMAP5 evm board's irq init
support with device tree.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
are runtime checked using cpu id
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
- Additional 32 interrupt support is added w.r.t OMAP4 design.
- The AUX CORE boot registers are now made accessible from non-secure SW.
- SAR offset are changed and PTMSYNC* registers are removed from SAR.
Patch updates the WakeupGen code accordingly.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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The l3 interconnect ip is same for OMAP4 and OMAP5.
So reuse the l3 error handler error code for OMAP5
as well. Also a few targets has been newly added for
OMAP5. So updating the driver for that here.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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GPMC module is the same as in OMAP4.
Just update the base address and irq number.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Adding the Initialisaton for clocksource and clockevent device
on OMAP5 Socs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP
architecture. It's a dual core SOC with GIC used for interrupt
handling and with an integrated L2 cache controller.
OMAP5432 is another variant of OMAP5430, with a
memory controller supporting DDR3 and SATA.
Patch includes:
- The machine specific headers and sources updates.
- Platform header updates.
- Minimum initialisation support for serial.
- IO table init
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Adding the OMAP5 ES1.0, 2.0 and OMAP5432 cpu revision
detection support.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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OMAP socs has a legacy and a highlander version of the
32k sync counter IP. The register offsets vary between the
highlander and the legacy scheme. So use the 'SCHEME'
bits(30-31) of the revision register to distinguish between
the two versions and choose the CR register offset accordingly.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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call it __weak
omap_secure_ram_reserve_memblock is stubbed for OMAP1,2 only builds using a
ifdef check. But this results in adding CONFIG_ARCH_OMAPxx checks for
future socs that use the real function. So move this to common.c file and
call it __weak.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Dependency for omap/minimal-omap5
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
You'll find in this patch set the nineth version of the initial
support for a new family of ARMv7-compatible Marvell SoCs.
As for the previous releases, both the Armada 370 and the Armada XP
SoCs are supported in this directory, and we are able to build a
single kernel image that boots on both SoCs. Both SoCs use the PJ4B
processor, a Marvell-developed ARM core that implements the ARMv7
instruction set. We are currently using Marvell evaluation boards for
both of those SoCs, and the support for those boards is added in this
patch set.
This patch set, and the support for those SoCs, started as a
collaborative effort from Marvell engineers (who have done the initial
development work) and Free Electrons engineers (who are reshaping the
code for mainline submission, adding device tree support, etc.). This
effort has also received contributions from Ben Dooks from Codethink.
* mvebu/newsoc:
ARM: mvebu: MPIC: read number of interrupts from control register
arm: mach-mvebu: add entry to MAINTAINERS
arm: mach-mvebu: add compilation/configuration change
arm: mach-mvebu: add defconfig
arm: mach-mvebu: add documentation for new device tree bindings
arm: mach-mvebu: add support for Armada 370 and Armada XP with DT
arm: mach-mvebu: add source files
arm: mach-mvebu: add header
clocksource: time-armada-370-xp: Marvell Armada 370/XP SoC timer driver
Changes from Arnd
* Pulled from git://github.com/Marvell-Semi/EBU_mainline_public.git mvebu_for-next-V9
* rebased onto v3.5-rc5 because it was originally based on
an old arm-soc/for-next branch
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Read the number of MPIC interrupts from the controller and only register
that many.
[gregory.clement@free-electrons.com: rename armada symbol name to fit
with new name: armada_370_xp]
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
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The new mach-mvebu directory will be maintained by Andrew Lunn and
Jason Cooper (as the existing maintainers for previous Marvell EBU
SoCs) together with Grégory Clément for the Armada 370/XP SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-by: Lior Amsalem <alior@marvell.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-by: Lior Amsalem <alior@marvell.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Tested-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-by: Lior Amsalem <alior@marvell.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
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[ben.dooks@codethink.co.uk: ensure error check on of_property_read_u32]
[ben.dooks@codethink.co.uk: use mpic address instead of bus-unit's ]
[ben.dooks@codethink.co.uk: BUG_ON() if the of_iomap() fails for mpic]
[ben.dooks@codethink.co.uk: move mpic per-cpu register base ]
[ben.dooks@codethink.co.uk: number fetch should use irqd_to_hwirq()]
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-by: Lior Amsalem <alior@marvell.com>
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[ben.dooks@codethink.co.uk: fixup style error in system-controller]
[ben.dooks@codethink.co.uk: check result of of_match_node()]
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-by: Lior Amsalem <alior@marvell.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-by: Lior Amsalem <alior@marvell.com>
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Timer 0 is used as free-running clocksource, while timer 1 is used as
clock_event_device.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-by: Lior Amsalem <alior@marvell.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: John Stultz <johnstul@us.ibm.com>
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