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authorArnd Bergmann <arnd@arndb.de>2012-07-10 11:43:22 -0400
committerArnd Bergmann <arnd@arndb.de>2012-07-10 11:43:22 -0400
commit0e3585113f8fe31b7015d52ac94f56c8952626f7 (patch)
treef7b175588cc5deafb9fdaf8a02fe84d7c52bf275
parent229ce6f45bec3ad35847256dde95267113af2d34 (diff)
parent39f47d9f437fa94622bf51d7b18b42b3336ad9ac (diff)
Merge branch 'devel-omap5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/newsoc
From Tony Lindgren <tony@atomide.com>: This branch contains minimal support for omap5 to boot to a console without clock framework support. This branch depends on omap-cleanup-part2-for-v3.6. * 'devel-omap5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: Kconfig update to support additional GPIOs in OMAP5 ARM: OMAP5: Add the build support arm/dts: OMAP5: Add omap5 dts files ARM: OMAP5: board-generic: Add device tree support ARM: omap2+: board-generic: clean up the irq data from board file ARM: OMAP5: Add SMP support ARM: OMAP5: Add the WakeupGen IP updates ARM: OMAP5: l3: Add l3 error handler support for omap5 ARM: OMAP5: gpmc: Update gpmc_init() ARM: OMAP5: timer: Add clocksource, clockevent support ARM: OMAP5: Add minimal support for OMAP5430 SOC ARM: OMAP5: id: Add cpu id for ES versions ARM: OMAP: counter-32k: Select the CR register offset using the IP scheme ARM: OMAP2+: Move stubbed secure_sram_reserve function to a common.c and call it __weak Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/omap/omap.txt3
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/boot/dts/omap5-evm.dts20
-rw-r--r--arch/arm/boot/dts/omap5.dtsi184
-rw-r--r--arch/arm/configs/omap2plus_defconfig1
-rw-r--r--arch/arm/mach-omap2/Kconfig8
-rw-r--r--arch/arm/mach-omap2/Makefile24
-rw-r--r--arch/arm/mach-omap2/board-generic.c42
-rw-r--r--arch/arm/mach-omap2/common.c24
-rw-r--r--arch/arm/mach-omap2/common.h19
-rw-r--r--arch/arm/mach-omap2/control.h4
-rw-r--r--arch/arm/mach-omap2/devices.c2
-rw-r--r--arch/arm/mach-omap2/gpmc.c3
-rw-r--r--arch/arm/mach-omap2/id.c42
-rw-r--r--arch/arm/mach-omap2/include/mach/debug-macro.S8
-rw-r--r--arch/arm/mach-omap2/include/mach/omap-wakeupgen.h7
-rw-r--r--arch/arm/mach-omap2/io.c44
-rw-r--r--arch/arm/mach-omap2/iomap.h27
-rw-r--r--arch/arm/mach-omap2/irq.c13
-rw-r--r--arch/arm/mach-omap2/omap-headsmp.S21
-rw-r--r--arch/arm/mach-omap2/omap-hotplug.c24
-rw-r--r--arch/arm/mach-omap2/omap-smp.c52
-rw-r--r--arch/arm/mach-omap2/omap-wakeupgen.c114
-rw-r--r--arch/arm/mach-omap2/omap4-common.c14
-rw-r--r--arch/arm/mach-omap2/omap4-sar-layout.h12
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c2
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.h22
-rw-r--r--arch/arm/mach-omap2/prcm-common.h2
-rw-r--r--arch/arm/mach-omap2/prcm.c2
-rw-r--r--arch/arm/mach-omap2/timer.c5
-rw-r--r--arch/arm/plat-omap/Kconfig4
-rw-r--r--arch/arm/plat-omap/common.c9
-rw-r--r--arch/arm/plat-omap/counter_32k.c16
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h22
-rw-r--r--arch/arm/plat-omap/include/plat/hardware.h1
-rw-r--r--arch/arm/plat-omap/include/plat/multi.h9
-rw-r--r--arch/arm/plat-omap/include/plat/omap-secure.h5
-rw-r--r--arch/arm/plat-omap/include/plat/omap54xx.h32
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h10
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h6
-rw-r--r--arch/arm/plat-omap/sram.c11
41 files changed, 773 insertions, 98 deletions
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index e78e8bccac30..3d450f65a17b 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -47,3 +47,6 @@ Boards:
47 47
48- AM335X EVM : Software Developement Board for AM335x 48- AM335X EVM : Software Developement Board for AM335x
49 compatible = "ti,am335x-evm", "ti,am33xx", "ti,omap3" 49 compatible = "ti,am335x-evm", "ti,am33xx", "ti,omap3"
50
51- OMAP5 EVM : Evaluation Module
52 compatible = "ti,omap5-evm", "ti,omap5"
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e7fbe53cbbf5..7e3d9317c0bf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1595,6 +1595,7 @@ config ARCH_NR_GPIO
1595 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA 1595 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1596 default 355 if ARCH_U8500 1596 default 355 if ARCH_U8500
1597 default 264 if MACH_H4700 1597 default 264 if MACH_H4700
1598 default 512 if SOC_OMAP5
1598 default 0 1599 default 0
1599 help 1600 help
1600 Maximum number of GPIOs in the system. 1601 Maximum number of GPIOs in the system.
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
new file mode 100644
index 000000000000..200c39ad1c82
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -0,0 +1,20 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap5.dtsi"
11
12/ {
13 model = "TI OMAP5 EVM board";
14 compatible = "ti,omap5-evm", "ti,omap5";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x40000000>; /* 1 GB */
19 };
20};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
new file mode 100644
index 000000000000..57e527083746
--- /dev/null
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -0,0 +1,184 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10/*
11 * Carveout for multimedia usecases
12 * It should be the last 48MB of the first 512MB memory part
13 * In theory, it should not even exist. That zone should be reserved
14 * dynamically during the .reserve callback.
15 */
16/memreserve/ 0x9d000000 0x03000000;
17
18/include/ "skeleton.dtsi"
19
20/ {
21 compatible = "ti,omap5";
22 interrupt-parent = <&gic>;
23
24 aliases {
25 serial0 = &uart1;
26 serial1 = &uart2;
27 serial2 = &uart3;
28 serial3 = &uart4;
29 serial4 = &uart5;
30 serial5 = &uart6;
31 };
32
33 cpus {
34 cpu@0 {
35 compatible = "arm,cortex-a15";
36 };
37 cpu@1 {
38 compatible = "arm,cortex-a15";
39 };
40 };
41
42 /*
43 * The soc node represents the soc top level view. It is uses for IPs
44 * that are not memory mapped in the MPU view or for the MPU itself.
45 */
46 soc {
47 compatible = "ti,omap-infra";
48 mpu {
49 compatible = "ti,omap5-mpu";
50 ti,hwmods = "mpu";
51 };
52 };
53
54 /*
55 * XXX: Use a flat representation of the OMAP3 interconnect.
56 * The real OMAP interconnect network is quite complex.
57 * Since that will not bring real advantage to represent that in DT for
58 * the moment, just use a fake OCP bus entry to represent the whole bus
59 * hierarchy.
60 */
61 ocp {
62 compatible = "ti,omap4-l3-noc", "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 ranges;
66 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
67
68 gic: interrupt-controller@48211000 {
69 compatible = "arm,cortex-a15-gic";
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 reg = <0x48211000 0x1000>,
73 <0x48212000 0x1000>;
74 };
75
76 gpio1: gpio@4ae10000 {
77 compatible = "ti,omap4-gpio";
78 ti,hwmods = "gpio1";
79 gpio-controller;
80 #gpio-cells = <2>;
81 interrupt-controller;
82 #interrupt-cells = <1>;
83 };
84
85 gpio2: gpio@48055000 {
86 compatible = "ti,omap4-gpio";
87 ti,hwmods = "gpio2";
88 gpio-controller;
89 #gpio-cells = <2>;
90 interrupt-controller;
91 #interrupt-cells = <1>;
92 };
93
94 gpio3: gpio@48057000 {
95 compatible = "ti,omap4-gpio";
96 ti,hwmods = "gpio3";
97 gpio-controller;
98 #gpio-cells = <2>;
99 interrupt-controller;
100 #interrupt-cells = <1>;
101 };
102
103 gpio4: gpio@48059000 {
104 compatible = "ti,omap4-gpio";
105 ti,hwmods = "gpio4";
106 gpio-controller;
107 #gpio-cells = <2>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
110 };
111
112 gpio5: gpio@4805b000 {
113 compatible = "ti,omap4-gpio";
114 ti,hwmods = "gpio5";
115 gpio-controller;
116 #gpio-cells = <2>;
117 interrupt-controller;
118 #interrupt-cells = <1>;
119 };
120
121 gpio6: gpio@4805d000 {
122 compatible = "ti,omap4-gpio";
123 ti,hwmods = "gpio6";
124 gpio-controller;
125 #gpio-cells = <2>;
126 interrupt-controller;
127 #interrupt-cells = <1>;
128 };
129
130 gpio7: gpio@48051000 {
131 compatible = "ti,omap4-gpio";
132 ti,hwmods = "gpio7";
133 gpio-controller;
134 #gpio-cells = <2>;
135 interrupt-controller;
136 #interrupt-cells = <1>;
137 };
138
139 gpio8: gpio@48053000 {
140 compatible = "ti,omap4-gpio";
141 ti,hwmods = "gpio8";
142 gpio-controller;
143 #gpio-cells = <2>;
144 interrupt-controller;
145 #interrupt-cells = <1>;
146 };
147
148 uart1: serial@4806a000 {
149 compatible = "ti,omap4-uart";
150 ti,hwmods = "uart1";
151 clock-frequency = <48000000>;
152 };
153
154 uart2: serial@4806c000 {
155 compatible = "ti,omap4-uart";
156 ti,hwmods = "uart2";
157 clock-frequency = <48000000>;
158 };
159
160 uart3: serial@48020000 {
161 compatible = "ti,omap4-uart";
162 ti,hwmods = "uart3";
163 clock-frequency = <48000000>;
164 };
165
166 uart4: serial@4806e000 {
167 compatible = "ti,omap4-uart";
168 ti,hwmods = "uart4";
169 clock-frequency = <48000000>;
170 };
171
172 uart5: serial@48066000 {
173 compatible = "ti,omap5-uart";
174 ti,hwmods = "uart5";
175 clock-frequency = <48000000>;
176 };
177
178 uart6: serial@48068000 {
179 compatible = "ti,omap6-uart";
180 ti,hwmods = "uart6";
181 clock-frequency = <48000000>;
182 };
183 };
184};
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 9854ff4279e0..5c903708974c 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -236,3 +236,4 @@ CONFIG_CRC_T10DIF=y
236CONFIG_CRC_ITU_T=y 236CONFIG_CRC_ITU_T=y
237CONFIG_CRC7=y 237CONFIG_CRC7=y
238CONFIG_LIBCRC32C=y 238CONFIG_LIBCRC32C=y
239CONFIG_SOC_OMAP5=y
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 6c934778357b..90d0f85afba5 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -9,7 +9,7 @@ config ARCH_OMAP2PLUS_TYPICAL
9 select REGULATOR 9 select REGULATOR
10 select PM_RUNTIME 10 select PM_RUNTIME
11 select VFP 11 select VFP
12 select NEON if ARCH_OMAP3 || ARCH_OMAP4 12 select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
13 select SERIAL_OMAP 13 select SERIAL_OMAP
14 select SERIAL_OMAP_CONSOLE 14 select SERIAL_OMAP_CONSOLE
15 select I2C 15 select I2C
@@ -61,6 +61,12 @@ config ARCH_OMAP4
61 select USB_ARCH_HAS_EHCI if USB_SUPPORT 61 select USB_ARCH_HAS_EHCI if USB_SUPPORT
62 select ARM_CPU_SUSPEND if PM 62 select ARM_CPU_SUSPEND if PM
63 63
64config SOC_OMAP5
65 bool "TI OMAP5"
66 select CPU_V7
67 select ARM_GIC
68 select HAVE_SMP
69
64comment "OMAP Core Type" 70comment "OMAP Core Type"
65 depends on ARCH_OMAP2 71 depends on ARCH_OMAP2
66 72
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 240f1969f2ad..238c5a3954b8 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
17obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) 17obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
18obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) 18obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
19obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) 19obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
20obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
20 21
21ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) 22ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
22obj-y += mcbsp.o 23obj-y += mcbsp.o
@@ -29,8 +30,10 @@ obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
29 30
30obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o 31obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
31obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o 32obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
32obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o 33omap-4-5-common = omap4-common.o omap-wakeupgen.o \
33obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o 34 sleep44xx.o
35obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common)
36obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common)
34 37
35plus_sec := $(call as-instr,.arch_extension sec,+sec) 38plus_sec := $(call as-instr,.arch_extension sec,+sec)
36AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) 39AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
@@ -70,6 +73,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
70obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o 73obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
71obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o 74obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
72obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o 75obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
76obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o
73obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o 77obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
74obj-$(CONFIG_PM_DEBUG) += pm-debug.o 78obj-$(CONFIG_PM_DEBUG) += pm-debug.o
75obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o 79obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
@@ -85,14 +89,16 @@ endif
85endif 89endif
86 90
87# PRCM 91# PRCM
92omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \
93 prcm_mpu44xx.o prminst44xx.o \
94 vc44xx_data.o vp44xx_data.o
88obj-y += prm_common.o 95obj-y += prm_common.o
89obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o 96obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
90obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o 97obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
91obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o 98obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
92obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o
93obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o
94obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o
95obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o 99obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o
100obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o
101obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
96 102
97# OMAP voltage domains 103# OMAP voltage domains
98voltagedomain-common := voltage.o vc.o vp.o 104voltagedomain-common := voltage.o vc.o vp.o
@@ -104,6 +110,7 @@ obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
104obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o 110obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
105obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) 111obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common)
106obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o 112obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
113obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
107 114
108# OMAP powerdomain framework 115# OMAP powerdomain framework
109powerdomain-common += powerdomain.o powerdomain-common.o 116powerdomain-common += powerdomain.o powerdomain-common.o
@@ -121,6 +128,8 @@ obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
121obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) 128obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
122obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o 129obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o
123obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o 130obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
131obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
132obj-$(CONFIG_SOC_OMAP5) += powerdomain44xx.o
124 133
125# PRCM clockdomain control 134# PRCM clockdomain control
126clockdomain-common += clockdomain.o 135clockdomain-common += clockdomain.o
@@ -139,6 +148,8 @@ obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
139obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) 148obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
140obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o 149obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o
141obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o 150obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
151obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
152obj-$(CONFIG_SOC_OMAP5) += clockdomain44xx.o
142 153
143# Clock framework 154# Clock framework
144obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o 155obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@@ -157,6 +168,8 @@ obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
157obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o 168obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
158obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o 169obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
159obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o 170obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
171obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
172obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
160 173
161# OMAP2 clock rate set data (old "OPP" data) 174# OMAP2 clock rate set data (old "OPP" data)
162obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o 175obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
@@ -184,6 +197,7 @@ obj-$(CONFIG_OMAP3_EMU) += emu.o
184# L3 interconnect 197# L3 interconnect
185obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o 198obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o
186obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o 199obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o
200obj-$(CONFIG_SOC_OMAP5) += omap_l3_noc.o
187 201
188obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o 202obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
189mailbox_mach-objs := mailbox.o 203mailbox_mach-objs := mailbox.o
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 2f2abfb82d84..6f93a20536ea 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -25,23 +25,12 @@
25#include "common-board-devices.h" 25#include "common-board-devices.h"
26 26
27#if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)) 27#if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
28#define omap_intc_of_init NULL 28#define intc_of_init NULL
29#endif 29#endif
30#ifndef CONFIG_ARCH_OMAP4 30#ifndef CONFIG_ARCH_OMAP4
31#define gic_of_init NULL 31#define gic_of_init NULL
32#endif 32#endif
33 33
34static struct of_device_id irq_match[] __initdata = {
35 { .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
36 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
37 { }
38};
39
40static void __init omap_init_irq(void)
41{
42 of_irq_init(irq_match);
43}
44
45static struct of_device_id omap_dt_match_table[] __initdata = { 34static struct of_device_id omap_dt_match_table[] __initdata = {
46 { .compatible = "simple-bus", }, 35 { .compatible = "simple-bus", },
47 { .compatible = "ti,omap-infra", }, 36 { .compatible = "ti,omap-infra", },
@@ -65,7 +54,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
65 .reserve = omap_reserve, 54 .reserve = omap_reserve,
66 .map_io = omap242x_map_io, 55 .map_io = omap242x_map_io,
67 .init_early = omap2420_init_early, 56 .init_early = omap2420_init_early,
68 .init_irq = omap_init_irq, 57 .init_irq = omap_intc_of_init,
69 .handle_irq = omap2_intc_handle_irq, 58 .handle_irq = omap2_intc_handle_irq,
70 .init_machine = omap_generic_init, 59 .init_machine = omap_generic_init,
71 .timer = &omap2_timer, 60 .timer = &omap2_timer,
@@ -84,7 +73,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
84 .reserve = omap_reserve, 73 .reserve = omap_reserve,
85 .map_io = omap243x_map_io, 74 .map_io = omap243x_map_io,
86 .init_early = omap2430_init_early, 75 .init_early = omap2430_init_early,
87 .init_irq = omap_init_irq, 76 .init_irq = omap_intc_of_init,
88 .handle_irq = omap2_intc_handle_irq, 77 .handle_irq = omap2_intc_handle_irq,
89 .init_machine = omap_generic_init, 78 .init_machine = omap_generic_init,
90 .timer = &omap2_timer, 79 .timer = &omap2_timer,
@@ -103,7 +92,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
103 .reserve = omap_reserve, 92 .reserve = omap_reserve,
104 .map_io = omap3_map_io, 93 .map_io = omap3_map_io,
105 .init_early = omap3430_init_early, 94 .init_early = omap3430_init_early,
106 .init_irq = omap_init_irq, 95 .init_irq = omap_intc_of_init,
107 .handle_irq = omap3_intc_handle_irq, 96 .handle_irq = omap3_intc_handle_irq,
108 .init_machine = omap_generic_init, 97 .init_machine = omap_generic_init,
109 .timer = &omap3_timer, 98 .timer = &omap3_timer,
@@ -122,7 +111,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
122 .reserve = omap_reserve, 111 .reserve = omap_reserve,
123 .map_io = am33xx_map_io, 112 .map_io = am33xx_map_io,
124 .init_early = am33xx_init_early, 113 .init_early = am33xx_init_early,
125 .init_irq = omap_init_irq, 114 .init_irq = omap_intc_of_init,
126 .handle_irq = omap3_intc_handle_irq, 115 .handle_irq = omap3_intc_handle_irq,
127 .init_machine = omap_generic_init, 116 .init_machine = omap_generic_init,
128 .timer = &omap3_am33xx_timer, 117 .timer = &omap3_am33xx_timer,
@@ -140,7 +129,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
140 .reserve = omap_reserve, 129 .reserve = omap_reserve,
141 .map_io = omap4_map_io, 130 .map_io = omap4_map_io,
142 .init_early = omap4430_init_early, 131 .init_early = omap4430_init_early,
143 .init_irq = omap_init_irq, 132 .init_irq = omap_gic_of_init,
144 .handle_irq = gic_handle_irq, 133 .handle_irq = gic_handle_irq,
145 .init_machine = omap_generic_init, 134 .init_machine = omap_generic_init,
146 .init_late = omap4430_init_late, 135 .init_late = omap4430_init_late,
@@ -149,3 +138,22 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
149 .restart = omap_prcm_restart, 138 .restart = omap_prcm_restart,
150MACHINE_END 139MACHINE_END
151#endif 140#endif
141
142#ifdef CONFIG_SOC_OMAP5
143static const char *omap5_boards_compat[] __initdata = {
144 "ti,omap5",
145 NULL,
146};
147
148DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
149 .reserve = omap_reserve,
150 .map_io = omap5_map_io,
151 .init_early = omap5_init_early,
152 .init_irq = omap_gic_of_init,
153 .handle_irq = gic_handle_irq,
154 .init_machine = omap_generic_init,
155 .timer = &omap5_timer,
156 .dt_compat = omap5_boards_compat,
157 .restart = omap_prcm_restart,
158MACHINE_END
159#endif
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 73d2a0b9ca04..069f9725b1c3 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -178,3 +178,27 @@ void __init omap4_map_io(void)
178} 178}
179#endif 179#endif
180 180
181#if defined(CONFIG_SOC_OMAP5)
182static struct omap_globals omap5_globals = {
183 .class = OMAP54XX_CLASS,
184 .tap = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
185 .ctrl = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
186 .ctrl_pad = OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE),
187 .prm = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE),
188 .cm = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
189 .cm2 = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE),
190 .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE),
191};
192
193void __init omap2_set_globals_5xxx(void)
194{
195 omap2_set_globals_tap(&omap5_globals);
196 omap2_set_globals_control(&omap5_globals);
197 omap2_set_globals_prcm(&omap5_globals);
198}
199
200void __init omap5_map_io(void)
201{
202 omap5_map_common_io();
203}
204#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 404f172d95a8..1f65b1871c23 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -115,6 +115,14 @@ static inline int omap_mux_late_init(void)
115} 115}
116#endif 116#endif
117 117
118#ifdef CONFIG_SOC_OMAP5
119extern void omap5_map_common_io(void);
120#else
121static inline void omap5_map_common_io(void)
122{
123}
124#endif
125
118extern void omap2_init_common_infrastructure(void); 126extern void omap2_init_common_infrastructure(void);
119 127
120extern struct sys_timer omap2_timer; 128extern struct sys_timer omap2_timer;
@@ -122,6 +130,7 @@ extern struct sys_timer omap3_timer;
122extern struct sys_timer omap3_secure_timer; 130extern struct sys_timer omap3_secure_timer;
123extern struct sys_timer omap3_am33xx_timer; 131extern struct sys_timer omap3_am33xx_timer;
124extern struct sys_timer omap4_timer; 132extern struct sys_timer omap4_timer;
133extern struct sys_timer omap5_timer;
125 134
126void omap2420_init_early(void); 135void omap2420_init_early(void);
127void omap2430_init_early(void); 136void omap2430_init_early(void);
@@ -134,6 +143,7 @@ void am35xx_init_early(void);
134void ti81xx_init_early(void); 143void ti81xx_init_early(void);
135void am33xx_init_early(void); 144void am33xx_init_early(void);
136void omap4430_init_early(void); 145void omap4430_init_early(void);
146void omap5_init_early(void);
137void omap3_init_late(void); /* Do not use this one */ 147void omap3_init_late(void); /* Do not use this one */
138void omap4430_init_late(void); 148void omap4430_init_late(void);
139void omap2420_init_late(void); 149void omap2420_init_late(void);
@@ -169,6 +179,7 @@ void omap2_set_globals_242x(void);
169void omap2_set_globals_243x(void); 179void omap2_set_globals_243x(void);
170void omap2_set_globals_3xxx(void); 180void omap2_set_globals_3xxx(void);
171void omap2_set_globals_443x(void); 181void omap2_set_globals_443x(void);
182void omap2_set_globals_5xxx(void);
172void omap2_set_globals_ti81xx(void); 183void omap2_set_globals_ti81xx(void);
173void omap2_set_globals_am33xx(void); 184void omap2_set_globals_am33xx(void);
174 185
@@ -188,6 +199,7 @@ void omap243x_map_io(void);
188void omap3_map_io(void); 199void omap3_map_io(void);
189void am33xx_map_io(void); 200void am33xx_map_io(void);
190void omap4_map_io(void); 201void omap4_map_io(void);
202void omap5_map_io(void);
191void ti81xx_map_io(void); 203void ti81xx_map_io(void);
192void omap_barriers_init(void); 204void omap_barriers_init(void);
193 205
@@ -227,6 +239,8 @@ void omap3_intc_prepare_idle(void);
227void omap3_intc_resume_idle(void); 239void omap3_intc_resume_idle(void);
228void omap2_intc_handle_irq(struct pt_regs *regs); 240void omap2_intc_handle_irq(struct pt_regs *regs);
229void omap3_intc_handle_irq(struct pt_regs *regs); 241void omap3_intc_handle_irq(struct pt_regs *regs);
242void omap_intc_of_init(void);
243void omap_gic_of_init(void);
230 244
231#ifdef CONFIG_CACHE_L2X0 245#ifdef CONFIG_CACHE_L2X0
232extern void __iomem *omap4_get_l2cache_base(void); 246extern void __iomem *omap4_get_l2cache_base(void);
@@ -234,10 +248,10 @@ extern void __iomem *omap4_get_l2cache_base(void);
234 248
235struct device_node; 249struct device_node;
236#ifdef CONFIG_OF 250#ifdef CONFIG_OF
237int __init omap_intc_of_init(struct device_node *node, 251int __init intc_of_init(struct device_node *node,
238 struct device_node *parent); 252 struct device_node *parent);
239#else 253#else
240int __init omap_intc_of_init(struct device_node *node, 254int __init intc_of_init(struct device_node *node,
241 struct device_node *parent) 255 struct device_node *parent)
242{ 256{
243 return 0; 257 return 0;
@@ -264,6 +278,7 @@ extern void omap_secondary_startup(void);
264extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); 278extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
265extern void omap_auxcoreboot_addr(u32 cpu_addr); 279extern void omap_auxcoreboot_addr(u32 cpu_addr);
266extern u32 omap_read_auxcoreboot0(void); 280extern u32 omap_read_auxcoreboot0(void);
281extern void omap5_secondary_startup(void);
267#endif 282#endif
268 283
269#if defined(CONFIG_SMP) && defined(CONFIG_PM) 284#if defined(CONFIG_SMP) && defined(CONFIG_PM)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 295b39047a71..b8cdc8531b60 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -253,6 +253,10 @@
253/* TI81XX CONTROL_DEVCONF register offsets */ 253/* TI81XX CONTROL_DEVCONF register offsets */
254#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) 254#define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000)
255 255
256/* OMAP54XX CONTROL STATUS register */
257#define OMAP5XXX_CONTROL_STATUS 0x134
258#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
259
256/* 260/*
257 * REVISIT: This list of registers is not comprehensive - there are more 261 * REVISIT: This list of registers is not comprehensive - there are more
258 * that should be added. 262 * that should be added.
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 7b4b9327e543..be3e059a4017 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -84,7 +84,7 @@ static int __init omap4_l3_init(void)
84 * To avoid code running on other OMAPs in 84 * To avoid code running on other OMAPs in
85 * multi-omap builds 85 * multi-omap builds
86 */ 86 */
87 if (!(cpu_is_omap44xx())) 87 if (!cpu_is_omap44xx() && !soc_is_omap54xx())
88 return -ENODEV; 88 return -ENODEV;
89 89
90 for (i = 0; i < L3_MODULES; i++) { 90 for (i = 0; i < L3_MODULES; i++) {
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 2286410671e7..b2b5759ab0fe 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -727,7 +727,8 @@ static int __init gpmc_init(void)
727 ck = "gpmc_fck"; 727 ck = "gpmc_fck";
728 l = OMAP34XX_GPMC_BASE; 728 l = OMAP34XX_GPMC_BASE;
729 gpmc_irq = INT_34XX_GPMC_IRQ; 729 gpmc_irq = INT_34XX_GPMC_IRQ;
730 } else if (cpu_is_omap44xx()) { 730 } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
731 /* Base address and irq number are same for OMAP4/5 */
731 ck = "gpmc_ck"; 732 ck = "gpmc_ck";
732 l = OMAP44XX_GPMC_BASE; 733 l = OMAP44XX_GPMC_BASE;
733 gpmc_irq = OMAP44XX_IRQ_GPMC; 734 gpmc_irq = OMAP44XX_IRQ_GPMC;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 37eb95aaf2f6..40373db649aa 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -50,6 +50,11 @@ int omap_type(void)
50 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 50 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
51 } else if (cpu_is_omap44xx()) { 51 } else if (cpu_is_omap44xx()) {
52 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); 52 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
53 } else if (soc_is_omap54xx()) {
54 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
55 val &= OMAP5_DEVICETYPE_MASK;
56 val >>= 6;
57 goto out;
53 } else { 58 } else {
54 pr_err("Cannot detect omap type!\n"); 59 pr_err("Cannot detect omap type!\n");
55 goto out; 60 goto out;
@@ -100,7 +105,7 @@ static u16 tap_prod_id;
100 105
101void omap_get_die_id(struct omap_die_id *odi) 106void omap_get_die_id(struct omap_die_id *odi)
102{ 107{
103 if (cpu_is_omap44xx()) { 108 if (cpu_is_omap44xx() || soc_is_omap54xx()) {
104 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); 109 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
105 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); 110 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
106 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); 111 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
@@ -513,6 +518,41 @@ void __init omap4xxx_check_revision(void)
513 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); 518 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
514} 519}
515 520
521void __init omap5xxx_check_revision(void)
522{
523 u32 idcode;
524 u16 hawkeye;
525 u8 rev;
526
527 idcode = read_tap_reg(OMAP_TAP_IDCODE);
528 hawkeye = (idcode >> 12) & 0xffff;
529 rev = (idcode >> 28) & 0xff;
530 switch (hawkeye) {
531 case 0xb942:
532 switch (rev) {
533 case 0:
534 default:
535 omap_revision = OMAP5430_REV_ES1_0;
536 }
537 break;
538
539 case 0xb998:
540 switch (rev) {
541 case 0:
542 default:
543 omap_revision = OMAP5432_REV_ES1_0;
544 }
545 break;
546
547 default:
548 /* Unknown default to latest silicon rev as default*/
549 omap_revision = OMAP5430_REV_ES1_0;
550 }
551
552 pr_info("OMAP%04x ES%d.0\n",
553 omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
554}
555
516/* 556/*
517 * Set up things for map_io and processor detection later on. Gets called 557 * Set up things for map_io and processor detection later on. Gets called
518 * pretty much first thing from board init. For multi-omap, this gets 558 * pretty much first thing from board init. For multi-omap, this gets
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index d7f844a99a7b..93d10de7129f 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -60,12 +60,12 @@ omap_uart_lsr: .word 0
60 beq 23f @ configure OMAP2UART3 60 beq 23f @ configure OMAP2UART3
61 cmp \rp, #OMAP3UART3 @ only on 34xx 61 cmp \rp, #OMAP3UART3 @ only on 34xx
62 beq 33f @ configure OMAP3UART3 62 beq 33f @ configure OMAP3UART3
63 cmp \rp, #OMAP4UART3 @ only on 44xx 63 cmp \rp, #OMAP4UART3 @ only on 44xx/54xx
64 beq 43f @ configure OMAP4UART3 64 beq 43f @ configure OMAP4/5UART3
65 cmp \rp, #OMAP3UART4 @ only on 36xx 65 cmp \rp, #OMAP3UART4 @ only on 36xx
66 beq 34f @ configure OMAP3UART4 66 beq 34f @ configure OMAP3UART4
67 cmp \rp, #OMAP4UART4 @ only on 44xx 67 cmp \rp, #OMAP4UART4 @ only on 44xx/54xx
68 beq 44f @ configure OMAP4UART4 68 beq 44f @ configure OMAP4/5UART4
69 cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different 69 cmp \rp, #TI81XXUART1 @ ti81Xx UART offsets different
70 beq 81f @ configure UART1 70 beq 81f @ configure UART1
71 cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different 71 cmp \rp, #TI81XXUART2 @ ti81Xx UART offsets different
diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
index 548de90b58c2..b0fd16f5c391 100644
--- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
@@ -11,15 +11,20 @@
11#ifndef OMAP_ARCH_WAKEUPGEN_H 11#ifndef OMAP_ARCH_WAKEUPGEN_H
12#define OMAP_ARCH_WAKEUPGEN_H 12#define OMAP_ARCH_WAKEUPGEN_H
13 13
14/* OMAP4 and OMAP5 has same base address */
15#define OMAP_WKUPGEN_BASE 0x48281000
16
14#define OMAP_WKG_CONTROL_0 0x00 17#define OMAP_WKG_CONTROL_0 0x00
15#define OMAP_WKG_ENB_A_0 0x10 18#define OMAP_WKG_ENB_A_0 0x10
16#define OMAP_WKG_ENB_B_0 0x14 19#define OMAP_WKG_ENB_B_0 0x14
17#define OMAP_WKG_ENB_C_0 0x18 20#define OMAP_WKG_ENB_C_0 0x18
18#define OMAP_WKG_ENB_D_0 0x1c 21#define OMAP_WKG_ENB_D_0 0x1c
22#define OMAP_WKG_ENB_E_0 0x20
19#define OMAP_WKG_ENB_A_1 0x410 23#define OMAP_WKG_ENB_A_1 0x410
20#define OMAP_WKG_ENB_B_1 0x414 24#define OMAP_WKG_ENB_B_1 0x414
21#define OMAP_WKG_ENB_C_1 0x418 25#define OMAP_WKG_ENB_C_1 0x418
22#define OMAP_WKG_ENB_D_1 0x41c 26#define OMAP_WKG_ENB_D_1 0x41c
27#define OMAP_WKG_ENB_E_1 0x420
23#define OMAP_AUX_CORE_BOOT_0 0x800 28#define OMAP_AUX_CORE_BOOT_0 0x800
24#define OMAP_AUX_CORE_BOOT_1 0x804 29#define OMAP_AUX_CORE_BOOT_1 0x804
25#define OMAP_PTMSYNCREQ_MASK 0xc00 30#define OMAP_PTMSYNCREQ_MASK 0xc00
@@ -28,4 +33,6 @@
28#define OMAP_TIMESTAMPCYCLEHI 0xc0c 33#define OMAP_TIMESTAMPCYCLEHI 0xc0c
29 34
30extern int __init omap_wakeupgen_init(void); 35extern int __init omap_wakeupgen_init(void);
36extern void __iomem *omap_get_wakeupgen_base(void);
37extern int omap_secure_apis_support(void);
31#endif 38#endif
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index cb6c11cd8df9..8976be90c8e8 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -233,6 +233,35 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
233}; 233};
234#endif 234#endif
235 235
236#ifdef CONFIG_SOC_OMAP5
237static struct map_desc omap54xx_io_desc[] __initdata = {
238 {
239 .virtual = L3_54XX_VIRT,
240 .pfn = __phys_to_pfn(L3_54XX_PHYS),
241 .length = L3_54XX_SIZE,
242 .type = MT_DEVICE,
243 },
244 {
245 .virtual = L4_54XX_VIRT,
246 .pfn = __phys_to_pfn(L4_54XX_PHYS),
247 .length = L4_54XX_SIZE,
248 .type = MT_DEVICE,
249 },
250 {
251 .virtual = L4_WK_54XX_VIRT,
252 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
253 .length = L4_WK_54XX_SIZE,
254 .type = MT_DEVICE,
255 },
256 {
257 .virtual = L4_PER_54XX_VIRT,
258 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
259 .length = L4_PER_54XX_SIZE,
260 .type = MT_DEVICE,
261 },
262};
263#endif
264
236#ifdef CONFIG_SOC_OMAP2420 265#ifdef CONFIG_SOC_OMAP2420
237void __init omap242x_map_common_io(void) 266void __init omap242x_map_common_io(void)
238{ 267{
@@ -278,6 +307,12 @@ void __init omap44xx_map_common_io(void)
278} 307}
279#endif 308#endif
280 309
310#ifdef CONFIG_SOC_OMAP5
311void __init omap5_map_common_io(void)
312{
313 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
314}
315#endif
281/* 316/*
282 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters 317 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
283 * 318 *
@@ -513,6 +548,15 @@ void __init omap4430_init_late(void)
513} 548}
514#endif 549#endif
515 550
551#ifdef CONFIG_SOC_OMAP5
552void __init omap5_init_early(void)
553{
554 omap2_set_globals_5xxx();
555 omap5xxx_check_revision();
556 omap_common_init_early();
557}
558#endif
559
516void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 560void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
517 struct omap_sdrc_params *sdrc_cs1) 561 struct omap_sdrc_params *sdrc_cs1)
518{ 562{
diff --git a/arch/arm/mach-omap2/iomap.h b/arch/arm/mach-omap2/iomap.h
index 80b88921faba..cce2b65039f1 100644
--- a/arch/arm/mach-omap2/iomap.h
+++ b/arch/arm/mach-omap2/iomap.h
@@ -1,6 +1,14 @@
1/* 1/*
2 * IO mappings for OMAP2+ 2 * IO mappings for OMAP2+
3 * 3 *
4 * IO definitions for TI OMAP processors and boards
5 *
6 * Copied from arch/arm/mach-sa1100/include/mach/io.h
7 * Copyright (C) 1997-1999 Russell King
8 *
9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
4 * This program is free software; you can redistribute it and/or modify it 12 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the 13 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your 14 * Free Software Foundation; either version 2 of the License, or (at your
@@ -166,4 +174,23 @@
166 /* 0x49000000 --> 0xfb000000 */ 174 /* 0x49000000 --> 0xfb000000 */
167#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) 175#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
168#define L4_ABE_44XX_SIZE SZ_1M 176#define L4_ABE_44XX_SIZE SZ_1M
177/*
178 * ----------------------------------------------------------------------------
179 * Omap5 specific IO mapping
180 * ----------------------------------------------------------------------------
181 */
182#define L3_54XX_PHYS L3_54XX_BASE /* 0x44000000 --> 0xf8000000 */
183#define L3_54XX_VIRT (L3_54XX_PHYS + OMAP4_L3_IO_OFFSET)
184#define L3_54XX_SIZE SZ_1M
185
186#define L4_54XX_PHYS L4_54XX_BASE /* 0x4a000000 --> 0xfc000000 */
187#define L4_54XX_VIRT (L4_54XX_PHYS + OMAP2_L4_IO_OFFSET)
188#define L4_54XX_SIZE SZ_4M
189
190#define L4_WK_54XX_PHYS L4_WK_54XX_BASE /* 0x4ae00000 --> 0xfce00000 */
191#define L4_WK_54XX_VIRT (L4_WK_54XX_PHYS + OMAP2_L4_IO_OFFSET)
192#define L4_WK_54XX_SIZE SZ_2M
169 193
194#define L4_PER_54XX_PHYS L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */
195#define L4_PER_54XX_VIRT (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET)
196#define L4_PER_54XX_SIZE SZ_4M
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index d5b34febd82d..8467beb122b5 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -21,6 +21,7 @@
21#include <linux/irqdomain.h> 21#include <linux/irqdomain.h>
22#include <linux/of.h> 22#include <linux/of.h>
23#include <linux/of_address.h> 23#include <linux/of_address.h>
24#include <linux/of_irq.h>
24 25
25#include <mach/hardware.h> 26#include <mach/hardware.h>
26 27
@@ -258,7 +259,7 @@ asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs
258 omap_intc_handle_irq(base_addr, regs); 259 omap_intc_handle_irq(base_addr, regs);
259} 260}
260 261
261int __init omap_intc_of_init(struct device_node *node, 262int __init intc_of_init(struct device_node *node,
262 struct device_node *parent) 263 struct device_node *parent)
263{ 264{
264 struct resource res; 265 struct resource res;
@@ -280,6 +281,16 @@ int __init omap_intc_of_init(struct device_node *node,
280 return 0; 281 return 0;
281} 282}
282 283
284static struct of_device_id irq_match[] __initdata = {
285 { .compatible = "ti,omap2-intc", .data = intc_of_init, },
286 { }
287};
288
289void __init omap_intc_of_init(void)
290{
291 of_irq_init(irq_match);
292}
293
283#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) 294#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
284static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; 295static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
285 296
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 503ac777a2ba..502e3135aad3 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -19,6 +19,27 @@
19#include <linux/init.h> 19#include <linux/init.h>
20 20
21 __CPUINIT 21 __CPUINIT
22
23/* Physical address needed since MMU not enabled yet on secondary core */
24#define AUX_CORE_BOOT0_PA 0x48281800
25
26/*
27 * OMAP5 specific entry point for secondary CPU to jump from ROM
28 * code. This routine also provides a holding flag into which
29 * secondary core is held until we're ready for it to initialise.
30 * The primary core will update this flag using a hardware
31+ * register AuxCoreBoot0.
32 */
33ENTRY(omap5_secondary_startup)
34wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
35 ldr r0, [r2]
36 mov r0, r0, lsr #5
37 mrc p15, 0, r4, c0, c0, 5
38 and r4, r4, #0x0f
39 cmp r0, r4
40 bne wait
41 b secondary_startup
42END(omap5_secondary_startup)
22/* 43/*
23 * OMAP4 specific entry point for secondary CPU to jump from ROM 44 * OMAP4 specific entry point for secondary CPU to jump from ROM
24 * code. This routine also provides a holding flag into which 45 * code. This routine also provides a holding flag into which
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 56c345b8b931..414083b427df 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -17,8 +17,10 @@
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/errno.h> 18#include <linux/errno.h>
19#include <linux/smp.h> 19#include <linux/smp.h>
20#include <linux/io.h>
20 21
21#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
23#include <mach/omap-wakeupgen.h>
22 24
23#include "common.h" 25#include "common.h"
24 26
@@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
35 */ 37 */
36void __ref platform_cpu_die(unsigned int cpu) 38void __ref platform_cpu_die(unsigned int cpu)
37{ 39{
38 unsigned int this_cpu; 40 unsigned int boot_cpu = 0;
41 void __iomem *base = omap_get_wakeupgen_base();
39 42
40 flush_cache_all(); 43 flush_cache_all();
41 dsb(); 44 dsb();
@@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
43 /* 46 /*
44 * we're ready for shutdown now, so do it 47 * we're ready for shutdown now, so do it
45 */ 48 */
46 if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0) 49 if (omap_secure_apis_support()) {
47 pr_err("Secure clear status failed\n"); 50 if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
51 pr_err("Secure clear status failed\n");
52 } else {
53 __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
54 }
55
48 56
49 for (;;) { 57 for (;;) {
50 /* 58 /*
51 * Enter into low power state 59 * Enter into low power state
52 */ 60 */
53 omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF); 61 omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
54 this_cpu = smp_processor_id(); 62
55 if (omap_read_auxcoreboot0() == this_cpu) { 63 if (omap_secure_apis_support())
64 boot_cpu = omap_read_auxcoreboot0();
65 else
66 boot_cpu =
67 __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
68
69 if (boot_cpu == smp_processor_id()) {
56 /* 70 /*
57 * OK, proper wakeup, we're done 71 * OK, proper wakeup, we're done
58 */ 72 */
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index deffbf1c9627..7d118b9bdd5f 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -26,11 +26,19 @@
26 26
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/omap-secure.h> 28#include <mach/omap-secure.h>
29#include <mach/omap-wakeupgen.h>
30#include <asm/cputype.h>
29 31
30#include "iomap.h" 32#include "iomap.h"
31#include "common.h" 33#include "common.h"
32#include "clockdomain.h" 34#include "clockdomain.h"
33 35
36#define CPU_MASK 0xff0ffff0
37#define CPU_CORTEX_A9 0x410FC090
38#define CPU_CORTEX_A15 0x410FC0F0
39
40#define OMAP5_CORE_COUNT 0x2
41
34/* SCU base address */ 42/* SCU base address */
35static void __iomem *scu_base; 43static void __iomem *scu_base;
36 44
@@ -73,6 +81,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
73{ 81{
74 static struct clockdomain *cpu1_clkdm; 82 static struct clockdomain *cpu1_clkdm;
75 static bool booted; 83 static bool booted;
84 void __iomem *base = omap_get_wakeupgen_base();
85
76 /* 86 /*
77 * Set synchronisation state between this boot processor 87 * Set synchronisation state between this boot processor
78 * and the secondary one 88 * and the secondary one
@@ -85,7 +95,11 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
85 * the AuxCoreBoot1 register is updated with cpu state 95 * the AuxCoreBoot1 register is updated with cpu state
86 * A barrier is added to ensure that write buffer is drained 96 * A barrier is added to ensure that write buffer is drained
87 */ 97 */
88 omap_modify_auxcoreboot0(0x200, 0xfffffdff); 98 if (omap_secure_apis_support())
99 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
100 else
101 __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
102
89 flush_cache_all(); 103 flush_cache_all();
90 smp_wmb(); 104 smp_wmb();
91 105
@@ -124,13 +138,19 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
124 138
125static void __init wakeup_secondary(void) 139static void __init wakeup_secondary(void)
126{ 140{
141 void __iomem *base = omap_get_wakeupgen_base();
127 /* 142 /*
128 * Write the address of secondary startup routine into the 143 * Write the address of secondary startup routine into the
129 * AuxCoreBoot1 where ROM code will jump and start executing 144 * AuxCoreBoot1 where ROM code will jump and start executing
130 * on secondary core once out of WFE 145 * on secondary core once out of WFE
131 * A barrier is added to ensure that write buffer is drained 146 * A barrier is added to ensure that write buffer is drained
132 */ 147 */
133 omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup)); 148 if (omap_secure_apis_support())
149 omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
150 else
151 __raw_writel(virt_to_phys(omap5_secondary_startup),
152 base + OMAP_AUX_CORE_BOOT_1);
153
134 smp_wmb(); 154 smp_wmb();
135 155
136 /* 156 /*
@@ -147,16 +167,21 @@ static void __init wakeup_secondary(void)
147 */ 167 */
148void __init smp_init_cpus(void) 168void __init smp_init_cpus(void)
149{ 169{
150 unsigned int i, ncores; 170 unsigned int i = 0, ncores = 1, cpu_id;
151 171
152 /* 172 /* Use ARM cpuid check here, as SoC detection will not work so early */
153 * Currently we can't call ioremap here because 173 cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
154 * SoC detection won't work until after init_early. 174 if (cpu_id == CPU_CORTEX_A9) {
155 */ 175 /*
156 scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE); 176 * Currently we can't call ioremap here because
157 BUG_ON(!scu_base); 177 * SoC detection won't work until after init_early.
158 178 */
159 ncores = scu_get_core_count(scu_base); 179 scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
180 BUG_ON(!scu_base);
181 ncores = scu_get_core_count(scu_base);
182 } else if (cpu_id == CPU_CORTEX_A15) {
183 ncores = OMAP5_CORE_COUNT;
184 }
160 185
161 /* sanity check */ 186 /* sanity check */
162 if (ncores > nr_cpu_ids) { 187 if (ncores > nr_cpu_ids) {
@@ -178,6 +203,7 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
178 * Initialise the SCU and wake up the secondary core using 203 * Initialise the SCU and wake up the secondary core using
179 * wakeup_secondary(). 204 * wakeup_secondary().
180 */ 205 */
181 scu_enable(scu_base); 206 if (scu_base)
207 scu_enable(scu_base);
182 wakeup_secondary(); 208 wakeup_secondary();
183} 209}
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index d811c7790350..05fdebfaa195 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -33,18 +33,23 @@
33#include "omap4-sar-layout.h" 33#include "omap4-sar-layout.h"
34#include "common.h" 34#include "common.h"
35 35
36#define NR_REG_BANKS 4 36#define MAX_NR_REG_BANKS 5
37#define MAX_IRQS 128 37#define MAX_IRQS 160
38#define WKG_MASK_ALL 0x00000000 38#define WKG_MASK_ALL 0x00000000
39#define WKG_UNMASK_ALL 0xffffffff 39#define WKG_UNMASK_ALL 0xffffffff
40#define CPU_ENA_OFFSET 0x400 40#define CPU_ENA_OFFSET 0x400
41#define CPU0_ID 0x0 41#define CPU0_ID 0x0
42#define CPU1_ID 0x1 42#define CPU1_ID 0x1
43#define OMAP4_NR_BANKS 4
44#define OMAP4_NR_IRQS 128
43 45
44static void __iomem *wakeupgen_base; 46static void __iomem *wakeupgen_base;
45static void __iomem *sar_base; 47static void __iomem *sar_base;
46static DEFINE_SPINLOCK(wakeupgen_lock); 48static DEFINE_SPINLOCK(wakeupgen_lock);
47static unsigned int irq_target_cpu[NR_IRQS]; 49static unsigned int irq_target_cpu[NR_IRQS];
50static unsigned int irq_banks = MAX_NR_REG_BANKS;
51static unsigned int max_irqs = MAX_IRQS;
52static unsigned int omap_secure_apis;
48 53
49/* 54/*
50 * Static helper functions. 55 * Static helper functions.
@@ -146,13 +151,13 @@ static void wakeupgen_unmask(struct irq_data *d)
146} 151}
147 152
148#ifdef CONFIG_HOTPLUG_CPU 153#ifdef CONFIG_HOTPLUG_CPU
149static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks); 154static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
150 155
151static void _wakeupgen_save_masks(unsigned int cpu) 156static void _wakeupgen_save_masks(unsigned int cpu)
152{ 157{
153 u8 i; 158 u8 i;
154 159
155 for (i = 0; i < NR_REG_BANKS; i++) 160 for (i = 0; i < irq_banks; i++)
156 per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu); 161 per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
157} 162}
158 163
@@ -160,7 +165,7 @@ static void _wakeupgen_restore_masks(unsigned int cpu)
160{ 165{
161 u8 i; 166 u8 i;
162 167
163 for (i = 0; i < NR_REG_BANKS; i++) 168 for (i = 0; i < irq_banks; i++)
164 wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu); 169 wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
165} 170}
166 171
@@ -168,7 +173,7 @@ static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
168{ 173{
169 u8 i; 174 u8 i;
170 175
171 for (i = 0; i < NR_REG_BANKS; i++) 176 for (i = 0; i < irq_banks; i++)
172 wakeupgen_writel(reg, i, cpu); 177 wakeupgen_writel(reg, i, cpu);
173} 178}
174 179
@@ -196,25 +201,14 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
196#endif 201#endif
197 202
198#ifdef CONFIG_CPU_PM 203#ifdef CONFIG_CPU_PM
199/* 204static inline void omap4_irq_save_context(void)
200 * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
201 * ROM code. WakeupGen IP is integrated along with GIC to manage the
202 * interrupt wakeups from CPU low power states. It manages
203 * masking/unmasking of Shared peripheral interrupts(SPI). So the
204 * interrupt enable/disable control should be in sync and consistent
205 * at WakeupGen and GIC so that interrupts are not lost.
206 */
207static void irq_save_context(void)
208{ 205{
209 u32 i, val; 206 u32 i, val;
210 207
211 if (omap_rev() == OMAP4430_REV_ES1_0) 208 if (omap_rev() == OMAP4430_REV_ES1_0)
212 return; 209 return;
213 210
214 if (!sar_base) 211 for (i = 0; i < irq_banks; i++) {
215 sar_base = omap4_get_sar_ram_base();
216
217 for (i = 0; i < NR_REG_BANKS; i++) {
218 /* Save the CPUx interrupt mask for IRQ 0 to 127 */ 212 /* Save the CPUx interrupt mask for IRQ 0 to 127 */
219 val = wakeupgen_readl(i, 0); 213 val = wakeupgen_readl(i, 0);
220 sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i); 214 sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
@@ -254,6 +248,53 @@ static void irq_save_context(void)
254 val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET); 248 val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
255 val |= SAR_BACKUP_STATUS_WAKEUPGEN; 249 val |= SAR_BACKUP_STATUS_WAKEUPGEN;
256 __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET); 250 __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
251
252}
253
254static inline void omap5_irq_save_context(void)
255{
256 u32 i, val;
257
258 for (i = 0; i < irq_banks; i++) {
259 /* Save the CPUx interrupt mask for IRQ 0 to 159 */
260 val = wakeupgen_readl(i, 0);
261 sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
262 val = wakeupgen_readl(i, 1);
263 sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
264 sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
265 sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
266 }
267
268 /* Save AuxBoot* registers */
269 val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
270 __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
271 val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
272 __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
273
274 /* Set the Backup Bit Mask status */
275 val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
276 val |= SAR_BACKUP_STATUS_WAKEUPGEN;
277 __raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
278
279}
280
281/*
282 * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
283 * ROM code. WakeupGen IP is integrated along with GIC to manage the
284 * interrupt wakeups from CPU low power states. It manages
285 * masking/unmasking of Shared peripheral interrupts(SPI). So the
286 * interrupt enable/disable control should be in sync and consistent
287 * at WakeupGen and GIC so that interrupts are not lost.
288 */
289static void irq_save_context(void)
290{
291 if (!sar_base)
292 sar_base = omap4_get_sar_ram_base();
293
294 if (soc_is_omap54xx())
295 omap5_irq_save_context();
296 else
297 omap4_irq_save_context();
257} 298}
258 299
259/* 300/*
@@ -262,9 +303,14 @@ static void irq_save_context(void)
262static void irq_sar_clear(void) 303static void irq_sar_clear(void)
263{ 304{
264 u32 val; 305 u32 val;
265 val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET); 306 u32 offset = SAR_BACKUP_STATUS_OFFSET;
307
308 if (soc_is_omap54xx())
309 offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
310
311 val = __raw_readl(sar_base + offset);
266 val &= ~SAR_BACKUP_STATUS_WAKEUPGEN; 312 val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
267 __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET); 313 __raw_writel(val, sar_base + offset);
268} 314}
269 315
270/* 316/*
@@ -336,13 +382,25 @@ static struct notifier_block irq_notifier_block = {
336 382
337static void __init irq_pm_init(void) 383static void __init irq_pm_init(void)
338{ 384{
339 cpu_pm_register_notifier(&irq_notifier_block); 385 /* FIXME: Remove this when MPU OSWR support is added */
386 if (!soc_is_omap54xx())
387 cpu_pm_register_notifier(&irq_notifier_block);
340} 388}
341#else 389#else
342static void __init irq_pm_init(void) 390static void __init irq_pm_init(void)
343{} 391{}
344#endif 392#endif
345 393
394void __iomem *omap_get_wakeupgen_base(void)
395{
396 return wakeupgen_base;
397}
398
399int omap_secure_apis_support(void)
400{
401 return omap_secure_apis;
402}
403
346/* 404/*
347 * Initialise the wakeupgen module. 405 * Initialise the wakeupgen module.
348 */ 406 */
@@ -358,12 +416,18 @@ int __init omap_wakeupgen_init(void)
358 } 416 }
359 417
360 /* Static mapping, never released */ 418 /* Static mapping, never released */
361 wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K); 419 wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K);
362 if (WARN_ON(!wakeupgen_base)) 420 if (WARN_ON(!wakeupgen_base))
363 return -ENOMEM; 421 return -ENOMEM;
364 422
423 if (cpu_is_omap44xx()) {
424 irq_banks = OMAP4_NR_BANKS;
425 max_irqs = OMAP4_NR_IRQS;
426 omap_secure_apis = 1;
427 }
428
365 /* Clear all IRQ bitmasks at wakeupGen level */ 429 /* Clear all IRQ bitmasks at wakeupGen level */
366 for (i = 0; i < NR_REG_BANKS; i++) { 430 for (i = 0; i < irq_banks; i++) {
367 wakeupgen_writel(0, i, CPU0_ID); 431 wakeupgen_writel(0, i, CPU0_ID);
368 wakeupgen_writel(0, i, CPU1_ID); 432 wakeupgen_writel(0, i, CPU1_ID);
369 } 433 }
@@ -382,7 +446,7 @@ int __init omap_wakeupgen_init(void)
382 */ 446 */
383 447
384 /* Associate all the IRQs to boot CPU like GIC init does. */ 448 /* Associate all the IRQs to boot CPU like GIC init does. */
385 for (i = 0; i < NR_IRQS; i++) 449 for (i = 0; i < max_irqs; i++)
386 irq_target_cpu[i] = boot_cpu; 450 irq_target_cpu[i] = boot_cpu;
387 451
388 irq_hotplug_init(); 452 irq_hotplug_init();
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index a8161e5f3204..c29dee998a79 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -21,6 +21,8 @@
21#include <asm/hardware/cache-l2x0.h> 21#include <asm/hardware/cache-l2x0.h>
22#include <asm/mach/map.h> 22#include <asm/mach/map.h>
23#include <asm/memblock.h> 23#include <asm/memblock.h>
24#include <linux/of_irq.h>
25#include <linux/of_platform.h>
24 26
25#include <plat/irqs.h> 27#include <plat/irqs.h>
26#include <plat/sram.h> 28#include <plat/sram.h>
@@ -210,6 +212,18 @@ static int __init omap4_sar_ram_init(void)
210} 212}
211early_initcall(omap4_sar_ram_init); 213early_initcall(omap4_sar_ram_init);
212 214
215static struct of_device_id irq_match[] __initdata = {
216 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
217 { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
218 { }
219};
220
221void __init omap_gic_of_init(void)
222{
223 omap_wakeupgen_init();
224 of_irq_init(irq_match);
225}
226
213#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) 227#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
214static int omap4_twl6030_hsmmc_late_init(struct device *dev) 228static int omap4_twl6030_hsmmc_late_init(struct device *dev)
215{ 229{
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index fe5b545ad443..e170fe803b04 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -12,7 +12,7 @@
12#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H 12#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
13 13
14/* 14/*
15 * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE 15 * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
16 */ 16 */
17#define SAR_BANK1_OFFSET 0x0000 17#define SAR_BANK1_OFFSET 0x0000
18#define SAR_BANK2_OFFSET 0x1000 18#define SAR_BANK2_OFFSET 0x1000
@@ -47,4 +47,14 @@
47#define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0) 47#define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0)
48#define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 48#define SAR_BACKUP_STATUS_WAKEUPGEN 0x10
49 49
50/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
51#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4)
52#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8)
53#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc)
54#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910)
55#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924)
56#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928)
57#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c)
58#define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800)
59
50#endif 60#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index ff76ef1d7232..2ada3642c671 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3619,7 +3619,7 @@ void __init omap_hwmod_init(void)
3619 soc_ops.assert_hardreset = _omap2_assert_hardreset; 3619 soc_ops.assert_hardreset = _omap2_assert_hardreset;
3620 soc_ops.deassert_hardreset = _omap2_deassert_hardreset; 3620 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
3621 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; 3621 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
3622 } else if (cpu_is_omap44xx()) { 3622 } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
3623 soc_ops.enable_module = _omap4_enable_module; 3623 soc_ops.enable_module = _omap4_enable_module;
3624 soc_ops.disable_module = _omap4_disable_module; 3624 soc_ops.disable_module = _omap4_disable_module;
3625 soc_ops.wait_target_ready = _omap4_wait_target_ready; 3625 soc_ops.wait_target_ready = _omap4_wait_target_ready;
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
index 90b50984cd2e..a6ce34dc4814 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -51,7 +51,9 @@ static u32 l3_targ_inst_clk1[] = {
51 0x200, /* DMM2 */ 51 0x200, /* DMM2 */
52 0x300, /* ABE */ 52 0x300, /* ABE */
53 0x400, /* L4CFG */ 53 0x400, /* L4CFG */
54 0x600 /* CLK2 PWR DISC */ 54 0x600, /* CLK2 PWR DISC */
55 0x0, /* Host CLK1 */
56 0x900 /* L4 Wakeup */
55}; 57};
56 58
57static u32 l3_targ_inst_clk2[] = { 59static u32 l3_targ_inst_clk2[] = {
@@ -72,11 +74,16 @@ static u32 l3_targ_inst_clk2[] = {
72 0xE00, /* missing in TRM corresponds to AES2*/ 74 0xE00, /* missing in TRM corresponds to AES2*/
73 0xC00, /* L4 PER3 */ 75 0xC00, /* L4 PER3 */
74 0xA00, /* L4 PER1*/ 76 0xA00, /* L4 PER1*/
75 0xB00 /* L4 PER2*/ 77 0xB00, /* L4 PER2*/
78 0x0, /* HOST CLK2 */
79 0x1800, /* CAL */
80 0x1700 /* LLI */
76}; 81};
77 82
78static u32 l3_targ_inst_clk3[] = { 83static u32 l3_targ_inst_clk3[] = {
79 0x0100 /* EMUSS */ 84 0x0100 /* EMUSS */,
85 0x0300, /* DEBUGSS_CT_TBR */
86 0x0 /* HOST CLK3 */
80}; 87};
81 88
82static struct l3_masters_data { 89static struct l3_masters_data {
@@ -110,13 +117,15 @@ static struct l3_masters_data {
110 { 0xC8, "USBHOSTFS"} 117 { 0xC8, "USBHOSTFS"}
111}; 118};
112 119
113static char *l3_targ_inst_name[L3_MODULES][18] = { 120static char *l3_targ_inst_name[L3_MODULES][21] = {
114 { 121 {
115 "DMM1", 122 "DMM1",
116 "DMM2", 123 "DMM2",
117 "ABE", 124 "ABE",
118 "L4CFG", 125 "L4CFG",
119 "CLK2 PWR DISC", 126 "CLK2 PWR DISC",
127 "HOST CLK1",
128 "L4 WAKEUP"
120 }, 129 },
121 { 130 {
122 "CORTEX M3" , 131 "CORTEX M3" ,
@@ -137,9 +146,14 @@ static char *l3_targ_inst_name[L3_MODULES][18] = {
137 "L4 PER3", 146 "L4 PER3",
138 "L4 PER1", 147 "L4 PER1",
139 "L4 PER2", 148 "L4 PER2",
149 "HOST CLK2",
150 "CAL",
151 "LLI"
140 }, 152 },
141 { 153 {
142 "EMUSS", 154 "EMUSS",
155 "DEBUG SOURCE",
156 "HOST CLK3"
143 }, 157 },
144}; 158};
145 159
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 6da3ba483ad1..44485a8f2556 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -416,7 +416,7 @@ extern void __iomem *cm_base;
416extern void __iomem *cm2_base; 416extern void __iomem *cm2_base;
417extern void __iomem *prcm_mpu_base; 417extern void __iomem *prcm_mpu_base;
418 418
419#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5) 419#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
420extern void omap_prm_base_init(void); 420extern void omap_prm_base_init(void);
421extern void omap_cm_base_init(void); 421extern void omap_cm_base_init(void);
422#else 422#else
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 28cbfb2b5733..053e24ed3c48 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -160,7 +160,7 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
160 if (omap2_globals->prcm_mpu) 160 if (omap2_globals->prcm_mpu)
161 prcm_mpu_base = omap2_globals->prcm_mpu; 161 prcm_mpu_base = omap2_globals->prcm_mpu;
162 162
163 if (cpu_is_omap44xx()) { 163 if (cpu_is_omap44xx() || soc_is_omap54xx()) {
164 omap_prm_base_init(); 164 omap_prm_base_init();
165 omap_cm_base_init(); 165 omap_cm_base_init();
166 } 166 }
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 2b318ec92d39..13d20c8a283d 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -393,6 +393,11 @@ static void __init omap4_timer_init(void)
393OMAP_SYS_TIMER(4) 393OMAP_SYS_TIMER(4)
394#endif 394#endif
395 395
396#ifdef CONFIG_SOC_OMAP5
397OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
398OMAP_SYS_TIMER(5)
399#endif
400
396/** 401/**
397 * omap_timer_init - build and register timer device with an 402 * omap_timer_init - build and register timer device with an
398 * associated timer hwmod 403 * associated timer hwmod
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index ad95c7a5d009..dcfb506a592e 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -29,7 +29,7 @@ config ARCH_OMAP2PLUS
29 select USE_OF 29 select USE_OF
30 select PROC_DEVICETREE if PROC_FS 30 select PROC_DEVICETREE if PROC_FS
31 help 31 help
32 "Systems based on OMAP2, OMAP3 or OMAP4" 32 "Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
33 33
34endchoice 34endchoice
35 35
@@ -150,7 +150,7 @@ config OMAP_32K_TIMER
150 This timer saves power compared to the OMAP_MPU_TIMER, and has 150 This timer saves power compared to the OMAP_MPU_TIMER, and has
151 support for no tick during idle. The 32KHz timer provides less 151 support for no tick during idle. The 32KHz timer provides less
152 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is 152 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
153 currently only available for OMAP16XX, 24XX, 34XX and OMAP4. 153 currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5.
154 154
155config OMAP3_L2_AUX_SECURE_SAVE_RESTORE 155config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
156 bool "OMAP3 HS/EMU save and restore for L2 AUX control register" 156 bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 0a9b9a970113..89a3723b3538 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -77,3 +77,12 @@ void __init omap_init_consistent_dma_size(void)
77 init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20); 77 init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
78#endif 78#endif
79} 79}
80
81/*
82 * Stub function for OMAP2 so that common files
83 * continue to build when custom builds are used
84 */
85int __weak omap_secure_ram_reserve_memblock(void)
86{
87 return 0;
88}
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 2132c4f389e1..dbf1e03029a5 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -29,7 +29,10 @@
29#include <plat/clock.h> 29#include <plat/clock.h>
30 30
31/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ 31/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
32#define OMAP2_32KSYNCNT_CR_OFF 0x10 32#define OMAP2_32KSYNCNT_REV_OFF 0x0
33#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
34#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
35#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
33 36
34/* 37/*
35 * 32KHz clocksource ... always available, on pretty most chips except 38 * 32KHz clocksource ... always available, on pretty most chips except
@@ -84,9 +87,16 @@ int __init omap_init_clocksource_32k(void __iomem *vbase)
84 int ret; 87 int ret;
85 88
86 /* 89 /*
87 * 32k sync Counter register offset is at 0x10 90 * 32k sync Counter IP register offsets vary between the
91 * highlander version and the legacy ones.
92 * The 'SCHEME' bits(30-31) of the revision register is used
93 * to identify the version.
88 */ 94 */
89 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF; 95 if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
96 OMAP2_32KSYNCNT_REV_SCHEME)
97 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
98 else
99 sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
90 100
91 /* 101 /*
92 * 120000 rough estimate from the calculations in 102 * 120000 rough estimate from the calculations in
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 14f050f7a897..e2d911d16fb4 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -9,7 +9,7 @@
9 * 9 *
10 * Written by Tony Lindgren <tony.lindgren@nokia.com> 10 * Written by Tony Lindgren <tony.lindgren@nokia.com>
11 * 11 *
12 * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com> 12 * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
13 * 13 *
14 * This program is free software; you can redistribute it and/or modify 14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by 15 * it under the terms of the GNU General Public License as published by
@@ -70,6 +70,7 @@ unsigned int omap_rev(void);
70 * cpu_is_omap443x(): True for OMAP4430 70 * cpu_is_omap443x(): True for OMAP4430
71 * cpu_is_omap446x(): True for OMAP4460 71 * cpu_is_omap446x(): True for OMAP4460
72 * cpu_is_omap447x(): True for OMAP4470 72 * cpu_is_omap447x(): True for OMAP4470
73 * soc_is_omap543x(): True for OMAP5430, OMAP5432
73 */ 74 */
74#define GET_OMAP_CLASS (omap_rev() & 0xff) 75#define GET_OMAP_CLASS (omap_rev() & 0xff)
75 76
@@ -122,6 +123,7 @@ IS_OMAP_CLASS(24xx, 0x24)
122IS_OMAP_CLASS(34xx, 0x34) 123IS_OMAP_CLASS(34xx, 0x34)
123IS_OMAP_CLASS(44xx, 0x44) 124IS_OMAP_CLASS(44xx, 0x44)
124IS_AM_CLASS(35xx, 0x35) 125IS_AM_CLASS(35xx, 0x35)
126IS_OMAP_CLASS(54xx, 0x54)
125IS_AM_CLASS(33xx, 0x33) 127IS_AM_CLASS(33xx, 0x33)
126 128
127IS_TI_CLASS(81xx, 0x81) 129IS_TI_CLASS(81xx, 0x81)
@@ -133,6 +135,7 @@ IS_OMAP_SUBCLASS(363x, 0x363)
133IS_OMAP_SUBCLASS(443x, 0x443) 135IS_OMAP_SUBCLASS(443x, 0x443)
134IS_OMAP_SUBCLASS(446x, 0x446) 136IS_OMAP_SUBCLASS(446x, 0x446)
135IS_OMAP_SUBCLASS(447x, 0x447) 137IS_OMAP_SUBCLASS(447x, 0x447)
138IS_OMAP_SUBCLASS(543x, 0x543)
136 139
137IS_TI_SUBCLASS(816x, 0x816) 140IS_TI_SUBCLASS(816x, 0x816)
138IS_TI_SUBCLASS(814x, 0x814) 141IS_TI_SUBCLASS(814x, 0x814)
@@ -156,6 +159,8 @@ IS_AM_SUBCLASS(335x, 0x335)
156#define cpu_is_omap443x() 0 159#define cpu_is_omap443x() 0
157#define cpu_is_omap446x() 0 160#define cpu_is_omap446x() 0
158#define cpu_is_omap447x() 0 161#define cpu_is_omap447x() 0
162#define soc_is_omap54xx() 0
163#define soc_is_omap543x() 0
159 164
160#if defined(MULTI_OMAP1) 165#if defined(MULTI_OMAP1)
161# if defined(CONFIG_ARCH_OMAP730) 166# if defined(CONFIG_ARCH_OMAP730)
@@ -291,6 +296,7 @@ IS_OMAP_TYPE(3430, 0x3430)
291#define cpu_is_omap2430() 0 296#define cpu_is_omap2430() 0
292#define cpu_is_omap3430() 0 297#define cpu_is_omap3430() 0
293#define cpu_is_omap3630() 0 298#define cpu_is_omap3630() 0
299#define soc_is_omap5430() 0
294 300
295/* 301/*
296 * Whether we have MULTI_OMAP1 or not, we still need to distinguish 302 * Whether we have MULTI_OMAP1 or not, we still need to distinguish
@@ -371,11 +377,18 @@ IS_OMAP_TYPE(3430, 0x3430)
371# define cpu_is_omap447x() is_omap447x() 377# define cpu_is_omap447x() is_omap447x()
372# endif 378# endif
373 379
380# if defined(CONFIG_SOC_OMAP5)
381# undef soc_is_omap54xx
382# undef soc_is_omap543x
383# define soc_is_omap54xx() is_omap54xx()
384# define soc_is_omap543x() is_omap543x()
385#endif
386
374/* Macros to detect if we have OMAP1 or OMAP2 */ 387/* Macros to detect if we have OMAP1 or OMAP2 */
375#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ 388#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
376 cpu_is_omap16xx()) 389 cpu_is_omap16xx())
377#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \ 390#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
378 cpu_is_omap44xx()) 391 cpu_is_omap44xx() || soc_is_omap54xx())
379 392
380/* Various silicon revisions for omap2 */ 393/* Various silicon revisions for omap2 */
381#define OMAP242X_CLASS 0x24200024 394#define OMAP242X_CLASS 0x24200024
@@ -428,9 +441,14 @@ IS_OMAP_TYPE(3430, 0x3430)
428#define OMAP447X_CLASS 0x44700044 441#define OMAP447X_CLASS 0x44700044
429#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8)) 442#define OMAP4470_REV_ES1_0 (OMAP447X_CLASS | (0x10 << 8))
430 443
444#define OMAP54XX_CLASS 0x54000054
445#define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
446#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
447
431void omap2xxx_check_revision(void); 448void omap2xxx_check_revision(void);
432void omap3xxx_check_revision(void); 449void omap3xxx_check_revision(void);
433void omap4xxx_check_revision(void); 450void omap4xxx_check_revision(void);
451void omap5xxx_check_revision(void);
434void omap3xxx_check_features(void); 452void omap3xxx_check_features(void);
435void ti81xx_check_features(void); 453void ti81xx_check_features(void);
436void omap4xxx_check_features(void); 454void omap4xxx_check_features(void);
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e897978371c2..ddbde38e1e33 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -288,5 +288,6 @@
288#include <plat/omap44xx.h> 288#include <plat/omap44xx.h>
289#include <plat/ti81xx.h> 289#include <plat/ti81xx.h>
290#include <plat/am33xx.h> 290#include <plat/am33xx.h>
291#include <plat/omap54xx.h>
291 292
292#endif /* __ASM_ARCH_OMAP_HARDWARE_H */ 293#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index 999ffba2690c..045e320f1067 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -99,4 +99,13 @@
99# endif 99# endif
100#endif 100#endif
101 101
102#ifdef CONFIG_SOC_OMAP5
103# ifdef OMAP_NAME
104# undef MULTI_OMAP2
105# define MULTI_OMAP2
106# else
107# define OMAP_NAME omap5
108# endif
109#endif
110
102#endif /* __PLAT_OMAP_MULTI_H */ 111#endif /* __PLAT_OMAP_MULTI_H */
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
index 8c7994ce9869..0e4acd2d2deb 100644
--- a/arch/arm/plat-omap/include/plat/omap-secure.h
+++ b/arch/arm/plat-omap/include/plat/omap-secure.h
@@ -3,12 +3,7 @@
3 3
4#include <linux/types.h> 4#include <linux/types.h>
5 5
6#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
7extern int omap_secure_ram_reserve_memblock(void); 6extern int omap_secure_ram_reserve_memblock(void);
8#else
9static inline void omap_secure_ram_reserve_memblock(void)
10{ }
11#endif
12 7
13#ifdef CONFIG_OMAP4_ERRATA_I688 8#ifdef CONFIG_OMAP4_ERRATA_I688
14extern int omap_barrier_reserve_memblock(void); 9extern int omap_barrier_reserve_memblock(void);
diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/plat-omap/include/plat/omap54xx.h
new file mode 100644
index 000000000000..a2582bb3cab3
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap54xx.h
@@ -0,0 +1,32 @@
1/*:
2 * Address mappings and base address for OMAP5 interconnects
3 * and peripherals.
4 *
5 * Copyright (C) 2012 Texas Instruments
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Sricharan <r.sricharan@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#ifndef __ASM_SOC_OMAP54XX_H
14#define __ASM_SOC_OMAP54XX_H
15
16/*
17 * Please place only base defines here and put the rest in device
18 * specific headers.
19 */
20#define L4_54XX_BASE 0x4a000000
21#define L4_WK_54XX_BASE 0x4ae00000
22#define L4_PER_54XX_BASE 0x48000000
23#define L3_54XX_BASE 0x44000000
24#define OMAP54XX_32KSYNCT_BASE 0x4ae04000
25#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
26#define OMAP54XX_CM_CORE_BASE 0x4a008000
27#define OMAP54XX_PRM_BASE 0x4ae06000
28#define OMAP54XX_PRCM_MPU_BASE 0x48243000
29#define OMAP54XX_SCM_BASE 0x4a002000
30#define OMAP54XX_CTRL_BASE 0x4a002800
31
32#endif /* __ASM_SOC_OMAP555554XX_H */
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 28e2d250c2fd..65fce44dce34 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -63,6 +63,14 @@
63/* AM33XX serial port */ 63/* AM33XX serial port */
64#define AM33XX_UART1_BASE 0x44E09000 64#define AM33XX_UART1_BASE 0x44E09000
65 65
66/* OMAP5 serial ports */
67#define OMAP5_UART1_BASE OMAP2_UART1_BASE
68#define OMAP5_UART2_BASE OMAP2_UART2_BASE
69#define OMAP5_UART3_BASE OMAP4_UART3_BASE
70#define OMAP5_UART4_BASE OMAP4_UART4_BASE
71#define OMAP5_UART5_BASE 0x48066000
72#define OMAP5_UART6_BASE 0x48068000
73
66/* External port on Zoom2/3 */ 74/* External port on Zoom2/3 */
67#define ZOOM_UART_BASE 0x10000000 75#define ZOOM_UART_BASE 0x10000000
68#define ZOOM_UART_VIRT 0xfa400000 76#define ZOOM_UART_VIRT 0xfa400000
@@ -97,6 +105,8 @@
97#define TI81XXUART2 82 105#define TI81XXUART2 82
98#define TI81XXUART3 83 106#define TI81XXUART3 83
99#define AM33XXUART1 84 107#define AM33XXUART1 84
108#define OMAP5UART3 OMAP4UART3
109#define OMAP5UART4 OMAP4UART4
100#define ZOOM_UART 95 /* Only on zoom2/3 */ 110#define ZOOM_UART 95 /* Only on zoom2/3 */
101 111
102/* This is only used by 8250.c for omap1510 */ 112/* This is only used by 8250.c for omap1510 */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index ac4323390213..b8d19a136781 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -95,6 +95,9 @@ static inline void flush(void)
95 _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \ 95 _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT, \
96 OMAP4UART##p) 96 OMAP4UART##p)
97 97
98#define DEBUG_LL_OMAP5(p, mach) \
99 _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT, \
100 OMAP5UART##p)
98/* Zoom2/3 shift is different for UART1 and external port */ 101/* Zoom2/3 shift is different for UART1 and external port */
99#define DEBUG_LL_ZOOM(mach) \ 102#define DEBUG_LL_ZOOM(mach) \
100 _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) 103 _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
@@ -177,6 +180,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
177 DEBUG_LL_OMAP4(3, omap_4430sdp); 180 DEBUG_LL_OMAP4(3, omap_4430sdp);
178 DEBUG_LL_OMAP4(3, omap4_panda); 181 DEBUG_LL_OMAP4(3, omap4_panda);
179 182
183 /* omap5 based boards using UART3 */
184 DEBUG_LL_OMAP5(3, omap5_sevm);
185
180 /* zoom2/3 external uart */ 186 /* zoom2/3 external uart */
181 DEBUG_LL_ZOOM(omap_zoom2); 187 DEBUG_LL_ZOOM(omap_zoom2);
182 DEBUG_LL_ZOOM(omap_zoom3); 188 DEBUG_LL_ZOOM(omap_zoom3);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 70cf825bdd87..766181cb5c95 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -6,8 +6,8 @@
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com> 7 * Written by Tony Lindgren <tony@atomide.com>
8 * 8 *
9 * Copyright (C) 2009 Texas Instruments 9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as 13 * it under the terms of the GNU General Public License version 2 as
@@ -44,6 +44,7 @@
44#else 44#else
45#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) 45#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
46#endif 46#endif
47#define OMAP5_SRAM_PA 0x40300000
47 48
48#if defined(CONFIG_ARCH_OMAP2PLUS) 49#if defined(CONFIG_ARCH_OMAP2PLUS)
49#define SRAM_BOOTLOADER_SZ 0x00 50#define SRAM_BOOTLOADER_SZ 0x00
@@ -118,6 +119,9 @@ static void __init omap_detect_sram(void)
118 } else if (cpu_is_omap44xx()) { 119 } else if (cpu_is_omap44xx()) {
119 omap_sram_start = OMAP4_SRAM_PUB_PA; 120 omap_sram_start = OMAP4_SRAM_PUB_PA;
120 omap_sram_size = 0xa000; /* 40K */ 121 omap_sram_size = 0xa000; /* 40K */
122 } else if (soc_is_omap54xx()) {
123 omap_sram_start = OMAP5_SRAM_PA;
124 omap_sram_size = SZ_128K; /* 128KB */
121 } else { 125 } else {
122 omap_sram_start = OMAP2_SRAM_PUB_PA; 126 omap_sram_start = OMAP2_SRAM_PUB_PA;
123 omap_sram_size = 0x800; /* 2K */ 127 omap_sram_size = 0x800; /* 2K */
@@ -132,6 +136,9 @@ static void __init omap_detect_sram(void)
132 } else if (cpu_is_omap44xx()) { 136 } else if (cpu_is_omap44xx()) {
133 omap_sram_start = OMAP4_SRAM_PA; 137 omap_sram_start = OMAP4_SRAM_PA;
134 omap_sram_size = 0xe000; /* 56K */ 138 omap_sram_size = 0xe000; /* 56K */
139 } else if (soc_is_omap54xx()) {
140 omap_sram_start = OMAP5_SRAM_PA;
141 omap_sram_size = SZ_128K; /* 128KB */
135 } else { 142 } else {
136 omap_sram_start = OMAP2_SRAM_PA; 143 omap_sram_start = OMAP2_SRAM_PA;
137 if (cpu_is_omap242x()) 144 if (cpu_is_omap242x())
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 18:21:15 -0400