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* Merge tag 'clk-for-linus-3.16-part2' of ↵Linus Torvalds2014-06-15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull more clock framework updates from Mike Turquette: "This contains the second half the of the clk changes for 3.16. They are simply fixes and code refactoring for the OMAP clock drivers. The sunxi clock driver changes include splitting out the one mega-driver into several smaller pieces and adding support for the A31 SoC clocks" * tag 'clk-for-linus-3.16-part2' of git://git.linaro.org/people/mike.turquette/linux: (25 commits) clk: sunxi: document PRCM clock compatible strings clk: sunxi: add PRCM (Power/Reset/Clock Management) clks support clk: sun6i: Protect SDRAM gating bit clk: sun6i: Protect CPU clock clk: sunxi: Rework clock protection code clk: sunxi: Move the GMAC clock to a file of its own clk: sunxi: Move the 24M oscillator to a file of its own clk: sunxi: Remove calls to clk_put clk: sunxi: document new A31 USB clock compatible clk: sunxi: Implement A31 USB clock ARM: dts: OMAP5/DRA7: use omap5-mpu-dpll-clock capable of dealing with higher frequencies CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher frequencies ARM: OMAP5+: dpll: support Duty Cycle Correction(DCC) CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic) dt:/bindings: DRA7 ATL (Audio Tracking Logic) clock bindings ARM: dts: dra7xx-clocks: Correct name for atl clkin3 clock CLK: TI: gate: add composite interface clock to OMAP2 only build ARM: OMAP2: clock: add DT boot support for cpufreq_ck CLK: TI: OMAP2: add clock init support ...
| * Merge tag 'sunxi-clk-for-3.16-2' of https://github.com/mripard/linux into ↵Mike Turquette2014-06-11
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next Rebase of Emilio's clk-sunxi-for-3.16 on top of clk-next Fixed a few compilation warnings exposed by a patch introduced during the 3.16 merge window. Original tag message: Allwinner sunXi SoCs clock changes This pull contains some new code to add support for A31 clocks by Maxime and Boris. It also reworks the driver a bit to avoid having a huge single file when we have a full folder for ourselves, and separating different functional units makes sense.
| | * clk: sunxi: document PRCM clock compatible stringsBoris BREZILLON2014-06-11
| | | | | | | | | | | | | | | | | | | | | | | | Document new compatible strings for clock provided by the PRCM (Power/Reset/Clock Management) unit. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| | * clk: sunxi: add PRCM (Power/Reset/Clock Management) clks supportBoris BREZILLON2014-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PRCM (Power/Reset/Clock Management) unit provides several clock devices: - AR100 clk: used to clock the Power Management co-processor - AHB0 clk: used to clock the AHB0 bus - APB0 clk and gates: used to clk peripherals connected to the APB0 bus Add support for these clks in a separate driver so that they can be probed as platform devices instead of registered during early init. This is needed to be able to probe PRCM MFD subdevices. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| | * clk: sun6i: Protect SDRAM gating bitMaxime Ripard2014-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Prevent the SDRAM controller from being gated by force-enabling it in the machine code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| | * clk: sun6i: Protect CPU clockMaxime Ripard2014-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Right now, AHB is an indirect child clock of the CPU clock. If that happens to change, since the CPU clock has no other consumers declared in Linux, it would be shut down, which is not really a good idea. Prevent this by forcing it enabled. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| | * clk: sunxi: Rework clock protection codeMaxime Ripard2014-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we start to have a lot of clocks to protect, some of them in a few SoCs only, it becomes difficult to handle the clock protection without having to add per machine exceptions. Add per-SoC data to tell which clock to leave enabled. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| | * clk: sunxi: Move the GMAC clock to a file of its ownMaxime Ripard2014-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we have a folder of our own, we can actually make use of it by splitting the huge clock file into several sub drivers. The gmac clock is pretty easy to deal with, since it's pretty much isolated and doesn't have any dependency on the other clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| | * clk: sunxi: Move the 24M oscillator to a file of its ownMaxime Ripard2014-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we have a folder of our own, we can actually make use of it by splitting the huge clock file into several sub drivers. The main oscillator is pretty easy to deal with, since it's pretty much isolated. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| | * clk: sunxi: Remove calls to clk_putMaxime Ripard2014-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Callers of clk_put must disable the clock first. This also means that as long as the clock is enabled the driver should hold a reference to that clock. Hence, the call to clk_put here are bogus and should be removed. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| | * clk: sunxi: document new A31 USB clock compatibleEmilio López2014-06-11
| | | | | | | | | | | | | | | | | | | | | Support for the USB gates and resets on A31 has been recently added using a new compatible, so let's document it here. Signed-off-by: Emilio López <emilio@elopez.com.ar>
| | * clk: sunxi: Implement A31 USB clockMaxime Ripard2014-06-11
| |/ | | | | | | | | | | | | | | | | | | | | The A31 USB clock slightly differ from its older counterparts, mostly because it has a different gate for each PHY, while the older one had a single gate for all the phy. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
| * Merge branch 'for-v3.16/ti-clk-drv' of github.com:t-kristo/linux-pm into ↵Mike Turquette2014-06-10
| |\ | | | | | | | | | clk-next
| | * ARM: dts: OMAP5/DRA7: use omap5-mpu-dpll-clock capable of dealing with ↵Nishanth Menon2014-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | higher frequencies OMAP5432, DRA75x and DRA72x have MPU DPLLs that need Duty Cycle Correction(DCC) to operate safely at frequencies >= 1.4GHz. Switch to "ti,omap5-mpu-dpll-clock" compatible property which provides this support. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher ↵Nishanth Menon2014-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | frequencies MPU DPLL on OMAP5, DRA75x, DRA72x has a limitation on the maximum frequency it can be locked at. Duty Cycle Correction circuit is used to recover a correct duty cycle for achieving higher frequencies (hardware internally switches output to M3 output(CLKOUTHIF) from M2 output (CLKOUT)). So provide support to setup required data to handle Duty cycle by the setting up the minimum frequency for DPLL. 1.4GHz is common for all these devices and is based on Technical Reference Manual information for OMAP5432((SWPU282U) chapter 3.6.3.3.1 "DPLLs Output Clocks Parameters", and equivalent information from DRA75x, DRA72x documentation(SPRUHP2E, SPRUHI2P). Signed-off-by: Nishanth Menon <nm@ti.com> [t-kristo@ti.com: updated for latest dpll init API call] Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * ARM: OMAP5+: dpll: support Duty Cycle Correction(DCC)Andrii Tseglytskyi2014-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Duty Cycle Correction(DCC) needs to be enabled if the MPU is to run at frequencies beyond 1.4GHz for OMAP5, DRA75x, DRA72x. MPU DPLL has a limitation on the maximum frequency it can be locked at. Duty Cycle Correction circuit is used to recover a correct duty cycle for achieving higher frequencies (hardware internally switches output to M3 output(CLKOUTHIF) from M2 output (CLKOUT)). For further information, See the note on OMAP5432 Technical Reference Manual(SWPU282U) chapter 3.6.3.3.1 "DPLLs Output Clocks Parameters", and also the "OMAP543x ES2.0 DM Operating Conditions Addendum v0.5" chapter 2.1 "Micro Processor Unit (MPU)". Equivalent information is present in relevant DRA75x, 72x documentation(SPRUHP2E, SPRUHI2P). Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> Signed-off-by: Taras Kondratiuk <taras@ti.com> Signed-off-by: J Keerthy <j-keerthy@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> [t-kristo@ti.com: added TRM / DM references for DCC clock rate] Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ckPeter Ujfalusi2014-06-06
| | | | | | | | | | | | | | | | | | | | | | | | In order to get correct clock dividers for AESS/ABE we need to set the dpll_abe_m2x2_ck rate to be double of dpll_abe_ck. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)Peter Ujfalusi2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Audio Tracking Logic is designed to be used by HD Radio applications to synchronize the audio output clocks to the baseband clock. ATL can be also used to track errors between two reference clocks (BWS, AWS) and generate a modulated clock output which averages to some desired frequency. In essence ATL is generating a clock to be used by an audio codec and also to be used by the SoC as MCLK. To be able to integrate the ATL provided clocks to the clock tree we need two types of DT binding: - DT clock nodes to represent the ATL clocks towards the CCF - binding for the ATL IP itself which is going to handle the hw configuration The reason for this type of setup is that ATL itself is a separate device in the SoC, it has it's own address space and clock domain. Other IPs can use the ATL generated clock as their functional clock (McASPs for example) and external components like audio codecs can also use the very same clock as their MCLK. The ATL IP in DRA7 contains 4 ATL instences. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * dt:/bindings: DRA7 ATL (Audio Tracking Logic) clock bindingsPeter Ujfalusi2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Audio Tracking Logic is designed to be used by HD Radio applications to synchronize the audio output clocks to the baseband clock. ATL can be also used to track errors between two reference clocks (BWS, AWS) and generate a modulated clock output which averages to some desired frequency. In essence ATL is generating a clock to be used by an audio codec and also to be used by the SoC as MCLK. To be able to integrate the ATL provided clocks to the clock tree we need two types of DT binding: - DT clock nodes to represent the ATL clocks towards the CCF - binding for the ATL IP itself which is going to handle the hw configuration The reason for this type of setup is that ATL itself is a separate device in the SoC, it has it's own address space and clock domain. Other IPs can use the ATL generated clock as their functional clock (McASPs for example) and external components like audio codecs can also use the very same clock as their MCLK. The ATL IP in DRA7 contains 4 ATL instences. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * ARM: dts: dra7xx-clocks: Correct name for atl clkin3 clockPeter Ujfalusi2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | To allign the name with the other atl clock names: atlclkin3_ck -> atl_clkin3_ck Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * CLK: TI: gate: add composite interface clock to OMAP2 only buildTero Kristo2014-05-28
| | | | | | | | | | | | | | | | | | | | | Composite interface clock is needed by OMAP2, but it was only built in for OMAP3. Fixed the conditional build flag checks for this. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * ARM: OMAP2: clock: add DT boot support for cpufreq_ckTero Kristo2014-05-28
| | | | | | | | | | | | | | | | | | The clock and clkdev for this are added manually. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * CLK: TI: OMAP2: add clock init supportTero Kristo2014-05-28
| | | | | | | | | | | | | | | | | | | | | Adds support for registering the alias clocks, boot time clock-enable list and disabling autoidle of clocks. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * CLK: TI: interface: add support for omap2430 specific interface clockTero Kristo2014-05-28
| | | | | | | | | | | | | | | | | | | | | OMAP2430 I2CHS modules require specific hardware ops to be used, so added a new compatible string for this. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * CLK: TI: gate: fixed DT binding documentation bugsTero Kristo2014-05-28
| | | | | | | | | | | | | | | | | | | | | ti,composite-gate-clock documentation was missing, also the register offset examples were wrong. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * CLK: TI: APLL: add support for omap2 apllsTero Kristo2014-05-28
| | | | | | | | | | | | | | | | | | | | | This patch adds support for omap2 type aplls, which have gating and autoidle functionality. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * CLK: TI: DPLL: add support for omap2 core dpllTero Kristo2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | OMAP2 has slightly different DPLL compared to later OMAP generations. This patch adds support for the ti,omap2-dpll-core-clock and also adds the bindings documentation. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| | * CLK: TI: DPLL: simplify autoidle register detection logicTero Kristo2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | AMxxxx dpll_data previously had autoidle_mask set, even if these SoC:s don't have autoidle register. Remove the bit-field value as it is unused, also drop the unnecessary DPLL_HAS_AUTOIDLE flag passing during init, as we can just simply check against the contents of the autoidle_mask. Signed-off-by: Tero Kristo <t-kristo@ti.com>
* | | Merge git://git.infradead.org/users/willy/linux-nvmeLinus Torvalds2014-06-15
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull NVMe update from Matthew Wilcox: "Mostly bugfixes again for the NVMe driver. I'd like to call out the exported tracepoint in the block layer; I believe Keith has cleared this with Jens. We've had a few reports from people who're really pounding on NVMe devices at scale, hence the timeout changes (and new module parameters), hotplug cpu deadlock, tracepoints, and minor performance tweaks" [ Jens hadn't seen that tracepoint thing, but is ok with it - it will end up going away when mq conversion happens ] * git://git.infradead.org/users/willy/linux-nvme: (22 commits) NVMe: Fix START_STOP_UNIT Scsi->NVMe translation. NVMe: Use Log Page constants in SCSI emulation NVMe: Define Log Page constants NVMe: Fix hot cpu notification dead lock NVMe: Rename io_timeout to nvme_io_timeout NVMe: Use last bytes of f/w rev SCSI Inquiry NVMe: Adhere to request queue block accounting enable/disable NVMe: Fix nvme get/put queue semantics NVMe: Delete NVME_GET_FEAT_TEMP_THRESH NVMe: Make admin timeout a module parameter NVMe: Make iod bio timeout a parameter NVMe: Prevent possible NULL pointer dereference NVMe: Fix the buffer size passed in GetLogPage(CDW10.NUMD) NVMe: Update data structures for NVMe 1.2 NVMe: Enable BUILD_BUG_ON checks NVMe: Update namespace and controller identify structures to the 1.1a spec NVMe: Flush with data support NVMe: Configure support for block flush NVMe: Add tracepoints NVMe: Protect against badly formatted CQEs ...
| * | | NVMe: Fix START_STOP_UNIT Scsi->NVMe translation.Dan McLeran2014-06-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains several fixes for Scsi START_STOP_UNIT. The previous code did not account for signed vs. unsigned arithmetic which resulted in an invalid lowest power state caculation when the device only supports 1 power state. The code for Power Condition == 2 (Idle) was not following the spec. The spec calls for setting the device to specific power states, depending upon Power Condition Modifier, without accounting for the number of power states supported by the device. The code for Power Condition == 3 (Standby) was using a hard-coded '0' which is replaced with the macro POWER_STATE_0. Signed-off-by: Dan McLeran <daniel.mcleran@intel.com> Reviewed-by: Vishal Verma <vishal.l.verma@linux.intel.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Use Log Page constants in SCSI emulationMatthew Wilcox2014-06-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The nvme-scsi file defined its own Log Page constant. Use the newly-defined one from the header file instead. Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Define Log Page constantsMatthew Wilcox2014-06-13
| | | | | | | | | | | | | | | | | | | | | | | | Taken from the 1.1a version of the spec Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Fix hot cpu notification dead lockKeith Busch2014-06-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a potential dead lock if a cpu event occurs during nvme probe since it registered with hot cpu notification. This fixes the race by having the module register with notification outside of probe rather than have each device register. The actual work is done in a scheduled work queue instead of in the notifier since assigning IO queues has the potential to block if the driver creates additional queues. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Rename io_timeout to nvme_io_timeoutMatthew Wilcox2014-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It's positively immoral to have a global variable called 'io_timeout'. Keep the module parameter called io_timeout, though. Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Use last bytes of f/w rev SCSI InquiryKeith Busch2014-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After skipping right-padded spaces, use the last four bytes of the firmware revision when reporting the Inquiry Product Revision. These are generally more indicative to what is running. Signed-off-by: Keith Busch <keith.busch@intel.com> Acked-by: Vishal Verma <vishal.l.verma@linux.intel.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Adhere to request queue block accounting enable/disableSam Bradshaw2014-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently, a new sysfs control "iostats" was added to selectively enable or disable io statistics collection for request queues. This patch hooks that control. IO statistics collection is rather expensive on large, multi-node machines with drives pushing millions of iops. Having the ability to disable collection if not needed can improve throughput significantly. As a data point, on a quad E5-4640, I see more than 50% throughput improvement when io statistics accounting is disabled during heavily multi-threaded small block random read benchmarks where device performance is in the million iops+ range. Signed-off-by: Sam Bradshaw <sbradshaw@micron.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Fix nvme get/put queue semanticsKeith Busch2014-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The routines to get and lock nvme queues required the caller to "put" or "unlock" them even if getting one returned NULL. This patch fixes that. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Delete NVME_GET_FEAT_TEMP_THRESHMatthew Wilcox2014-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This define isn't used, and any code that wanted to use it should use NVME_FEAT_TEMP_THRESH instead. Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Make admin timeout a module parameterKeith Busch2014-06-03
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Keith Busch <keith.busch@intel.com> [made admin_timeout static] Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Make iod bio timeout a parameterKeith Busch2014-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was originally set to 4 times the IO timeout, but that was when the IO timeout was 5 seconds instead of 30. 20 seconds for total time to failure seemed more reasonable than 2 minutes for most, but other users have requested to make this a module parameter instead. Signed-off-by: Keith Busch <keith.busch@intel.com> [renamed the module parameter to retry_time] [made retry_time static] Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Prevent possible NULL pointer dereferenceSantosh Y2014-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kmalloc() used by the nvme_alloc_iod() to allocate memory for 'iod' can fail. So check the return value. Signed-off-by: Santosh Y <santosh.sy@samsung.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Fix the buffer size passed in GetLogPage(CDW10.NUMD)Indraneel Mukherjee2014-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In GetLogPage the buffer size passed to device is a 0's based value. Signed-off-by: Indraneel M <indraneel.m@samsung.com> Reported-by: Shiro Itou <shiro.itou@outlook.com> Reviewed-by: Vishal Verma <vishal.l.verma@linux.intel.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Update data structures for NVMe 1.2Matthew Wilcox2014-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Include changes from the current set of ratified Technical Proposals for NVMe 1.2. Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Enable BUILD_BUG_ON checksMatthew Wilcox2014-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since _nvme_check_size() wasn't being called from anywhere, the compiler was optimising it away ... along with all the link-time build failures that would result if any of the structures were the wrong size. Call it from nvme_exit() for no particular reason. Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Update namespace and controller identify structures to the 1.1a specDimitri John Ledkov2014-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Controller: add CNTLID, AVSCC, APSTA, NVSCC, ACWU, SGLS fields. Namespace: add NMIC, RESCAP, EUI64 fields. EUI64 is specifically interesting, since it can be used to construct an UEFI NVMe device path for a boot entry. As per NVM Express 1.1a spec: http://www.nvmexpress.org/wp-content/uploads/NVM-Express-1_1a.pdf Signed-off-by: Dimitri John Ledkov <dimitri.ledkov@canonical.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Flush with data supportKeith Busch2014-05-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is possible a filesystem may send a flush flagged bio with write data. There is no such composite NVMe command, so the driver sends flush and write separately. The device is allowed to execute these commands in any order, so it was possible the driver ends the bio after the write completes, but while the flush is still active. We don't want to let a filesystem believe flush succeeded before it really has; this could cause data corruption on a power loss between these events. To fix, this patch splits the flush and write into chained bios. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Configure support for block flushKeith Busch2014-05-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This configures an nvme request_queue as flush capable if the device has a volatile write cache present. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Add tracepointsKeith Busch2014-05-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding tracepoints for bio_complete and block_split into nvme to help with gathering IO info using blktrace and blkparse. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Protect against badly formatted CQEsKeith Busch2014-05-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a misbehaving device posts a CQE with a command id < depth but for one that was never allocated, the command info will have a callback function set to NULL and we don't want to try invoking that. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
| * | | NVMe: Improve error messagesMatthew Wilcox2014-05-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Help people diagnose what is going wrong at initialisation time by printing out which command has gone wrong and what the device returned. Also fix the error message printed while waiting for reset. Signed-off-by: Matthew Wilcox <matthew.r.wilcox@intel.com> Reviewed-by: Keith Busch <keith.busch@intel.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-15 04:18:07 -0400