diff options
| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | 2014-05-07 06:20:45 -0400 |
|---|---|---|
| committer | Tero Kristo <t-kristo@ti.com> | 2014-05-28 06:06:50 -0400 |
| commit | 0cccd9190009aa6c037aa88a85f2a1b72a6a7963 (patch) | |
| tree | d731b24917b2438be1815c98fce58ddc20919de8 | |
| parent | b3654d703de2ddf5651d2fa959879d586e685376 (diff) | |
ARM: dts: dra7xx-clocks: Correct name for atl clkin3 clock
To allign the name with the other atl clock names:
atlclkin3_ck -> atl_clkin3_ck
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
| -rw-r--r-- | arch/arm/boot/dts/dra7xx-clocks.dtsi | 22 | ||||
| -rw-r--r-- | drivers/clk/ti/clk-7xx.c | 2 |
2 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index cfb8fc753f50..30160348934c 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | clock-frequency = <0>; | 26 | clock-frequency = <0>; |
| 27 | }; | 27 | }; |
| 28 | 28 | ||
| 29 | atlclkin3_ck: atlclkin3_ck { | 29 | atl_clkin3_ck: atl_clkin3_ck { |
| 30 | #clock-cells = <0>; | 30 | #clock-cells = <0>; |
| 31 | compatible = "fixed-clock"; | 31 | compatible = "fixed-clock"; |
| 32 | clock-frequency = <0>; | 32 | clock-frequency = <0>; |
| @@ -730,7 +730,7 @@ | |||
| 730 | mcasp1_ahclkr_mux: mcasp1_ahclkr_mux { | 730 | mcasp1_ahclkr_mux: mcasp1_ahclkr_mux { |
| 731 | #clock-cells = <0>; | 731 | #clock-cells = <0>; |
| 732 | compatible = "ti,mux-clock"; | 732 | compatible = "ti,mux-clock"; |
| 733 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 733 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 734 | ti,bit-shift = <28>; | 734 | ti,bit-shift = <28>; |
| 735 | reg = <0x0550>; | 735 | reg = <0x0550>; |
| 736 | }; | 736 | }; |
| @@ -738,7 +738,7 @@ | |||
| 738 | mcasp1_ahclkx_mux: mcasp1_ahclkx_mux { | 738 | mcasp1_ahclkx_mux: mcasp1_ahclkx_mux { |
| 739 | #clock-cells = <0>; | 739 | #clock-cells = <0>; |
| 740 | compatible = "ti,mux-clock"; | 740 | compatible = "ti,mux-clock"; |
| 741 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 741 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 742 | ti,bit-shift = <24>; | 742 | ti,bit-shift = <24>; |
| 743 | reg = <0x0550>; | 743 | reg = <0x0550>; |
| 744 | }; | 744 | }; |
| @@ -1631,7 +1631,7 @@ | |||
| 1631 | mcasp2_ahclkr_mux: mcasp2_ahclkr_mux { | 1631 | mcasp2_ahclkr_mux: mcasp2_ahclkr_mux { |
| 1632 | #clock-cells = <0>; | 1632 | #clock-cells = <0>; |
| 1633 | compatible = "ti,mux-clock"; | 1633 | compatible = "ti,mux-clock"; |
| 1634 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1634 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1635 | ti,bit-shift = <28>; | 1635 | ti,bit-shift = <28>; |
| 1636 | reg = <0x1860>; | 1636 | reg = <0x1860>; |
| 1637 | }; | 1637 | }; |
| @@ -1639,7 +1639,7 @@ | |||
| 1639 | mcasp2_ahclkx_mux: mcasp2_ahclkx_mux { | 1639 | mcasp2_ahclkx_mux: mcasp2_ahclkx_mux { |
| 1640 | #clock-cells = <0>; | 1640 | #clock-cells = <0>; |
| 1641 | compatible = "ti,mux-clock"; | 1641 | compatible = "ti,mux-clock"; |
| 1642 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1642 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1643 | ti,bit-shift = <24>; | 1643 | ti,bit-shift = <24>; |
| 1644 | reg = <0x1860>; | 1644 | reg = <0x1860>; |
| 1645 | }; | 1645 | }; |
| @@ -1655,7 +1655,7 @@ | |||
| 1655 | mcasp3_ahclkx_mux: mcasp3_ahclkx_mux { | 1655 | mcasp3_ahclkx_mux: mcasp3_ahclkx_mux { |
| 1656 | #clock-cells = <0>; | 1656 | #clock-cells = <0>; |
| 1657 | compatible = "ti,mux-clock"; | 1657 | compatible = "ti,mux-clock"; |
| 1658 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1658 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1659 | ti,bit-shift = <24>; | 1659 | ti,bit-shift = <24>; |
| 1660 | reg = <0x1868>; | 1660 | reg = <0x1868>; |
| 1661 | }; | 1661 | }; |
| @@ -1671,7 +1671,7 @@ | |||
| 1671 | mcasp4_ahclkx_mux: mcasp4_ahclkx_mux { | 1671 | mcasp4_ahclkx_mux: mcasp4_ahclkx_mux { |
| 1672 | #clock-cells = <0>; | 1672 | #clock-cells = <0>; |
| 1673 | compatible = "ti,mux-clock"; | 1673 | compatible = "ti,mux-clock"; |
| 1674 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1674 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1675 | ti,bit-shift = <24>; | 1675 | ti,bit-shift = <24>; |
| 1676 | reg = <0x1898>; | 1676 | reg = <0x1898>; |
| 1677 | }; | 1677 | }; |
| @@ -1687,7 +1687,7 @@ | |||
| 1687 | mcasp5_ahclkx_mux: mcasp5_ahclkx_mux { | 1687 | mcasp5_ahclkx_mux: mcasp5_ahclkx_mux { |
| 1688 | #clock-cells = <0>; | 1688 | #clock-cells = <0>; |
| 1689 | compatible = "ti,mux-clock"; | 1689 | compatible = "ti,mux-clock"; |
| 1690 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1690 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1691 | ti,bit-shift = <24>; | 1691 | ti,bit-shift = <24>; |
| 1692 | reg = <0x1878>; | 1692 | reg = <0x1878>; |
| 1693 | }; | 1693 | }; |
| @@ -1703,7 +1703,7 @@ | |||
| 1703 | mcasp6_ahclkx_mux: mcasp6_ahclkx_mux { | 1703 | mcasp6_ahclkx_mux: mcasp6_ahclkx_mux { |
| 1704 | #clock-cells = <0>; | 1704 | #clock-cells = <0>; |
| 1705 | compatible = "ti,mux-clock"; | 1705 | compatible = "ti,mux-clock"; |
| 1706 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1706 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1707 | ti,bit-shift = <24>; | 1707 | ti,bit-shift = <24>; |
| 1708 | reg = <0x1904>; | 1708 | reg = <0x1904>; |
| 1709 | }; | 1709 | }; |
| @@ -1719,7 +1719,7 @@ | |||
| 1719 | mcasp7_ahclkx_mux: mcasp7_ahclkx_mux { | 1719 | mcasp7_ahclkx_mux: mcasp7_ahclkx_mux { |
| 1720 | #clock-cells = <0>; | 1720 | #clock-cells = <0>; |
| 1721 | compatible = "ti,mux-clock"; | 1721 | compatible = "ti,mux-clock"; |
| 1722 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1722 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1723 | ti,bit-shift = <24>; | 1723 | ti,bit-shift = <24>; |
| 1724 | reg = <0x1908>; | 1724 | reg = <0x1908>; |
| 1725 | }; | 1725 | }; |
| @@ -1735,7 +1735,7 @@ | |||
| 1735 | mcasp8_ahclk_mux: mcasp8_ahclk_mux { | 1735 | mcasp8_ahclk_mux: mcasp8_ahclk_mux { |
| 1736 | #clock-cells = <0>; | 1736 | #clock-cells = <0>; |
| 1737 | compatible = "ti,mux-clock"; | 1737 | compatible = "ti,mux-clock"; |
| 1738 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; | 1738 | clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; |
| 1739 | ti,bit-shift = <22>; | 1739 | ti,bit-shift = <22>; |
| 1740 | reg = <0x1890>; | 1740 | reg = <0x1890>; |
| 1741 | }; | 1741 | }; |
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index f7e40734c819..e1581335937d 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c | |||
| @@ -24,7 +24,7 @@ static struct ti_dt_clk dra7xx_clks[] = { | |||
| 24 | DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"), | 24 | DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"), |
| 25 | DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"), | 25 | DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"), |
| 26 | DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"), | 26 | DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"), |
| 27 | DT_CLK(NULL, "atlclkin3_ck", "atlclkin3_ck"), | 27 | DT_CLK(NULL, "atl_clkin3_ck", "atl_clkin3_ck"), |
| 28 | DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"), | 28 | DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"), |
| 29 | DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"), | 29 | DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"), |
| 30 | DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"), | 30 | DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"), |