aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAge
* Merge tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2012-07-23
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull arm-soc power management changes from Arnd Bergmann: "These are various power management related changes, mainly concerning cpuidle on i.MX and OMAP, as well as a the move of the omap smartreflex driver to live in the power subsystem." Fix up conflicts in arch/arm/mach-{imx/mach-imx6q.c,omap2/prm2xxx_3xxx.h} * tag 'pm' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits) ARM: OMAP2+: PM: fix IRQ_NOAUTOEN removal by mis-merge ARM: OMAP2+: do not allow SmartReflex to be built as a module ARM: OMAP2: Use hwmod to initialize mmc for 2420 ARM: OMAP3: PM: cpuidle: optimize the clkdm idle latency in C1 state ARM: OMAP3: PM: cpuidle: optimize the PER latency in C1 state ARM: OMAP3: PM: cpuidle: default to C1 in next_valid_state ARM: OMAP3: PM: cleanup cam_pwrdm leftovers ARM: OMAP3: PM: call pre/post transition per powerdomain ARM: OMAP2+: powerdomain: allow pre/post transtion to be per pwrdm ARM: OMAP3: PM: Remove IO Daisychain control from cpuidle ARM: OMAP3PLUS: hwmod: reconfigure IO Daisychain during hwmod mux ARM: OMAP3+: PRM: Enable IO wake up ARM: OMAP4: PRM: Add IO Daisychain support ARM: OMAP3: PM: Move IO Daisychain function to omap3 prm file ARM: OMAP3: PM: correct enable/disable of daisy io chain ARM: OMAP2+: PRM: fix compile for OMAP4-only build W1: OMAP HDQ1W: use runtime PM ARM: OMAP2+: HDQ1W: use omap_device W1: OMAP HDQ1W: use 32-bit register accesses W1: OMAP HDQ1W: allow driver to be built on all OMAP2+ ...
| * Merge tag 'omap-devel-pm-for-v3.6' of ↵Arnd Bergmann2012-07-03
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/pm From: Tony Lindgren <tony@atomide.com>: Here are some omap PM changes that reimplement omap PRCM I/O chain code for wake-ups, and improve idle latencies for cpuidle. * tag 'omap-devel-pm-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: PM: fix IRQ_NOAUTOEN removal by mis-merge ARM: OMAP3: PM: cpuidle: optimize the clkdm idle latency in C1 state ARM: OMAP3: PM: cpuidle: optimize the PER latency in C1 state ARM: OMAP3: PM: cpuidle: default to C1 in next_valid_state ARM: OMAP3: PM: cleanup cam_pwrdm leftovers ARM: OMAP3: PM: call pre/post transition per powerdomain ARM: OMAP2+: powerdomain: allow pre/post transtion to be per pwrdm ARM: OMAP3: PM: Remove IO Daisychain control from cpuidle ARM: OMAP3PLUS: hwmod: reconfigure IO Daisychain during hwmod mux ARM: OMAP3+: PRM: Enable IO wake up ARM: OMAP4: PRM: Add IO Daisychain support ARM: OMAP3: PM: Move IO Daisychain function to omap3 prm file ARM: OMAP3: PM: correct enable/disable of daisy io chain ARM: OMAP2+: PRM: fix compile for OMAP4-only build Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * ARM: OMAP2+: PM: fix IRQ_NOAUTOEN removal by mis-mergeKevin Hilman2012-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 99b59df0 (ARM: OMAP3: PM: fix shared PRCM interrupt leave disabled at boot) added IRQ_NOAUTOEN to the PRCM interrupt so it could be enabled later if needed. However, this commit was partially undone when merging the IO daisy chain rework in 9a17d88e (Merge tag 'omap-devel-c-for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-pm This patch adds back the IRQ_NOAUTOEN fix that was removed by the merge resolution. This also fixes the following boot-time warning that showed up after merging the IO daisy chain rework: [ 3.849334] WARNING: at kernel/irq/manage.c:436 enable_irq+0x3c/0x78() [ 3.856231] Unbalanced enable for IRQ 297 [ 3.860473] Modules linked in: [ 3.863739] [<c001a114>] (unwind_backtrace+0x0/0xf0) from [<c003c7e8>] (warn_slowpath_common+0x4c/0x64) [ 3.873687] [<c003c7e8>] (warn_slowpath_common+0x4c/0x64) from [<c003c894>] (warn_slowpath_fmt+0x30/0x40) [ 3.883819] [<c003c894>] (warn_slowpath_fmt+0x30/0x40) from [<c00993e0>] (enable_irq+0x3c/0x78) [ 3.893035] [<c00993e0>] (enable_irq+0x3c/0x78) from [<c067b1e8>] (omap3_pm_init+0x328/0x5f4) [ 3.902099] [<c067b1e8>] (omap3_pm_init+0x328/0x5f4) from [<c067161c>] (init_machine_late+0x1c/0x28) [ 3.911773] [<c067161c>] (init_machine_late+0x1c/0x28) from [<c0008648>] (do_one_initcall+0x34/0x178) [ 3.921539] [<c0008648>] (do_one_initcall+0x34/0x178) from [<c066e8f4>] (kernel_init+0xfc/0x1c0) [ 3.930847] [<c066e8f4>] (kernel_init+0xfc/0x1c0) from [<c00140b0>] (kernel_thread_exit+0x0/0x8) [ 3.940246] ---[ end trace 55a0ad32ca2ca682 ]--- Reported-by: Javier Martinez Canillas <javier@dowhile0.org> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * Merge branch 'for_3.6/pm/performance' of ↵Tony Lindgren2012-06-27
| | |\ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into devel-pm
| | | * ARM: OMAP3: PM: cpuidle: optimize the clkdm idle latency in C1 stateJean Pihet2012-06-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For a power domain to idle all the clock domains in it must idle. This patch implements an optimization of the cpuidle code by denying and later allowing only the first registered clock domain of a power domain, and so optimizes the latency of the low power code. The functions _cpuidle_allow_idle and _cpuidle_deny_idle are not used anymore and so are removed. Signed-off-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | * ARM: OMAP3: PM: cpuidle: optimize the PER latency in C1 stateJean Pihet2012-06-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One of the main contributors of the low power code latency is the PER power domain. To optimize the high-performance and low-latency C1 state, prevent any PER state which is lower than the CORE state in C1. Reported and suggested by Kevin Hilman. Reported-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | * ARM: OMAP3: PM: cpuidle: default to C1 in next_valid_stateJean Pihet2012-06-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the next state is no found in the next_valid_state function, fallback to the default value of C1 (which is state 0). This prevents the use of a bogus state -1 in the rest of the cpuidle code. Signed-off-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | * ARM: OMAP3: PM: cleanup cam_pwrdm leftoversKevin Hilman2012-06-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit e7410cf7 (OMAP3: PM: move device-specific special cases from PM core into CPUidle) moved mangement of cam_pwrdm to CPUidle but left some remnants behind, namely the call to clkcm_allo_idle() for the clockdomains in the MPU pwrdm. Remove these since they are not necessary and cause unwanted latency in the idle path. Acked-by: Tero Kristo <Tero Kristo <t-kristo@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | * ARM: OMAP3: PM: call pre/post transition per powerdomainKevin Hilman2012-06-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We only need to call the pre/post transtion methods when we know the power state is changing. First, split up the pre/post transition calls to be per-powerdomain, and then make them conditional on whether the power domain is actually changing states. Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | * ARM: OMAP2+: powerdomain: allow pre/post transtion to be per pwrdmKevin Hilman2012-06-25
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Iteration over all power domains in the idle path is unnecessary since only power domains that are transitioning need to be accounted for. Also PRCM register accesses are known to be expensive, so the additional latency added to the idle path is signficiant. In order allow the pre/post transitions to be isolated and called per-pwrdm, change the API so passing in a specific power domain will trigger the pre/post transtion accounting for only that specific power domain. Passing NULL means iterating over all power domains as is current behavior. Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Grazvydas Ignotas <notasas@gmail.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | * Merge tag 'omap-devel-c-for-3.6' of ↵Tony Lindgren2012-06-25
| | |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-pm Reimplement the OMAP PRCM I/O chain code. Needed for I/O wakeups to work correctly. Conflicts: arch/arm/mach-omap2/prm2xxx_3xxx.c
| | | * ARM: OMAP3: PM: Remove IO Daisychain control from cpuidleVishwanath BS2012-06-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As IO Daisy chain sequence is triggered via hwmod mux, there is no need to control it from cpuidle path for OMAP3. Also as omap3_disable_io_chain is no longer being used, just remove the function. Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * ARM: OMAP3PLUS: hwmod: reconfigure IO Daisychain during hwmod muxVishwanath BS2012-06-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IO Daisychain feature has to be triggered whenever there is a change in device's mux configuration (See section 3.9.4 in OMAP4 Public TRM vP). Now devices can idle independent of the powerdomain, there can be a window where device is idled and corresponding powerdomain can be ON/INACTIVE state. In such situations, since both module wake up is enabled at padlevel as well as io daisychain sequence is triggered, there will be 2 PRCM interrupts (Module async wake up via swakeup and IO Pad interrupt). But as PRCM Interrupt handler clears the Module Padlevel WKST bit in the first interrupt, module specific interrupt handler will not triggered for the second time Also look at detailed explanation given by Rajendra at http://www.spinics.net/lists/linux-serial/msg04480.html Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: remove dependency on pm.c & pm.h; add kerneldoc] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * ARM: OMAP3+: PRM: Enable IO wake upTero Kristo2012-06-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable IO Wake up for OMAP3/4 as part of PRM Init. Currently this has been managed in cpuidle path which is not the right place. Subsequent patch will remove IO Daisy chain handling in cpuidle path once daisy chain is handled as part of hwmod mux. This patch also moves the OMAP4 IO wakeup enable code from the trigger function to init time setup. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: harmonize function names with other PRM functions; add kerneldoc; resolve checkpatch warnings] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * ARM: OMAP4: PRM: Add IO Daisychain supportRajendra Nayak2012-06-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IO daisychain is a mechanism that allows individual IO pads to generate wakeup events on their own based on a switch of an input signal level. This allows the hardware module behind the pad to be powered down, but still have device level capability to detect IO events, and once this happens the module can be powered back up to resume IO. See section 3.9.4 in OMAP4430 Public TRM for details. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> [paul@pwsan.com: use the shared MAX_IOPAD_LATCH_TIME declaration; renamed omap4_trigger_io_chain() to conform to other PRM function names; added kerneldoc; resolved checkpatch warnings] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * ARM: OMAP3: PM: Move IO Daisychain function to omap3 prm fileVishwanath BS2012-06-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since IO Daisychain modifies only PRM registers, it makes sense to move it to PRM File. Also changed the timeout value for IO chain enable to 100us and added a wait for status disable at the end. Thanks to Nishanth Menon <nm@ti.com> for contributing a fix to the timeout code waiting for WUCLKOUT to go high. Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Cc: Nishanth Menon <nm@ti.com> Reviewed-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: renamed omap3_trigger_io_chain() to better describe the end result and to match other PRM functions; removed omap3_disable_io_chain(); moved MAX_IOPAD_LATCH_TIME to prcm-common as it will also be used by the OMAP4 code; removed unnecessary barrier; added kerneldoc; added credit for fix from Nishanth] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * ARM: OMAP3: PM: correct enable/disable of daisy io chainMohan V2012-06-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the enabling and disabling of IO Daisy chain is not according to the TRM. The below steps are followed to enable/ disable the IO chain, based loosely on the "Sec 3.5.7.2.2 I/O Wake-Up Mechanism" section in OMAP3630 Public TRM[1]. Steps to enable IO chain: [a] Set PM_WKEN_WKUP.EN_IO bit [b] Set the PM_WKEN_WKUP.EN_IO_CHAIN bit [c] Poll for PM_WKST_WKUP.ST_IO_CHAIN. [d] When ST_IO_CHAIN bit set to 1, clear PM_WKEN_WKUP.EN_IO_CHAIN [e] Clear ST_IO_CHAIN bit. Steps to disable IO chain: [a] Clear PM_WKEN_WKUP.EN_IO_CHAIN bit [b] Clear PM_WKEN_WKUP.EN_IO bit [c] Clear PM_WKST_WKUP.ST_IO bit by writing 1 to it. Step [e] & [c] in each case can be skipped, as these are handled by the PRCM interrupt handler later. [1] http://focus.ti.com/pdfs/wtbu/OMAP36xx_ES1.x_PUBLIC_TRM_vV.zip Signed-off-by: Mohan V <mohanv@ti.com> Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> [paul@pwsan.com: modified commit message to clarify that these steps are based loosely on the TRM section, rather than documented exactly] Reviewed-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: resolved new warnings from checkpatch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * ARM: OMAP2+: PRM: fix compile for OMAP4-only buildKevin Hilman2012-06-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For OMAP4 only builds, the omap2_prm_* functions have dummy wrappers to detect incorrect usage. However, several unrelated omap3 PRM functions have made it inside the #else clause of the #ifdef wrapping the omap2_prm stubs, causing them to disappear on OMAP4-only builds. This was unnoticed until the IO chain support was added and introduced a new function in this section which is referenced by omap_hwmod.c: arch/arm/mach-omap2/omap_hwmod.c: In function '_reconfigure_io_chain': arch/arm/mach-omap2/omap_hwmod.c:1665:3: error: implicit declaration of function 'omap3xxx_prm_reconfigure_io_chain' [-Werror=implicit-function-declaration] Fix by using the #ifdef to only wrap the omap2_prm functions that need stubs on OMAP4-only builds. Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@ti.com> [paul@pwsan.com: fixed checkpatch warnings for patch description] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | Merge tag 'omap-devel-driver-for-v3.6' of ↵Arnd Bergmann2012-07-03
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/pm From Tony Lindgren <tony@atomide.com>: Here are omap driver changes for v3.6 that were agreed to be merged via the omap tree. These changes convert omap HDQ1W driver to use runtime PM, and finally move omap SmartReflex driver from arch/arm to live under drivers. * tag 'omap-devel-driver-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: do not allow SmartReflex to be built as a module ARM: OMAP2: Use hwmod to initialize mmc for 2420 W1: OMAP HDQ1W: use runtime PM ARM: OMAP2+: HDQ1W: use omap_device W1: OMAP HDQ1W: use 32-bit register accesses W1: OMAP HDQ1W: allow driver to be built on all OMAP2+ ARM: OMAP: SmartReflex: Move smartreflex driver to drivers/ ARM: OMAP2+: SmartReflex: add POWER_AVS Kconfig options ARM: OMAP2+: SmartReflex: Create per-opp debugfs node for errminlimit ARM: OMAP2+: SmartReflex: Use per-OPP data structure ARM: OMAP2+: Voltage: Move the omap_volt_data structure to plat ARM: OMAP2+: SmartReflex: introduce a busy loop condition test macro ARM: OMAP3: hwmod: rename the smartreflex entries ARM: OMAP2+: smartreflex: Use the names from hwmod data instead of voltage domains. ARM: OMAP3+: SmartReflex: class drivers should use struct omap_sr * ARM: OMAP2+: SmartReflex: move the smartreflex header to include/linux/power Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * | | ARM: OMAP2+: do not allow SmartReflex to be built as a moduleJean Pihet2012-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable the module option for POWER_AVS since this is currently not supported. This patch fixes these error in the case POWER_AVS is set to 'm': arch/arm/mach-omap2/built-in.o: In function `sr_class3_configure': arch/arm/mach-omap2/smartreflex-class3.c:43: undefined reference to `sr_configure_errgen' arch/arm/mach-omap2/built-in.o: In function `sr_class3_disable': arch/arm/mach-omap2/smartreflex-class3.c:33: undefined reference to `sr_disable_errgen' arch/arm/mach-omap2/smartreflex-class3.c:35: undefined reference to `sr_disable' arch/arm/mach-omap2/built-in.o: In function `sr_class3_enable': arch/arm/mach-omap2/smartreflex-class3.c:28: undefined reference to `sr_enable' arch/arm/mach-omap2/built-in.o: In function `sr_class3_init': arch/arm/mach-omap2/smartreflex-class3.c:59: undefined reference to `sr_register_class' Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com> [tony@atomide.com: updated to use relative paths for the build error] Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | Merge branch 'for_3.6/pm/sr-move' of ↵Tony Lindgren2012-06-26
| | |\ \ \ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into devel-driver
| | | * | | ARM: OMAP: SmartReflex: Move smartreflex driver to drivers/Jean Pihet2012-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After a clean-up of the interfaces the OMAP Smartreflex IP driver is now a generic driver. Move it to drivers/power/avs/. The build is controlled by the following Kconfig options: . CONFIG_POWER_AVS: general knob for Adaptive Voltage Scaling support, . CONFIG_POWER_AVS_OMAP: AVS(Adaptive Voltage Scaling) support on OMAP containing the version 1 or version 2 of the SmartReflex IP, . CONFIG_POWER_AVS_OMAP_CLASS3: Class 3 implementation of Smartreflex. Signed-off-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: J Keerthy <j-keerthy@ti.com> Acked-by: Rafael J. Wysocki <rjw@sisk.pl> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | * | | ARM: OMAP2+: SmartReflex: add POWER_AVS Kconfig optionsJean Pihet2012-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a Kconfig menu (POWER_AVS) and rename the Kconfig options for the OMAP SmartReflex implementation: CONFIG_OMAP_SMARTREFLEX renames to CONFIG_POWER_AVS_OMAP CONFIG_OMAP_SMARTREFLEX_CLASS3 renames to CONFIG_POWER_AVS_OMAP_CLASS3 This change makes the SmartReflex implementation ready for the move to drivers/. Signed-off-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: J Keerthy <j-keerthy@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | * | | ARM: OMAP2+: SmartReflex: Create per-opp debugfs node for errminlimitJean Pihet2012-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the global errminlimit debugfs entry and create per-voltage entries from the data tables. Signed-off-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: J Keerthy <j-keerthy@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | * | | ARM: OMAP2+: SmartReflex: Use per-OPP data structureJean Pihet2012-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SmartReflex driver incorrectly treats some per-OPP data as data common to all OPPs (e.g., ERRMINLIMIT). Move this data into a per-OPP data structure. Furthermore, in order to make the SmartReflex implementation ready for the move to drivers/, remove the dependency from the SR driver code to the voltage layer by querying the data tables only from the SR device init code. Based on Paul's original code for the SmartReflex driver conversion. Signed-off-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: J Keerthy <j-keerthy@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | * | | ARM: OMAP2+: Voltage: Move the omap_volt_data structure to platJ Keerthy2012-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the omap_volt_data structure from mach-omap2/ directory to arch/arm/plat-omap/include/plat/ so that it is accessible from both mach-omap2 and drivers directories. Signed-off-by: J Keerthy <j-keerthy@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | * | | ARM: OMAP2+: SmartReflex: introduce a busy loop condition test macroJean Pihet2012-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that omap_test_timeout is only accessible from mach-omap2/, introduce a similar function for SR. This change makes the SmartReflex implementation ready for the move to drivers/. Signed-off-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: J Keerthy <j-keerthy@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | * | | ARM: OMAP3: hwmod: rename the smartreflex entriesJean Pihet2012-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the name field value to better reflect the smartreflex integration in the system. Signed-off-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: J Keerthy <j-keerthy@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | * | | ARM: OMAP2+: smartreflex: Use the names from hwmod data instead of voltage ↵Jean Pihet2012-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | domains. Associate a name with each SmartReflex instance from the hwmod data, rather than attempting to reuse the name of a voltage domain. The name from hwmod better reflects the smartreflex integration in the system. Also have the name passed to the drivers using pdata, which helps to remove any dependencies on SoC-specific structures. Signed-off-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: J Keerthy <j-keerthy@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | * | | ARM: OMAP3+: SmartReflex: class drivers should use struct omap_sr *Jean Pihet2012-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert SmartReflex "class" functions to take a struct omap_sr *, rather than a struct voltagedomain *. SmartReflex code should be driver code and not tightly coupled to OMAP subarchitecture-specific structures. Based on Paul's original code for the SmartReflex driver conversion. Signed-off-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: J Keerthy <j-keerthy@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | * | | ARM: OMAP2+: SmartReflex: move the smartreflex header to include/linux/powerJean Pihet2012-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the smartreflex header file (arch/arm/mach-omap2/smartreflex.h) in a new header file include/linux/power/smartreflex.h. This change makes the SmartReflex implementation ready for the move to drivers/. Signed-off-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: J Keerthy <j-keerthy@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | * | | | ARM: OMAP2: Use hwmod to initialize mmc for 2420Tony Lindgren2012-06-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to pass dma request lines in platform data to MMC driver the same way as we already do for omap2430 and later. Also note that we need to only build this code if MMC_OMAP is selected, so change Makefile accordingly and place it near the MMC_OMAP_HS in the Makefile. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | | Merge tag 'omap-devel-b-for-3.6' of ↵Tony Lindgren2012-06-25
| | |\ \ \ \ | | | |_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-driver Convert the OMAP HDQ1W driver to use runtime PM. Make it available on all OMAP2+ chips that appear to have it integrated. Fix a problem preventing it from being used on OMAP4.
| | | * | | W1: OMAP HDQ1W: use runtime PMPaul Walmsley2012-06-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the OMAP HDQ driver to use runtime PM. Compile- and boot-tested, but not tested in actual use. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: NeilBrown <neilb@suse.de> Cc: Evgeniy Polyakov <zbr@ioremap.net> Acked-by: Evgeniy Polyakov <zbr@ioremap.net> Tested-by: NeilBrown <neilb@suse.de>
| | | * | | ARM: OMAP2+: HDQ1W: use omap_devicePaul Walmsley2012-06-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the old-style device registration code for HDQ1W to use omap_device. This will allow the driver to be converted to use PM runtime and to take advantage of the OMAP IP block management infrastructure (hwmod, PM, etc.). A side benefit of this conversion is that it also makes the HDQ device available on OMAP2420. The previous code only enabled it on 2430 and 3430. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: NeilBrown <neilb@suse.de> Tested-by: NeilBrown <neilb@suse.de>
| | | * | | W1: OMAP HDQ1W: use 32-bit register accessesPaul Walmsley2012-06-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HDQ/1-wire registers are 32 bits long, even if the register contents fit into 8 bits, so accesses must be 32-bit aligned. Evidently the OMAP2/3 interconnects allowed the driver to get away with 8 bit accesses, but the OMAP4 puts a stop to that: [ 1.488800] Driver for 1-wire Dallas network protocol. [ 1.495025] Bad mode in data abort handler detected [ 1.500122] Internal error: Oops - bad mode: 0 [#1] SMP [ 1.505615] Modules linked in: [ 1.508819] CPU: 0 Not tainted (3.3.0-rc1-00008-g45030e9 #992) [ 1.515289] PC is at 0xffff0018 [ 1.518615] LR is at omap_hdq_probe+0xd4/0x2cc The OMAP4430 ES2 Rev X TRM does warn about this restriction in section 23.2.6.2 "HDQ/1-Wire Registers". Fixes the crash on OMAP4430 ES2 Pandaboard. Tested also on OMAP34xx and OMAP2420; it seems to work fine on those chips, although due to the lack of boards with HDQ/1-wire devices here, a more indepth test was not possible. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: NeilBrown <neilb@suse.de> Cc: Evgeniy Polyakov <zbr@ioremap.net> Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
| | | * | | W1: OMAP HDQ1W: allow driver to be built on all OMAP2+Paul Walmsley2012-06-21
| | | | |/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the OMAP HDQ1W driver to be built for all OMAP2+ SoCs by adjusting KConfig dependencies. The previous dependency required either SOC_OMAP2430 or ARCH_OMAP3 to be set, but the HDQ IP block is present on OMAP2420 and OMAP44xx SoCs. The driver was still selectable on multi-OMAP kernel configurations, however; so the previous prohibition was rather pointless. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Evgeniy Polyakov <zbr@ioremap.net> Acked-by: Evgeniy Polyakov <zbr@ioremap.net>
| * | | | Merge branch 'imx/cpuidle' into next/pmOlof Johansson2012-06-30
| |\ \ \ \ | | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * imx/cpuidle: ARM: imx: Add imx6q cpuidle driver ARM: imx: Add imx5 cpuidle ARM: imx: Add common imx cpuidle init functionality. ARM: imx: Enable imx53 low power idle ARM: imx: clean and consolidate imx5 suspend and idle code ARM: imx: Add comments to tzic_enable_waker() ARM: imx: Modify IMX_IO_P2V macro Resolved trivial context conflict in arch/arm/plat-mxc/include/mach/common.h Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | ARM: imx: Add imx6q cpuidle driverRobert Lee2012-06-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic imx6q cpuidle driver. For now, only basic WFI state is supported. Deeper idle states will be added in the future. Signed-off-by: Robert Lee <rob.lee@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | * | | ARM: imx: Add imx5 cpuidleRobert Lee2012-06-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add cpuidle driver for imx5 platform. Signed-off-by: Robert Lee <rob.lee@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | * | | ARM: imx: Add common imx cpuidle init functionality.Robert Lee2012-06-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add common cpuidle init functionality that can be used by various imx platforms. Signed-off-by: Robert Lee <rob.lee@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | * | | ARM: imx: Enable imx53 low power idleRobert Lee2012-06-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add various functionality needed to enable a imx53 low power idle state. This includes adding the imx53 gpc_dvfs clock and making a common imx5_late_init function and initializing all imx53 MACHINE_STATE late_init calls to imx5_late_init. Signed-off-by: Robert Lee <rob.lee@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | * | | ARM: imx: clean and consolidate imx5 suspend and idle codeRobert Lee2012-06-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The imx5 idle code that existed in mm-imx5.c is moved to pm-imx5.c. The imx5_pm_init call is now exported and called during the MACHINE_START late_init in supported imx5 platforms. Remove various enabling/disabling of the gpc_dvfs clock and enable it once during initialization. This is a very low power clock that must be enabled during low power operations. There are only two "suspend_state_t" imx5 low power modes ever used. STOP_POWER_OFF for suspend to mem and WAIT_UNCLOCKED_POWER_OFF for idle and suspend to standby. The latter mode only requires 500 nanoseconds of extra hardware exit time beyond a basic WFI operation (WAIT_CLOCKED mode) so no other idle mode is necessary. Given this information, it is more efficient to keep the registers in the often used WAIT_UNCLOCKED_POWER_OFF state and only to and from the STOP_POWER_OFF register state as needed when suspend to mem is required. Signed-off-by: Robert Lee <rob.lee@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | * | | ARM: imx: Add comments to tzic_enable_waker()Robert Lee2012-06-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add additional comments to the tzic_enable_wake() funciton to clarify its intended usage. Signed-off-by: Robert Lee <rob.lee@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | * | | ARM: imx: Modify IMX_IO_P2V macroRobert Lee2012-06-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A change is needed in the IMX_IO_P2V macro to allow all imx5 platforms to use common definitions when accessing registers of peripherals on the AIPS2 bus. With this change, IMX_IO_P2V(MX50_AIPS2_BASE_ADDR) == IMX_IO_P2V(MX51_AIPS2_BASE_ADDR) == IMX_IO_P2V(MX53_AIPS2_BASE_ADDR). This change was tested for mapping conflicts using the iop2v script found at git://git.pengutronix.de/git/ukl/imx-iop2v.git and by performing a bootup of a default build using imx_v6_v7_defconfig on a imx51 babbage board and imx53 loco board. The comments were modified to reflect the output given by the script which shows the virtual address mappings. Signed-off-by: Robert Lee <rob.lee@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | | | Merge tag 'pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2012-07-23
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull arm-soc pincontrol drivers update from Arnd Bergmann: "We are converting platforms to use the pinctrl framework over time, rather than using platform specific code for the same effect. This adds the respective driver for the prima2 platform." * tag 'pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: prima2: enable gpiolib unconditionally PINCTRL: SiRF: add GPIO and GPIO irq support in CSR SiRFprimaII
| * \ \ \ \ Merge branch 'prima2/pinctrl' into next/pinctrlArnd Bergmann2012-07-04
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * prima2/pinctrl: ARM: prima2: enable gpiolib unconditionally
| | * | | | | ARM: prima2: enable gpiolib unconditionallyArnd Bergmann2012-07-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinctrl code needs GPIOLIB to be enabled, so make sure that it cannot be built otherwise. This fixes the prima2_defconfig. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Barry Song <21cnbao@gmail.com>
| * | | | | | Merge branch 'prima2/drivers' of ↵Arnd Bergmann2012-07-02
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel into next/pinctrl * 'prima2/drivers' of git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel: PINCTRL: SiRF: add GPIO and GPIO irq support in CSR SiRFprimaII Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <inus.walleij@linaro.org>
| | * | | | | PINCTRL: SiRF: add GPIO and GPIO irq support in CSR SiRFprimaIIBarry Song2012-07-01
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In SiRFprimaII, Each GPIO pin can be configured as input or output independently. If a GPIO is configured as input, it can also be enabled as an interrupt source (either edge or level triggered). These pins must be either MUXed as GPIO or other function pads. Signed-off-by: Yuping Luo <yuping.luo@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-29 23:42:41 -0400