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| * | | | | Merge branch 'for-3.10/soc' into for-3.10/clkStephen Warren2013-04-04
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* | \ \ \ \ \ Merge branch 'depends/clk' into next/driversArnd Bergmann2013-04-09
|\ \ \ \ \ \ \ | | |_|/ / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a snapshot of the stable clk branch at git://git.linaro.org/people/mturquette/linux.git clk-for-3.10 which is a dependency for the tegra clock changes. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | | | | clk: allow reentrant calls into the clk frameworkMike Turquette2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reentrancy into the clock framework is necessary for clock operations that result in nested calls to the clk api. A common example is a clock that is prepared via an i2c transaction, such as a clock inside of a discrete audio chip or a power management IC. The i2c subsystem itself will use the clk api resulting in a deadlock: clk_prepare(audio_clk) i2c_transfer(..) clk_prepare(i2c_controller_clk) The ability to reenter the clock framework prevents this deadlock. Other use cases exist such as allowing .set_rate callbacks to call clk_set_parent to achieve the best rate, or to save power in certain configurations. Yet another example is performing pinctrl operations from a clk_ops callback. Calls into the pinctrl subsystem may call clk_{un}prepare on an unrelated clock. Allowing for nested calls to reenter the clock framework enables both of these use cases. Reentrancy is implemented by two global pointers that track the owner currently holding a global lock. One pointer tracks the owner during sleepable, mutex-protected operations and the other one tracks the owner during non-interruptible, spinlock-protected operations. When the clk framework is entered we try to hold the global lock. If it is held we compare the current task against the current owner; a match implies a nested call and we reenter. If the values do not match then we block on the lock until it is released. Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org> Cc: David Brown <davidb@codeaurora.org> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | | | | clk: abstract locking out into helper functionsMike Turquette2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create locking helpers for the global mutex and global spinlock. The definitions of these helpers will be expanded upon in the next patch which introduces reentrancy into the locking scheme. Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org> Cc: David Brown <davidb@codeaurora.org> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | | | | clk: zynq: Add missing zynq clk headerMichal Simek2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Include zynq clk header where init function is declared. It removes this sparse warning: drivers/clk/clk-zynq.c:373:13: warning: symbol 'xilinx_zynq_clocks_init' was not declared. Should it be static? Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | | clk: sunxi: rename compatible stringsEmilio López2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the introduction of the Allwinner SoC platforms, sunxi was initially meant as a generic name for all the variants of the Allwinner SoC. It was ok at the time of the support of only the A10 and A13 that look pretty much the same; but it's beginning to be troublesome with the future addition of the Allwinner A31 (sun6i) that is quite different, and would introduce some weird logic, where sunxi would actually mean in some case sun4i and sun5i but without sun6i... Moreover, it makes the compatible strings naming scheme not consistent with other architectures, where usually for this kind of compability, we just use the oldest SoC name that has this IP, so let's do just this. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | | arm: sunxi: Add useful information about sunxi clocksEmilio López2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains useful bits of information about the sunxi clocks that may help and/or be interesting for current and future developers. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | | clk: arm: sunxi: Add a new clock driver for sunxi SOCsEmilio López2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit implements the base CPU clocks for sunxi devices. It has been tested using a slightly modified cpufreq driver from the linux-sunxi 3.0 tree. Additionally, document the new bindings introduced by this patch. Idling: / # cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc32k 0 0 32768 osc24M_fixed 0 0 24000000 osc24M 0 0 24000000 apb1_mux 0 0 24000000 apb1 0 0 24000000 pll1 0 0 60000000 cpu 0 0 60000000 axi 0 0 60000000 ahb 0 0 60000000 apb0 0 0 30000000 dummy 0 0 0 After "yes >/dev/null &": / # cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc32k 0 0 32768 osc24M_fixed 0 0 24000000 osc24M 0 0 24000000 apb1_mux 0 0 24000000 apb1 0 0 24000000 pll1 0 0 1008000000 cpu 0 0 1008000000 axi 0 0 336000000 ahb 0 0 168000000 apb0 0 0 84000000 dummy 0 0 0 Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | | clk: ux500: Fix prcmu clocks registrationMaxime Coquelin2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In clk_reg_prcmu(), clk->hw.init field is assigned with a reference local to clk_reg_prcmu() function. This patch replaces references to clk->hw.init with calls to __clk_get_name when called after clock registration. This patch applies on top of v3.9-rc4. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: resolved trivial merge issues]
| * | | | | | ARM: imx: adapt clk_busy_mux to new clk_mux structFabio Estevam2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ce4f3313b05 (clk: add table lookup to mux) caused the following build error on imx_v4_v5_defconfig/imx_v6_v7_defconfig: arch/arm/mach-imx/clk-busy.c:172:11: error: 'struct clk_mux' has no member named 'width' Fix it by passing the 'mask' field. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: shortened $SUBJECT line]
| * | | | | | clk: Add composite clock typePrashant Gaikwad2013-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | | clk: add table lookup to muxPeter De Schrijver2013-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a table lookup feature to the mux clock. Also allow arbitrary masks instead of the width. This will be used by some clocks on Tegra114. Also adapt the tegra periph clk because it uses struct clk_mux directly. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | | clk: Fix incorrect return type in clk.cSachin Kamat2013-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Return type of function clk_propagate_rate_change is a pointer. But 0 was being returned. Change it to NULL. Silences the following warning: drivers/clk/clk.c:977:24: warning: Using plain integer as NULL pointer Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reviewed-by: Pankaj Jangra <jangra.pankaj9@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | | clk: prima2: fix return value check in sirfsoc_of_clk_init()Wei Yongjun2013-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of error, the function clk_get() returns ERR_PTR() not NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Barry Song <21cnbao@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: added missing parenthesis to fix compile break]
| * | | | | | clk:SPEAr1340: Correct parent clock configurationVipul Kumar Samar2013-03-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch corrects wrongly configured parent clock for following devices: * Video enc/decoder * Video ip * Pin control * ACP * camx Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Reviewed-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | | documentation: clk: fix couple of misspellingEduardo Valentin2013-03-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correcting misspelling inside the clk.txt. Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | | clk: Add axi-clkgen driverLars-Peter Clausen2013-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | | clk: ux500: Support is_prepared callback for clk-prcmuUlf Hansson2013-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To be able to gate unused prcmu clocks from the clk_disable_unused sequence, clk-prcmu now implements the is_prepared callback. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | | clk: Introduce optional unprepare_unused callbackUlf Hansson2013-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An unprepare_unused callback is introduced due to the same reasons to why the disable_unused callback was added. During the clk_disable_unused sequence, those clk_hw that needs specific treatment with regards to being unprepared, shall implement the unprepare_unused callback. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | | clk: Unprepare the unused prepared slow clocks at late initUlf Hansson2013-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The unused ungated fast clocks are already being disabled from clk_disable_unused at late init. This patch extend this sequence to the slow unused prepared clocks to be unprepared. Unless the optional .is_prepared callback is implemented by a clk_hw the clk_disable_unused sequence will not unprepare any unused clocks, since it will fall back to use the software prepare counter. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed hlist accessors per b67bfe0d]
| * | | | | | clk: Introduce optional is_prepared callbackUlf Hansson2013-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To reflect whether a clk_hw is prepared the clk_hw may implement the optional is_prepared callback. If not implemented we fall back to use the software prepare counter. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | | clk: mxs: Fix sparse warningsFabio Estevam2013-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following sparse warnings: drivers/clk/mxs/clk.c:17:1: warning: symbol 'mxs_lock' was not declared. Should it be static? drivers/clk/mxs/clk.c:19:5: warning: symbol 'mxs_clk_wait' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | | | | | Merge branch 'tegra/soc' into next/driversArnd Bergmann2013-04-09
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a dependency for the tegra/clk branch. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Conflicts: drivers/clocksource/tegra20_timer.c
| * | | | | | | ARM: tegra: pm: remove duplicated include from pm.cWei Yongjun2013-04-05
| | |_|/ / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove duplicated include. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: cpuidle: remove redundant parameters for powered-down modeJoseph Lo2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After the patch series for system suspending support, tegra_idle_lp2_last() no longer uses its parameters cpu_on_time or cpu_off_time, so remove them. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: pm: add platform suspend supportJoseph Lo2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding suspend to RAM support for Tegra platform. There are three suspend mode for Tegra. The difference were below. * LP2: CPU voltage off * LP1: CPU voltage off, DRAM in self-refresh * LP0: CPU + Core voltage off, DRAM in self-refresh After this patch, the LP2 suspend mode will be supported. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: dt: tegra: add bindings of power management configurations for PMCJoseph Lo2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PMC mostly controls the entry and exit of the system from different sleep modes. Different platform or system may have different configurations. The power management configurations of PMC is represented as some properties. The system needs to define the properties when the system supports deep sleep mode (i.e. suspend). Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: devicetree-discuss@lists.ozlabs.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: irq: add wake up handlingJoseph Lo2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the wake up handling for legacy irq controller, and using IRQCHIP_MASK_ON_SUSPEND for wake irq handling. Based on the work by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | gpio: tegra: add gpio wakeup source handlingJoseph Lo2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add the gpio wakeup source handling for the Tegra platform. It was be done by enabling the irq for the gpio in the gpio controller and enabling the bank irq of the gpio in the Tegra legacy irq controller when the system going to suspend. Based on the work by: Varun Wadekar <vwadekar@nvidia.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: moving the CPU power timer function to PMC driverJoseph Lo2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU power timer set up function was related to PMC register. Now moving it to PMC driver. And it also help to clean up the PM related code later. The timer was calculated based on the input clock of PMC. In this patch, we also get the clock from DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: add clock source of PMC to device treesJoseph Lo2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding the bindings of the clock source of PMC in DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: add speedo-based process id for Tegra114Danny Huang2013-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add speedo-based process identification for Tegra114. Based on the work by: Alex Frid <afrid@nvidia.com> Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren: added include of bug.h] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: expose chip ID and revisionDanny Huang2013-03-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose Tegra chip ID and revision in /sys/devices/soc for user mode usage Signed-off-by: Danny Huang <dahuang@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: bring up secondary CPU for Tegra114Joseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The secondary CPU can be brought up by toggling the power in PMC. Then the flow controller will release CPU to go by clearing the reset and clamp signal automatically. Based on the work by: Bo Yan <byan@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: replace the CPU power on function with PMC callJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the CPU power on function in PMC driver to bring up secondary CPUs, because we are going to re-factor powergate driver to support generic power domain. It will be removed later and added the generic power domain support in PMC driver. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: pmc: add power on function for secondary CPUsJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding the power on function for secondary CPUs in PMC driver, this can help us to remove legacy powergate driver and add generic power domain support later. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: pmc: convert PMC driver to support DT onlyJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra kernel only support boot from DT now. Clean up the PMC driver to support DT only, that includes: * remove the ifdef of CONFIG_OF * replace the static mapping of PMC addr to map from DT Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: fix the PMC compatible string in DTJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PMC HW is not 100% compatible across all Tegra series. We need to specify them in DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: pmc: add specific compatible DT string for Tegra30 and Tegra114Joseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PMC HW is not 100% compatible across all Tegra series. We need to specify each of them in the DT match table. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: refactor tegra{20,30}_boot_secondaryHiroshi Doyu2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "tegra_boot_secondary()" has many condition branches for some Tegra SoC generations in a single function so that it's not easy to compile a kernel only for a single SoC if one wants with some reason, debug purpose(?). This patch provides SoC specific version of boot_secondary(), tegra{20,30}_boot_secondary(). This could allow any combination of SoC to be built. Those boot_secondary functions can be preparation when we ntroduce chip specific function pointers in the future without having chip dependent branches around. Also removed unused definition/prototpye. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> [josephl: remove the Tegra114 part of the original patch] Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | clocksource: tegra: move to of_clk_getPeter De Schrijver2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new clockframework introduced DT IDs for each clock. To be able to remove the device registrations, this driver needs to be updated to use the DT IDs. Note that the actual removal of the clk_register_clkdev() calls will be done in a later series. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: Unify Device tree board filesHiroshi Doyu2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unify board-dt-tegra{30,114} to the Tegra20 DT board file, "tegra.c". Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: Rename board-dt-tegra20.c to tegra.cHiroshi Doyu2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the preparation to unify "board-dt-tegra{20,30,114}.c" to a single file "tegra.c". Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: Unify tegra{20,30,114}_init_early()Hiroshi Doyu2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactored tegra{20,30,114}_init_early() so that we have the unified tegra_init_early(). Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: fix ignored return value of regulator_enableStephen Warren2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes: arch/arm/mach-tegra/board-harmony-pcie.c: In function ‘harmony_pcie_init’: arch/arm/mach-tegra/board-harmony-pcie.c:65:18: warning: ignoring return value of ‘regulator_enable’, declared with attribute warn_unused_result [-Wunused-result] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: fix the logical detection of power on sequence of warm boot CPUsJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The warm boot sequence of Tegra30 secondary CPUs should wait for the power ready then removing the clamps. This did not fix any known or unknown issue, but nice to have this fix. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: Fix unchecked return valueHiroshi Doyu2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check a return value for tegra_powergate_remove_clamping(). Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: don't unlock MMIO access to DBGLARJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to unlock MMIO access to the DBGLAR all the time. Doing so may even cause problems if a SW bug causes writes to that MMIO region. Cortex-A15 processors do not support the CP14 register write the code currently uses to unlock the DBGLAR; the instruction throws an undefined instruction exceptions. This prevents tegra_secondary_startup() from executing on Tegra114, and hence prevents SMP. Remove the code that unlocks this access. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | clk: tegra: No 7.1 super clk dividers on Tegra20Peter De Schrijver2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk. Remove the clocks related to the divider. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | | ARM: tegra: remove save/restore of CPU diag registerStephen Warren2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this change, {save,restore}_cpu_arch_register() collaborated to maintain the value of the CPU diagnostic register across power cycles. This was required to maintain any CPU errata workaround enable bits in that register. However, now that the Tegra reset vector code always enables all required workarounds, there is no need to save and restore the diagnostic register; it is always explicitly programmed in the required manner. Hence, remove the save/restore logic. This has the advantage that the kernel always directly controls the value of this register every boot, rather than relying on a bootloader or other kernel code having previously written the correct value into it. This makes CPU0 (which was previously saved/restored) and CPUn (which should have been set up by the reset vector) be controlled in exactly the same way, which is easier to debug/find/... In particular, when converting Tegra to a multi-platform kernel, the CPU0 diagnostic register value initially comes from the bootloader. Most Tegra bootloaders don't yet enable all required CPU bug workarounds. The previous commit updates the kernel to do so on any CPU power cycle. However, the save/restore code ends up over-writing the value with the old bootloader-driven value instead of the now more-likely-to-be-correct kernel value! Even irrespective of multi-platform conversion, this change limits the kernel's exposure to any WARs the bootloader didn't enable for CPU0: on the very first LP2 transition (CPU power-saving which power-cycles the CPU), the correct value will be enabled. Signed-off-by: Stephen Warren <swarren@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-15 15:20:03 -0400