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authorVipul Kumar Samar <vipulkumar.samar@st.com>2013-03-07 02:05:24 -0500
committerMike Turquette <mturquette@linaro.org>2013-03-21 17:36:55 -0400
commit04981724172062029c4986e1d90732ff3c574944 (patch)
treec6183348bb401a780e5d59364e0a27f73ecc325b
parenta368a6a33b107d680e955c799e6e1e3d6b4bbe8a (diff)
clk:SPEAr1340: Correct parent clock configuration
This patch corrects wrongly configured parent clock for following devices: * Video enc/decoder * Video ip * Pin control * ACP * camx Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Reviewed-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
-rw-r--r--drivers/clk/spear/spear1340_clock.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index 82abea366b78..35e7e2698e10 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -960,47 +960,47 @@ void __init spear1340_clk_init(void)
960 SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock); 960 SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock);
961 clk_register_clkdev(clk, NULL, "d0100000.spdif-in"); 961 clk_register_clkdev(clk, NULL, "d0100000.spdif-in");
962 962
963 clk = clk_register_gate(NULL, "acp_clk", "acp_mclk", 0, 963 clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0,
964 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0, 964 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
965 &_lock); 965 &_lock);
966 clk_register_clkdev(clk, NULL, "acp_clk"); 966 clk_register_clkdev(clk, NULL, "acp_clk");
967 967
968 clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mclk", 0, 968 clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0,
969 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0, 969 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
970 &_lock); 970 &_lock);
971 clk_register_clkdev(clk, NULL, "e2800000.gpio"); 971 clk_register_clkdev(clk, NULL, "e2800000.gpio");
972 972
973 clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mclk", 0, 973 clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0,
974 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB, 974 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
975 0, &_lock); 975 0, &_lock);
976 clk_register_clkdev(clk, NULL, "video_dec"); 976 clk_register_clkdev(clk, NULL, "video_dec");
977 977
978 clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mclk", 0, 978 clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0,
979 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB, 979 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
980 0, &_lock); 980 0, &_lock);
981 clk_register_clkdev(clk, NULL, "video_enc"); 981 clk_register_clkdev(clk, NULL, "video_enc");
982 982
983 clk = clk_register_gate(NULL, "video_in_clk", "video_in_mclk", 0, 983 clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0,
984 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0, 984 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
985 &_lock); 985 &_lock);
986 clk_register_clkdev(clk, NULL, "spear_vip"); 986 clk_register_clkdev(clk, NULL, "spear_vip");
987 987
988 clk = clk_register_gate(NULL, "cam0_clk", "cam0_mclk", 0, 988 clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0,
989 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0, 989 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
990 &_lock); 990 &_lock);
991 clk_register_clkdev(clk, NULL, "d0200000.cam0"); 991 clk_register_clkdev(clk, NULL, "d0200000.cam0");
992 992
993 clk = clk_register_gate(NULL, "cam1_clk", "cam1_mclk", 0, 993 clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0,
994 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0, 994 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
995 &_lock); 995 &_lock);
996 clk_register_clkdev(clk, NULL, "d0300000.cam1"); 996 clk_register_clkdev(clk, NULL, "d0300000.cam1");
997 997
998 clk = clk_register_gate(NULL, "cam2_clk", "cam2_mclk", 0, 998 clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0,
999 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0, 999 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
1000 &_lock); 1000 &_lock);
1001 clk_register_clkdev(clk, NULL, "d0400000.cam2"); 1001 clk_register_clkdev(clk, NULL, "d0400000.cam2");
1002 1002
1003 clk = clk_register_gate(NULL, "cam3_clk", "cam3_mclk", 0, 1003 clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0,
1004 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0, 1004 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
1005 &_lock); 1005 &_lock);
1006 clk_register_clkdev(clk, NULL, "d0500000.cam3"); 1006 clk_register_clkdev(clk, NULL, "d0500000.cam3");