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* driver/mtd:IFC NAND:Initialise internal SRAM before any writePrabhakar Kushwaha2012-09-27
| | | | | | | | | | | | | | | | IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for SRAM i.e. "byte select" is not supported. Hence Read Modify Write is implemented in IFC for any "system side write" into sram buffer. Reading an uninitialized memory results in ECC Error from sram wrapper. Hence we must initialize/prefill SRAM buffer by any data before writing anything in SRAM from system side. To initialize SRAM user can use "READID" NAND command with read bytes equal to SRAM size. It will be a one time activity post boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/fsl-pci: use 'Header Type' to identify PCIE modeMinghuan Lian2012-09-27
| | | | | | | | | | | | | | The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, some latest silicons do not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so change code to use 'Header Type' field to judge PCIE mode. Because FSL PCI controller does not support 'Header Type', patch still uses 'Programming Interface' to identify PCI mode. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/eeh: Don't release eeh_mutex in eeh_phb_pe_getAneesh Kumar K.V2012-09-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Acked-by: Gavin Shan <shangw@linux.vnet.ibm.com> ===================================== [ BUG: bad unlock balance detected! ] 3.6.0-rc5-00338-gcaa1d63-dirty #6 Not tainted ------------------------------------- swapper/0/1 is trying to release lock (eeh_mutex) at: [<c000000000058218>] .eeh_add_to_parent_pe+0x318/0x410 but there are no more locks to release! other info that might help us debug this: no locks held by swapper/0/1. stack backtrace: Call Trace: [c00000003e483870] [c000000000013310] .show_stack+0x70/0x1c0 (unreliable) [c00000003e483920] [c0000000000d8310] .print_unlock_inbalance_bug+0x110/0x120 [c00000003e4839b0] [c0000000000d9a50] .lock_release+0x1d0/0x240 [c00000003e483a60] [c000000000778064] .__mutex_unlock_slowpath+0xb4/0x250 [c00000003e483b10] [c000000000058218] .eeh_add_to_parent_pe+0x318/0x410 [c00000003e483bc0] [c00000000005a118] .pseries_eeh_of_probe+0x258/0x2f0 [c00000003e483cc0] [c000000000032528] .traverse_pci_devices+0xa8/0x150 [c00000003e483d70] [c000000000aa7288] .eeh_init+0xd4/0x140 [c00000003e483e00] [c00000000000abc4] .do_one_initcall+0x64/0x1e0 [c00000003e483ec0] [c000000000a90418] .kernel_init+0x1e8/0x2bc [c00000003e483f90] [c00000000002048c] .kernel_thread+0x54/0x70 EEH: PCI Enhanced I/O Error Handling Enabled Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Remove tlb batching hack for nighthawkMichael Ellerman2012-09-26
| | | | | | | | | | | | | | | | | | | | | In hpte_init_native() we call tlb_batching_enabled() to decide if we should setup ppc_md.flush_hash_range. tlb_batching_enabled() checks the _unflattened_ device tree, to see if we are running on a nighthawk. Since commit a223535 ("dont allow pSeries_probe to succeed without initialising MMU", Dec 2006), hpte_init_native() has been called from pSeries_probe() - at which point we have not yet unflattened the device tree. This means tlb_batching_enabled() will always return true, so the hack has effectively been disabled since Dec 2006. Ergo, I think we can drop it. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Set paca->data_offset = 0 for boot cpuMichael Ellerman2012-09-26
| | | | | | | | | | | | | | | | | | | | | | In commit 407821a we assigned a poison value to the paca->data_offset. Unfortunately with CONFIG_LOCK_STAT=y lockdep will read & write to percpu data very early in boot, prior to us initialising the percpu areas, leading to a crash. We have been getting away with this because the data_offset was previously set to zero. This causes lockdep to read & write to the initial copy of the percpu variables, which are discarded later in boot. Although that is "fishy", it does work, and for lock statistics it is no big deal to discard the counts from early boot. So set the paca->data_offset = 0 for the boot cpu paca only. Reported-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Tested-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/perf: Sample only if SIAR-Valid bit is set in P7+sukadev@linux.vnet.ibm.com2012-09-26
| | | | | | | | | | | | | | | | | | | | powerpc/perf: Sample only if SIAR-Valid bit is set in P7+ On POWER7+ two new bits (mmcra[35] and mmcra[36]) indicate whether the contents of SIAR and SDAR are valid. For marked instructions on P7+, we must save the contents of SIAR and SDAR registers only if these new bits are set. This code/check for the SIAR-Valid bit is specific to P7+, so rather than waste a CPU-feature bit use the PVR flag. Note that Carl Love proposed a similar change for oprofile: https://lkml.org/lkml/2012/6/22/309 Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Merge remote-tracking branch 'kumar/next' into nextBenjamin Herrenschmidt2012-09-26
|\ | | | | | | A few more fsl updates from Kumar
| * powerpc/fsl-pci: fix warning when CONFIG_SWIOTLB is disabledJia Hongtao2012-09-19
| | | | | | | | | | | | | | | | | | | | Fix the following warning: arch/powerpc/sysdev/fsl_pci.c: In function 'fsl_pci_probe': arch/powerpc/sysdev/fsl_pci.c:867:25: error: unused variable 'hose' Signed-off-by: Jia Hongtao <B38951@freescale.com> Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/mpc85xx: Update interrupt handling for IFC controllerPrabhakar Kushwaha2012-09-19
| | | | | | | | | | | | | | | | | | | | IFC may have one or two interrupts. If two interrupt specifiers are present, the first is the "common" interrupt (CM_EVTER_STAT), and the second is the NAND interrupt (NAND_EVTER_STAT). If there is only one, that interrupt reports both types of event. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Enable USB support in p1023rds_defconfigChunhe Lan2012-09-19
| | | | | | | | | | Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/smp: Do not disable IPI interrupts during suspendZhao Chenhui2012-09-19
| | | | | | | | | | | | | | | | | | | | | | During suspend, all interrupts including IPI will be disabled. In this case, the suspend process will hang in SMP. To prevent this, pass the flag IRQF_NO_SUSPEND when requesting IPI irq. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Merge remote-tracking branch 'agust/next' into nextBenjamin Herrenschmidt2012-09-26
|\ \ | |/ |/| | | mpc5xxx updates from Anatolij
| * powerpc/mpc52xx_lpbfifo: optionally defer fifo transfer startAnatolij Gustschin2012-09-14
| | | | | | | | | | | | | | | | | | | | Currently fifo transfer is started when submitting a transfer request. Add posibility to defer the fifo transfer and start it later by calling additional function. This change is backward compatible, the behaviour of mpc52xx_lpbfifo_submit() is the same for previous driver users, so there is no need to adapt them. Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * dt/misc: add bindings documentation for ifm camera sensor interfaceAnatolij Gustschin2012-09-14
| | | | | | | | | | | | | | | | IFM O2D cameras use special sensor bus interface glue-logic to connect camera sensors to mpc5200 LocalPlus bus. Add device tree bindings documentation for it. Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * powerpc/mpc5200: add dts files for ifm camera machinesAnatolij Gustschin2012-09-14
| | | | | | | | | | | | | | | | Add common o2d dtsi file to reuse it for other configurations. Add machine compatible string to mpc5200 simple platform file. Add dts files for O2D, O2I, O2MNT, O2DNT2, O2D300 and O3DNT boards. Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * powerpc: Option FB_FSL_DIU is not really optional for mpc512xPaul Gortmaker2012-09-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In powerpc randconfig builds, this keeps showing up: CC arch/powerpc/platforms/512x/mpc512x_shared.o arch/powerpc/platforms/512x/mpc512x_shared.c:70:9: warning: 'enum fsl_diu_monitor_port' declared inside parameter list arch/powerpc/platforms/512x/mpc512x_shared.c:70:9: warning: its scope is only this definition or declaration, which is probably not what you want arch/powerpc/platforms/512x/mpc512x_shared.c:69:56: error: parameter 1 ('port') has incomplete type arch/powerpc/platforms/512x/mpc512x_shared.c:69:5: warning: function declaration isn't a prototype arch/powerpc/platforms/512x/mpc512x_shared.c:84:9: warning: 'enum fsl_diu_monitor_port' declared inside parameter list arch/powerpc/platforms/512x/mpc512x_shared.c:83:56: error: parameter 1 ('port') has incomplete type arch/powerpc/platforms/512x/mpc512x_shared.c:83:6: warning: function declaration isn't a prototype arch/powerpc/platforms/512x/mpc512x_shared.c:88:36: warning: 'enum fsl_diu_monitor_port' declared inside parameter list arch/powerpc/platforms/512x/mpc512x_shared.c:88:57: error: parameter 1 ('port') has incomplete type arch/powerpc/platforms/512x/mpc512x_shared.c:88:6: warning: function declaration isn't a prototype arch/powerpc/platforms/512x/mpc512x_shared.c:187:54: error: parameter 1 ('port') has incomplete type arch/powerpc/platforms/512x/mpc512x_shared.c:187:1: error: return type is an incomplete type arch/powerpc/platforms/512x/mpc512x_shared.c:187:1: warning: function declaration isn't a prototype arch/powerpc/platforms/512x/mpc512x_shared.c: In function 'mpc512x_valid_monitor_port': arch/powerpc/platforms/512x/mpc512x_shared.c:189:9: error: 'FSL_DIU_PORT_DVI' undeclared (first use in this function) arch/powerpc/platforms/512x/mpc512x_shared.c:189:9: note: each undeclared identifier is reported only once for each function it appears in arch/powerpc/platforms/512x/mpc512x_shared.c:189:2: warning: 'return' with a value, in function returning void make[2]: *** [arch/powerpc/platforms/512x/mpc512x_shared.o] Error 1 The reason is that mpc512x_shared.c has a couple token #ifdef on FB_FSL_DIU/FB_FSL_DIU_MODULE, but they don't come close to masking all the DIU dependencies, as the above fail shows. Rather than sprinkle more pointless #ifdef in this file, just remove the existing two, and make FB_FSL_DIU part of the dependency. The mpc512x_defconfig already has the line "CONFIG_FB_FSL_DIU=y" so this change should be zero impact on real world configs. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * powerpc: 512x: Fix mpc5121_clk_get()Richard Weinberger2012-09-09
| | | | | | | | | | | | | | | | If try_module_get() fails, mpc5121_clk_get() might return a wrong clock. Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | Merge remote-tracking branch 'kumar/next' into nextBenjamin Herrenschmidt2012-09-18
|\ \
| * | powerpc/fsl-pci: Unify pci/pcie initialization codeJia Hongtao2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We unified the Freescale pci/pcie initialization by changing the fsl_pci to a platform driver. In previous PCI code architecture the initialization routine is called at board_setup_arch stage. Now the initialization is done in probe function which is architectural better. Also It's convenient for adding PM support for PCI controller in later patch. Now we registered pci controllers as platform devices. So we combine two initialization code as one platform driver. Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/pci: Use PCIe IP block revision register instead of compatibleRoy Zang2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale PCIe IP block revision bigger than rev2.2 will also need redefine the sequence of inbound windows. So change to use IP block revision instead of compatible for the judgment. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/pci: Add IP revision register define for Freescale PCIe controllerRoy Zang2012-09-12
| | | | | | | | | | | | | | | Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/p5040: fix dtb build warning of p5040ds.dtbShaohui Xie2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Device node adt7461 was wrongly added in p5040ds.dts, it should be added into i2c instead of localbus, when build p5040ds.dtb, a warning will dump: Warning (reg_format): "reg" property in /localbus@ffe124000/nand@2,0/adt7461@4c has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1) This was introduced by: commit ea6b1ba692bcb5f6e39f409a78cf8b04fdf23baa Author: Jia Hongtao <B38951@freescale.com> Date: Tue Aug 28 10:00:55 2012 +0800 powerpc: add adt7461 thermal monitor support to applicable boards Add thermal monitor support to following boards: P1022DS, MPC8536DS, P2041RDB, P3041DS, P4080DS, P5020DS, P5040DS Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/8544ds: add partition table for norflashWang Dongsheng2012-09-12
| | | | | | | | | | | | | | | | | | | | | create partition table for norflash. Signed-off-by: Wang Dongsheng <Dongsheng.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc: add adt7461 thermal monitor support to applicable boardsJia Hongtao2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add thermal monitor support to following boards: P1022DS, MPC8536DS, P2041RDB, P3041DS, P4080DS, P5020DS, P5040DS Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc85xx: Add new ext fields to Integrated FLash ControllerPrabhakar Kushwaha2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's Integrated Flash controller(IFC) v1.1.0 supports 40 bit address bus width. In case more than 32 bit address is used, the EXT registers should be set. Add support of ext registers. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc: Update Integrated Flash controller device tree bindingsPrabhakar Kushwaha2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's Integrated Flash controller (IFC) may have one or two interrupts. In case of single interrupt line, it will cover all IFC interrupts. Update this information in IFC device tree bindings Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/e5500: Add Power ISA properties to comply with ePAPR 1.1Olivia Yin2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | power-isa-version and power-isa-* are cpu node general properties defined in ePAPR. If the power-isa-version property exists, then for each category from the Categories section of Book I of the Power ISA version indicated, the existence of a property named power-isa-[CAT], where [CAT] is the abbreviated category name with all uppercase letters converted to lowercase, indicates that the category is supported by the implementation. This patch update all the e5500 platforms. Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/e500mc: Add Power ISA properties to comply with ePAPR 1.1Olivia Yin2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | power-isa-version and power-isa-* are cpu node general properties defined in ePAPR. If the power-isa-version property exists, then for each category from the Categories section of Book I of the Power ISA version indicated, the existence of a property named power-isa-[CAT], where [CAT] is the abbreviated category name with all uppercase letters converted to lowercase, indicates that the category is supported by the implementation. The patch update all the e500mc platforms. Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/e500v2: Add Power ISA properties to comply with ePAPR 1.1Olivia Yin2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | power-isa-version and power-isa-* are cpu node general properties defined in ePAPR. If the power-isa-version property exists, then for each category from the Categories section of Book I of the Power ISA version indicated, the existence of a property named power-isa-[CAT], where [CAT] is the abbreviated category name with all uppercase letters converted to lowercase, indicates that the category is supported by the implementation. The patch update all e500v2 platforms. Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpic: FSL MPIC error interrupt support.Varun Sethi2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All SOC device error interrupts are muxed and delivered to the core as a single MPIC error interrupt. Currently all the device drivers requiring access to device errors have to register for the MPIC error interrupt as a shared interrupt. With this patch we add interrupt demuxing capability in the mpic driver, allowing device drivers to register for their individual error interrupts. This is achieved by handling error interrupts in a cascaded fashion. MPIC error interrupt is handled by the "error_int_handler", which subsequently demuxes it using the EISR and delivers it to the respective drivers. The error interrupt capability is dependent on the MPIC EIMR register, which was introduced in FSL MPIC version 4.1 (P4080 rev2). So, error interrupt demuxing capability is dependent on the MPIC version and can be used for versions >= 4.1. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/swiotlb: Enable at early stage and disable if not necessaryJia Hongtao2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the dependency on PCI initialization for SWIOTLB initialization. So that PCI can be initialized at proper time. SWIOTLB is partly determined by PCI inbound/outbound map which is assigned in PCI initialization. But swiotlb_init() should be done at the stage of mem_init() which is much earlier than PCI initialization. So we reserve the memory for SWIOTLB first and free it if not necessary. All boards are converted to fit this change. Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Acked-by: Tony Breeds <tony@bakeyournoodle.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/booke: Add CPU_FTR_EMB_HV check for e5500.Varun Sethi2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | Added CPU_FTR_EMB_HV feature check for e5500. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/booke: Separate out restore_e5500/setup_e5500 routines.Varun Sethi2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the 64 bit case separate out e5500 cpu_setup and cpu_restore functions. The cpu_setup function (for the primary core) is passed the cpu_spec pointer, which is not there in case of the cpu_restore function. Also, in our case we will have to manipulate the CPU_FTR_EMB_HV flag on the primary core. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/booke: Merge the 32 bit e5500/e500mc cpu setup code.Varun Sethi2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge the 32 bit cpu setup code for e500mc/e5500 and define the "cpu_restore" routine (for e5500/e6500) only for the 64 bit case. The cpu_restore routine is used in the 64 bit case for setting up the secondary cores. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powepc/booke: Separate out E.HV check and ivor setup code.Varun Sethi2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | Move the E.HV check and CPU_FTR_EMB_HV flag manipulation to the cpu setup code. Create a separate routine for E.HV ivors setup. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: add HOTPLUG_CPU supportZhao Chenhui2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to disable and re-enable individual cores at runtime on MPC85xx/QorIQ SMP machines. Currently support e500v1/e500v2 core. MPC85xx machines use ePAPR spin-table in boot page for CPU kick-off. This patch uses the boot page from bootloader to boot core at runtime. It supports 32-bit and 36-bit physical address. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: implement hardware timebase syncZhao Chenhui2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do hardware timebase sync. Firstly, stop all timebases, and transfer the timebase value of the boot core to the other core. Finally, start all timebases. Only apply to dual-core chips, such as MPC8572, P2020, etc. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/smp: add generic_set_cpu_up() to set cpu_state as CPU_UP_PREPAREZhao Chenhui2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the case of cpu hotplug, the cpu_state should be set to CPU_UP_PREPARE when kicking cpu. Otherwise, the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(), which makes the delay in generic_cpu_die() not happen. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Replace epapr spin table macros/defines with a structZhao Chenhui2012-09-12
| | | | | | | | | | | | | | | Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpic: finish supporting timer group B on Freescale chipsVarun Sethi2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, these interrupts would be mapped, but the offset calculation was broken, and only the first group was initialized. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: introduce support for the Freescale / iVeia P1022RDKTimur Tabi2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale / iVeia P1022RDK reference board is a small-factor board with a Freescale P1022 SOC. It includes: 1) 512 MB 64-bit DDR3-800 (max) memory 2) 8MB SPI serial flash memory for boot loader 3) Bootable 4-bit SD/MMC port 4) Two 10/100/1000 Ethernet connectors 5) One SATA port 6) Two USB ports 7) One PCIe x4 slot 8) DVI video connector 9) Audio input and output jacks, powered by a Wolfson WM8960 codec. Unlike the P1022DS, the P1022RDK does not have any localbus devices, presumably because of the localbus / DIU multiplexing restriction of the P1022 SOC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Add support for P5040DS boardTimur Tabi2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Freescale P5040DS Reference Board ("Superhydra"), which is similar to the P5020DS. Features of the P5040 are listed below, but not all of these features (e.g. DPAA networking) are currently supported. Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: add Freescale P5040 SOC and SEC v5.2 device treesKim Phillips2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree (dtsi) files for the Freescale P5040 SOC. Since this SOC introduces SEC v5.2, add the dtsi file for that also. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/fsl-pci: add fsl,qoriq-pcie-v2.4 compatible stringTimur Tabi2012-09-12
| | | | | | | | | | | | | | | | | | | | | The PCI controller on the Freescale P5040 is v2.4. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: remove P1020RDB and P2020RDB CAMP device treesTimur Tabi2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We only need two examples of CAMP device trees in the upstream kernel. Co-operative Asymmetric Multi-Processing (CAMP) is a technique where two or more operating systems (typically multiple copies of the same Linux kernel) are loaded into memory, and each kernel is given a subset of the available cores to execute on. For example, on a four-core system, one kernel runs on cores 0 and 1, and the other runs on cores 2 and 3. The devices are also partitioned among the operating systems, and this is done with customized device trees. Each kernel gets its own device tree that has only the devices that it should know about. Unfortunately, this approach is very hackish. The kernels are trusted to only access devices in their respective device trees, and the partitioning only works for devices that can be handled. Crafting the device trees is a tricky process, and getting U-Boot to load and start all kernels is cumbersome. But most importantly, each CAMP setup is very application-specific, since the actual partitioning of resources is done in the DTS by the system designer. Therefore, it doesn't make a lot of sense to have a lot of CAMP device trees, since we only expect them to be used as examples. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: L2sram - Add compatible string to the device id listTang Yuantian2012-09-12
| | | | | | | | | | | | | | | | | | | | | | | | The following platforms are supported: mpc8544, mpc8572, mpc8536, p1021, p1025, p1024, p1010. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | powerpc/eeh: Fix crash on converting OF node to edevGavin Shan2012-09-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel crash was reported by Alexy. He was testing some feature with private kernel, in which Alexy added some code in pci_pm_reset() to read the CSR after writting it. The bug could be reproduced on Fiber Channel card (Fibre Channel: Emulex Corporation Saturn-X: LightPulse Fibre Channel Host Adapter (rev 03)) by the following commands. # echo 1 > /sys/devices/pci0004:01/0004:01:00.0/reset # rmmod lpfc # modprobe lpfc The history behind the test case is that those additional config space reading operations in pci_pm_reset() would cause EEH error, but we didn't detect EEH error until "modprobe lpfc". For the case, all the PCI devices on PCI bus (0004:01) were removed and added after PE reset. Then the EEH devices would be figured out again based on the OF nodes. Unfortunately, there were some child OF nodes under PCI device (0004:01:00.0), but they didn't have attached PCI_DN since they're invisible from PCI domain. However, we were still trying to convert OF node to EEH device without checking on the attached PCI_DN. Eventually, it caused the kernel crash as follows: Unable to handle kernel paging request for data at address 0x00000030 Faulting instruction address: 0xc00000000004d888 cpu 0x0: Vector: 300 (Data Access) at [c000000fc797b950] pc: c00000000004d888: .eeh_add_device_tree_early+0x78/0x140 lr: c00000000004d880: .eeh_add_device_tree_early+0x70/0x140 sp: c000000fc797bbd0 msr: 8000000000009032 dar: 30 dsisr: 40000000 current = 0xc000000fc78d9f70 paca = 0xc00000000edb0000 softe: 0 irq_happened: 0x00 pid = 2951, comm = eehd enter ? for help [c000000fc797bc50] c00000000004d848 .eeh_add_device_tree_early+0x38/0x140 [c000000fc797bcd0] c00000000004d848 .eeh_add_device_tree_early+0x38/0x140 [c000000fc797bd50] c000000000051b54 .pcibios_add_pci_devices+0x34/0x190 [c000000fc797bde0] c00000000004fb10 .eeh_reset_device+0x100/0x160 [c000000fc797be70] c0000000000502dc .eeh_handle_event+0x19c/0x300 [c000000fc797bf00] c000000000050570 .eeh_event_handler+0x130/0x1a0 [c000000fc797bf90] c000000000020138 .kernel_thread+0x54/0x70 The patch changes of_node_to_eeh_dev() and just returns NULL if the passed OF node doesn't have attached PCI_DN. Cc: stable@vger.kernel.org Reported-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | | powerpc/eeh: Lock module while handling EEH eventGavin Shan2012-09-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EEH core is talking with the PCI device driver to determine the action (purely reset, or PCI device removal). During the period, the driver might be unloaded and in turn causes kernel crash as follows: EEH: Detected PCI bus error on PHB#4-PE#10000 EEH: This PCI device has failed 3 times in the last hour lpfc 0004:01:00.0: 0:2710 PCI channel disable preparing for reset Unable to handle kernel paging request for data at address 0x00000490 Faulting instruction address: 0xd00000000e682c90 cpu 0x1: Vector: 300 (Data Access) at [c000000fc75ffa20] pc: d00000000e682c90: .lpfc_io_error_detected+0x30/0x240 [lpfc] lr: d00000000e682c8c: .lpfc_io_error_detected+0x2c/0x240 [lpfc] sp: c000000fc75ffca0 msr: 8000000000009032 dar: 490 dsisr: 40000000 current = 0xc000000fc79b88b0 paca = 0xc00000000edb0380 softe: 0 irq_happened: 0x00 pid = 3386, comm = eehd enter ? for help [c000000fc75ffca0] c000000fc75ffd30 (unreliable) [c000000fc75ffd30] c00000000004fd3c .eeh_report_error+0x7c/0xf0 [c000000fc75ffdc0] c00000000004ee00 .eeh_pe_dev_traverse+0xa0/0x180 [c000000fc75ffe70] c00000000004ffd8 .eeh_handle_event+0x68/0x300 [c000000fc75fff00] c0000000000503a0 .eeh_event_handler+0x130/0x1a0 [c000000fc75fff90] c000000000020138 .kernel_thread+0x54/0x70 1:mon> The patch increases the reference of the corresponding driver modules while EEH core does the negotiation with PCI device driver so that the corresponding driver modules can't be unloaded during the period and we're safe to refer the callbacks. Cc: stable@vger.kernel.org Reported-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | | powerpc/kprobe: Don't emulate store when kprobe stwu r1Tiejun Chen2012-09-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't do the real store operation for kprobing 'stwu Rx,(y)R1' since this may corrupt the exception frame, now we will do this operation safely in exception return code after migrate current exception frame below the kprobed function stack. So we only update gpr[1] here and trigger a thread flag to mask this. Note we should make sure if we trigger kernel stack over flow. Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* | | powerpc/kprobe: Complete kprobe and migrate exception frameTiejun Chen2012-09-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can't emulate stwu since that may corrupt current exception stack. So we will have to do real store operation in the exception return code. Firstly we'll allocate a trampoline exception frame below the kprobed function stack and copy the current exception frame to the trampoline. Then we can do this real store operation to implement 'stwu', and reroute the trampoline frame to r1 to complete this exception migration. Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-11 23:32:34 -0400