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* power: reset: driver for the Versatile syscon rebootLinus Walleij2014-09-25
| | | | | | | | | | | | | | | | | | | This driver enabled us to drive the reboot of the Versatile family of ARM reference boards. Even though only the RealView boards are supported initially, these boards all have the same procedure for reboot: - Write a magic value into an unlocking register - Write another magic value into a reset control register The driver will be reusable for Versatile and possibly also the Integrator family of reference boards. Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Acked-By: Sebastian Reichel <sre@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* leds: add a driver for syscon-based LEDsLinus Walleij2014-09-25
| | | | | | | | | | | | | | This makes it possible to create a set of LEDs from a syscon MFD instance, which is lean mean and clean on the ARM reference designs and can replace the Versatile LEDs driver in the long run, as well as other custom syscon LEDs drivers. Cc: Bryan Wu <cooloney@gmail.com> Cc: Richard Purdie <rpurdie@rpsys.net> [Fixed cocinelle warnings] Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Merge tag 'intc-part2-for-v3.18' of ↵Arnd Bergmann2014-09-25
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers Merge "part 2 of omap intc changes" from Tony Lindgren: Second part of omap intc interrupt controller changes to move it to drivers. Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'intc-part2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: irqchip: omap-intc: remove unnecessary comments irqchip: omap-intc: correct maximum number or MIR registers irqchip: omap-intc: enable TURBO idle mode irqchip: omap-intc: enable IP protection irqchip: omap-intc: remove unnecesary of_address_to_resource() call irqchip: omap-intc: comment style cleanup irqchip: omap-intc: minor improvement to omap_irq_pending() arm: omap: irq: move irq.c to drivers/irqchip/ irqchip: add irq-omap-intc.h header arm: omap2: n8x0: move i2c devices to DT
| * irqchip: omap-intc: remove unnecessary commentsFelipe Balbi2014-09-16
| | | | | | | | | | | | | | | | no fuctional changes. Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * irqchip: omap-intc: correct maximum number or MIR registersFelipe Balbi2014-09-16
| | | | | | | | | | | | | | | | | | maximum number of MIR register is 4, rather than 3. Fix that. Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * irqchip: omap-intc: enable TURBO idle modeFelipe Balbi2014-09-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When TURBO bit is set in the INTC_IDLE register, the input synchronizer clock will be autogated based on activity on the INTC. Because this idle mode increases the interrupt latency by 2 clock cycles, we're only enabling it during suspend. Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * irqchip: omap-intc: enable IP protectionFelipe Balbi2014-09-16
| | | | | | | | | | | | | | | | | | | | When PROTECTION bit in enabled in PROTECTION register, INTC's registers are only accessible from privileged mode. Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * irqchip: omap-intc: remove unnecesary of_address_to_resource() callFelipe Balbi2014-09-16
| | | | | | | | | | | | | | | | | | | | | | of_iomap(), which is called from omap_init_irq_of(), already takes care of making sure we have a valid resource to deal with. Because of that, we can safely remove our explicit call to of_address_to_resource(). Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * irqchip: omap-intc: comment style cleanupFelipe Balbi2014-09-16
| | | | | | | | | | | | | | | | | | no functional changes, just making sure comment follows Coding Style. Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * irqchip: omap-intc: minor improvement to omap_irq_pending()Felipe Balbi2014-09-16
| | | | | | | | | | | | | | | | | | We already hold the number of Pending registers in omap_nr_pending. Let's use that instead. Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * arm: omap: irq: move irq.c to drivers/irqchip/Felipe Balbi2014-09-16
| | | | | | | | | | | | | | | | Just move the code over as it has no dependencies on arch/arm/ anymore. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * irqchip: add irq-omap-intc.h headerFelipe Balbi2014-09-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP INTC irqchip driver will be moved under drivers/irqchip/ soon but we still have a dependency with mach-omap2 when it comes to idle functions. In order to make it easy to share those function prototypes with OMAP PM code, we introduce this new header. To avoid modifying several board-files and some of the PM-related code, we just include the new header from common.h which was already included by all users of IRQ-related PM code. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * arm: omap2: n8x0: move i2c devices to DTFelipe Balbi2014-09-16
| | | | | | | | | | | | | | | | | | | | | | By moving i2c devices to DT we can clean up i2c_board_info and fix a problem with moving INTC to irq domain where IRQs can be renumbered on each boot. Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | Merge tag 'sunxi-drivers-for-3.18' of ↵Arnd Bergmann2014-09-25
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/drivers Pull "Allwinner drivers additions for 3.18" from Maxime Ripard: Nothing major, just handling the RTC driver changes needed for the A31/A23. Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'sunxi-drivers-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: rtc: sunxi: Depend on platforms sun4i/sun7i that actually have the rtc rtc: sun6i: Add sun6i RTC driver
| * | rtc: sunxi: Depend on platforms sun4i/sun7i that actually have the rtcChen-Yu Tsai2014-09-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have Kconfig options for individual sunxi platforms, let the rtc-sunxi driver depend on the platforms that actually have this hardware, sun4i and sun7i. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | rtc: sun6i: Add sun6i RTC driverChen-Yu Tsai2014-09-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the driver for the RTC in the Allwinner A31 and A23 SoCs. Unlike the RTC found in A10/A20 SoCs, which was part of the timer, the RTC in A31/A23 are a separate hardware block, which also contain a few controls for the RTC block hardware (a regulator and RTC block GPIO pin latches), while also having separate interrupts for the alarms. The hardware is different enough to make a different driver for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Varka Bhadram <varkabhadram@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | | drivers/soc: ti: fix build break with modulesOlof Johansson2014-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes below build break by not switching to stubs when the driver is a module: drivers/soc/ti/knav_dma.c:418:7: error: redefinition of 'knav_dma_open_channel' void *knav_dma_open_channel(struct device *dev, const char *name, ^ In file included from drivers/soc/ti/knav_dma.c:26:0: include/linux/soc/ti/knav_dma.h:165:21: note: previous definition of 'knav_dma_open_channel' was here static inline void *knav_dma_open_channel(struct device *dev, const char *name, ^ Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* | | Merge tag 'drivers-soc-ti-v2' of ↵Olof Johansson2014-09-24
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/drivers Merge "soc: Keystone SOC Navigator drivers for 3.18" from Santosh Shilimkar: Keystone SOC Navigator drivers for 3.18 The Keystone Multi-core Navigator contains QMSS and packet DMA subsystems which interwork together to form the Navigator cloud used by various subsystems like NetCP, SRIO, SideBand Crypto engines etc. * tag 'drivers-soc-ti-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: MAINTAINERS: Add Keystone Multicore Navigator drivers entry soc: ti: add Keystone Navigator DMA support Documentation: dt: soc: add Keystone Navigator DMA bindings soc: ti: add Keystone Navigator QMSS driver Documentation: dt: soc: add Keystone Navigator QMSS bindings Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | MAINTAINERS: Add Keystone Multicore Navigator drivers entrySantosh Shilimkar2014-09-24
| | | | | | | | | | | | | | | | Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * | | soc: ti: add Keystone Navigator DMA supportSantosh Shilimkar2014-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Keystone Navigator DMA driver sets up the dma channels and flows for the QMSS(Queue Manager SubSystem) who triggers the actual data movements across clients using destination queues. Every client modules like NETCP(Network Coprocessor), SRIO(Serial Rapid IO) and CRYPTO Engines has its own instance of packet dma hardware. QMSS has also an internal packet DMA module which is used as an infrastructure DMA with zero copy. Initially this driver was proposed as DMA engine driver but since the hardware is not typical DMA engine and hence doesn't comply with typical DMA engine driver needs, that approach was naked. Link to that discussion - https://lkml.org/lkml/2014/3/18/340 As aligned, now we pair the Navigator DMA with its companion Navigator QMSS subsystem driver. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * | | Documentation: dt: soc: add Keystone Navigator DMA bindingsSantosh Shilimkar2014-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Keystone Navigator DMA driver sets up the dma channels and flows for the QMSS(Queue Manager SubSystem) who triggers the actual data movements across clients using destination queues. Every client modules like NETCP(Network Coprocessor), SRIO(Serial Rapid IO) and CRYPTO Engines has its own instance of packet dma hardware. QMSS has also an internal packet DMA module which is used as an infrastructure DMA with zero copy. Initially this driver was proposed as DMA engine driver but since the hardware is not typical DMA engine and hence doesn't comply with typical DMA engine driver needs, that approach was naked. Link to that discussion - https://lkml.org/lkml/2014/3/18/340 As aligned, now we pair the Navigator DMA with its companion Navigator QMSS subsystem driver. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * | | soc: ti: add Keystone Navigator QMSS driverSandeep Nair2014-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of the main hardware sub system which forms the backbone of the Keystone Multi-core Navigator. QMSS consist of queue managers, packed-data structure processors(PDSP), linking RAM, descriptor pools and infrastructure Packet DMA. The Queue Manager is a hardware module that is responsible for accelerating management of the packet queues. Packets are queued/de-queued by writing or reading descriptor address to a particular memory mapped location. The PDSPs perform QMSS related functions like accumulation, QoS, or event management. Linking RAM registers are used to link the descriptors which are stored in descriptor RAM. Descriptor RAM is configurable as internal or external memory. The QMSS driver manages the PDSP setups, linking RAM regions, queue pool management (allocation, push, pop and notify) and descriptor pool management. The specifics on the device tree bindings for QMSS can be found in: Documentation/devicetree/bindings/soc/keystone-navigator-qmss.txt Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * | | Documentation: dt: soc: add Keystone Navigator QMSS bindingsSandeep Nair2014-09-24
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of the main hardware sub system which forms the backbone of the Keystone Multi-core Navigator. QMSS consist of queue managers, packed-data structure processors(PDSP), linking RAM, descriptor pools and infrastructure Packet DMA. The Queue Manager is a hardware module that is responsible for accelerating management of the packet queues. Packets are queued/de-queued by writing or reading descriptor address to a particular memory mapped location. The PDSPs perform QMSS related functions like accumulation, QoS, or event management. Linking RAM registers are used to link the descriptors which are stored in descriptor RAM. Descriptor RAM is configurable as internal or external memory. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* | | Merge tag 'mailbox-for-v3.18' of ↵Olof Johansson2014-09-24
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers Mailbox related changes for omaps to get it to work with device tree. * tag 'mailbox-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: mailbox/omap: add support for parsing dt devices Documentation: dt: add omap mailbox bindings Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | mailbox/omap: add support for parsing dt devicesSuman Anna2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Logic has been added to the OMAP2+ mailbox code to parse the mailbox dt nodes and construct the different sub-mailboxes associated with the instance. The DT representation of the sub-mailbox devices is different from legacy platform data representation to allow flexibility of interrupt configuration between Tx and Rx fifos (to also possibly allow simplex devices in the future). The DT representation gathers similar information that was being passed previously through the platform data, except for the interrupt type information, which is gathered through driver compatible match data. The non-DT support has to be maintained for now to not break OMAP3 legacy boot, and the legacy-style code will be cleaned up once OMAP3 is also converted to DT-boot only. Cc: Jassi Brar <jassisinghbrar@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | Documentation: dt: add omap mailbox bindingsSuman Anna2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree bindings document for OMAP2+ mailbox. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | | Merge tag 'intc-for-v3.18' of ↵Olof Johansson2014-09-24
|\ \ \ \ | | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers Merge "omap intc changes for v3.18 merge window" from Tony Lindgren: Interrupt code related clean-up for omap2 and 3 to make it ready to move to drivers/irqchip. Note that this series does not yet move the interrupt code to drivers, that will be posted separately as a follow-up series. Note that this branch has a dependency to patches both in fixes-v3.18-not-urgent and soc-for-v3.18 and is based on a merge. Without doing the merge, off-idle would not work properly for git bisect. * tag 'intc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (325 commits) arm: omap: intc: switch over to linear irq domain arm: omap: irq: get rid of ifdef hack arm: omap: irq: introduce omap_nr_pending arm: omap: irq: remove nr_irqs argument arm: omap: irq: remove unnecessary header arm: omap: irq: drop omap2_intc_handle_irq() arm: omap: irq: drop omap3_intc_handle_irq() arm: omap: irq: call set_handle_irq() from .init_irq arm: omap: irq: move some more code around arm: boot: dts: omap2/3/am33xx: drop ti,intc-size arm: omap: irq: drop ti,intc-size support arm: boot: dts: am33xx/omap3: fix intc compatible flag arm: omap: irq: use compatible flag to figure out number of IRQ lines arm: omap: irq: add specific compatibles for omap3 and am33xx devices arm: omap: irq: drop .handle_irq and .init_irq fields arm: omap: irq: use IRQCHIP_DECLARE macro arm: omap: irq: call set_handle_irq() from intc_of_init arm: omap: irq: make intc_of_init static arm: omap: irq: reorganize code a little bit arm: omap: irq: always define omap3 support ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | arm: omap: intc: switch over to linear irq domainFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | now that we don't need to support legacy board-files, we can completely switch over to a linear irq domain and make use of irq_alloc_domain_generic_chips() to allocate all generic irq chips for us. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: get rid of ifdef hackFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | we don't need the ifdef if we have omap_nr_pending telling us how many pending registers we have on current platform. This solves a possible problem where we could try to handle bogus interrupts on OMAP2 and OMAP3 if using single zImage kernel, because we would end up reading the following pending FIQ register. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: introduce omap_nr_pendingFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | that variable will tell us how many INTC_PENDING_IRQn registers we have. It'll be used on a following patch to cleanup omap_intc_handle_irq() a bit. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: remove nr_irqs argumentFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | we can set our global omap_nr_irqs early on and drop the extra argument to omap_init_irq(). Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: remove unnecessary headerFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no need for that header to be included. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: drop omap2_intc_handle_irq()Felipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | that was just a no-op wrapper around omap_intc_handle_irq anyway. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: drop omap3_intc_handle_irq()Felipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | now that we're calling set_handle_irq() from init_irq(), we can safely drop all callers to omap3_intc_handle_irq() and its definition. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: call set_handle_irq() from .init_irqFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the idea is that board-files won't need to set .handle_irq on their machine_descs, which lets us drop a little more pointless code. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: move some more code aroundFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want .init_irq to call set_irq_handle() for legacy platforms. Note that this code will also be dropped once omap2/3 devices are completely moved to DT. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: boot: dts: omap2/3/am33xx: drop ti,intc-sizeFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | we are now infering number of IRQ lines based on correct compatible flag, which renders this binding completely useless. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: drop ti,intc-size supportFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | we don't need that anymore since specific devices are passing correct compatible flags. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: boot: dts: am33xx/omap3: fix intc compatible flagFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | that way, our intc driver can figure out how many IRQ lines INTC has. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: use compatible flag to figure out number of IRQ linesFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | so far, only am33xx has 128 lines, all other devices have only 96. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: add specific compatibles for omap3 and am33xx devicesFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | with this, we can use a compatible flag to figure out how many irq lines are wired up, no need for our TI-specific ti,intc-size binding. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: drop .handle_irq and .init_irq fieldsFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | now we can safely drop those fields from our machine_desc. While at that, also drop the now unused omap_intc_of_init() definition. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: use IRQCHIP_DECLARE macroFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IRQCHIP_DECLARE macro is used to declare the same of_device_id structure for irqchips, it's just a helper. No functional changes. Note that we're temporarily including irqchip.h with its full path, until we move this driver to drivers/irqchip/. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: call set_handle_irq() from intc_of_initFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this will let us drop .handle_irq and .init_irq fields from our generic machine_descs. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: make intc_of_init staticFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nobody uses that function outside of this file, so we don't need to expose it. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: reorganize code a little bitFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | no functional changes, just moving code around. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: always define omap3 supportFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | remove ifdef around omap3 INTC support. This will make it easier to reuse code for PM. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: rename omap3_intc_regsFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | just to make it clearer that it can be used on all omaps. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: remove unnecessary base_addr argumentFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | omap_intc_handle_irq now had an unnecessary base_addr argument. Let's remove it and fix all callers. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | arm: omap: irq: switch over to intc_readl on omap_intc_handle_irqFelipe Balbi2014-09-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | an almost blind conversion from readl_relaxed to our newly introduced intc_readl(). While at that, also remove some hardcoded register addresses. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 19:28:54 -0400