diff options
author | Felipe Balbi <balbi@ti.com> | 2014-09-08 20:54:42 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2014-09-11 16:03:41 -0400 |
commit | 131b48c061726d4ac98f70a2beae35280a8de5cf (patch) | |
tree | 5350ba61194a405753be8fdc0e4e74b0d2a96382 | |
parent | f8cc9eaf26dc026f134996a0cc6e1d1ce157ce9c (diff) |
arm: omap: irq: reorganize code a little bit
no functional changes, just moving code around.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r-- | arch/arm/mach-omap2/irq.c | 133 |
1 files changed, 66 insertions, 67 deletions
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 4e8705d3d8d8..480a9a7c8445 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c | |||
@@ -57,10 +57,6 @@ | |||
57 | * for each bank.. when in doubt, consult the TRM. | 57 | * for each bank.. when in doubt, consult the TRM. |
58 | */ | 58 | */ |
59 | 59 | ||
60 | static struct irq_domain *domain; | ||
61 | static void __iomem *omap_irq_base; | ||
62 | static int omap_nr_irqs = 96; | ||
63 | |||
64 | /* Structure to save interrupt controller context */ | 60 | /* Structure to save interrupt controller context */ |
65 | struct omap_intc_regs { | 61 | struct omap_intc_regs { |
66 | u32 sysconfig; | 62 | u32 sysconfig; |
@@ -70,6 +66,11 @@ struct omap_intc_regs { | |||
70 | u32 ilr[INTCPS_NR_ILR_REGS]; | 66 | u32 ilr[INTCPS_NR_ILR_REGS]; |
71 | u32 mir[INTCPS_NR_MIR_REGS]; | 67 | u32 mir[INTCPS_NR_MIR_REGS]; |
72 | }; | 68 | }; |
69 | static struct omap_intc_regs intc_context; | ||
70 | |||
71 | static struct irq_domain *domain; | ||
72 | static void __iomem *omap_irq_base; | ||
73 | static int omap_nr_irqs = 96; | ||
73 | 74 | ||
74 | /* INTC bank register get/set */ | 75 | /* INTC bank register get/set */ |
75 | static void intc_writel(u32 reg, u32 val) | 76 | static void intc_writel(u32 reg, u32 val) |
@@ -82,6 +83,61 @@ static u32 intc_readl(u32 reg) | |||
82 | return readl_relaxed(omap_irq_base + reg); | 83 | return readl_relaxed(omap_irq_base + reg); |
83 | } | 84 | } |
84 | 85 | ||
86 | void omap_intc_save_context(void) | ||
87 | { | ||
88 | int i; | ||
89 | |||
90 | intc_context.sysconfig = | ||
91 | intc_readl(INTC_SYSCONFIG); | ||
92 | intc_context.protection = | ||
93 | intc_readl(INTC_PROTECTION); | ||
94 | intc_context.idle = | ||
95 | intc_readl(INTC_IDLE); | ||
96 | intc_context.threshold = | ||
97 | intc_readl(INTC_THRESHOLD); | ||
98 | |||
99 | for (i = 0; i < omap_nr_irqs; i++) | ||
100 | intc_context.ilr[i] = | ||
101 | intc_readl((INTC_ILR0 + 0x4 * i)); | ||
102 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | ||
103 | intc_context.mir[i] = | ||
104 | intc_readl(INTC_MIR0 + (0x20 * i)); | ||
105 | } | ||
106 | |||
107 | void omap_intc_restore_context(void) | ||
108 | { | ||
109 | int i; | ||
110 | |||
111 | intc_writel(INTC_SYSCONFIG, intc_context.sysconfig); | ||
112 | intc_writel(INTC_PROTECTION, intc_context.protection); | ||
113 | intc_writel(INTC_IDLE, intc_context.idle); | ||
114 | intc_writel(INTC_THRESHOLD, intc_context.threshold); | ||
115 | |||
116 | for (i = 0; i < omap_nr_irqs; i++) | ||
117 | intc_writel(INTC_ILR0 + 0x4 * i, | ||
118 | intc_context.ilr[i]); | ||
119 | |||
120 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | ||
121 | intc_writel(INTC_MIR0 + 0x20 * i, | ||
122 | intc_context.mir[i]); | ||
123 | /* MIRs are saved and restore with other PRCM registers */ | ||
124 | } | ||
125 | |||
126 | void omap3_intc_prepare_idle(void) | ||
127 | { | ||
128 | /* | ||
129 | * Disable autoidle as it can stall interrupt controller, | ||
130 | * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) | ||
131 | */ | ||
132 | intc_writel(INTC_SYSCONFIG, 0); | ||
133 | } | ||
134 | |||
135 | void omap3_intc_resume_idle(void) | ||
136 | { | ||
137 | /* Re-enable autoidle */ | ||
138 | intc_writel(INTC_SYSCONFIG, 1); | ||
139 | } | ||
140 | |||
85 | /* XXX: FIQ and additional INTC support (only MPU at the moment) */ | 141 | /* XXX: FIQ and additional INTC support (only MPU at the moment) */ |
86 | static void omap_ack_irq(struct irq_data *d) | 142 | static void omap_ack_irq(struct irq_data *d) |
87 | { | 143 | { |
@@ -125,6 +181,12 @@ int omap_irq_pending(void) | |||
125 | return 0; | 181 | return 0; |
126 | } | 182 | } |
127 | 183 | ||
184 | void omap3_intc_suspend(void) | ||
185 | { | ||
186 | /* A pending interrupt would prevent OMAP from entering suspend */ | ||
187 | omap_ack_irq(NULL); | ||
188 | } | ||
189 | |||
128 | static __init void | 190 | static __init void |
129 | omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) | 191 | omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) |
130 | { | 192 | { |
@@ -265,69 +327,6 @@ void __init omap_intc_of_init(void) | |||
265 | of_irq_init(irq_match); | 327 | of_irq_init(irq_match); |
266 | } | 328 | } |
267 | 329 | ||
268 | static struct omap_intc_regs intc_context; | ||
269 | |||
270 | void omap_intc_save_context(void) | ||
271 | { | ||
272 | int i; | ||
273 | |||
274 | intc_context.sysconfig = | ||
275 | intc_readl(INTC_SYSCONFIG); | ||
276 | intc_context.protection = | ||
277 | intc_readl(INTC_PROTECTION); | ||
278 | intc_context.idle = | ||
279 | intc_readl(INTC_IDLE); | ||
280 | intc_context.threshold = | ||
281 | intc_readl(INTC_THRESHOLD); | ||
282 | |||
283 | for (i = 0; i < omap_nr_irqs; i++) | ||
284 | intc_context.ilr[i] = | ||
285 | intc_readl((INTC_ILR0 + 0x4 * i)); | ||
286 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | ||
287 | intc_context.mir[i] = | ||
288 | intc_readl(INTC_MIR0 + (0x20 * i)); | ||
289 | } | ||
290 | |||
291 | void omap_intc_restore_context(void) | ||
292 | { | ||
293 | int i; | ||
294 | |||
295 | intc_writel(INTC_SYSCONFIG, intc_context.sysconfig); | ||
296 | intc_writel(INTC_PROTECTION, intc_context.protection); | ||
297 | intc_writel(INTC_IDLE, intc_context.idle); | ||
298 | intc_writel(INTC_THRESHOLD, intc_context.threshold); | ||
299 | |||
300 | for (i = 0; i < omap_nr_irqs; i++) | ||
301 | intc_writel(INTC_ILR0 + 0x4 * i, | ||
302 | intc_context.ilr[i]); | ||
303 | |||
304 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | ||
305 | intc_writel(INTC_MIR0 + 0x20 * i, | ||
306 | intc_context.mir[i]); | ||
307 | /* MIRs are saved and restore with other PRCM registers */ | ||
308 | } | ||
309 | |||
310 | void omap3_intc_suspend(void) | ||
311 | { | ||
312 | /* A pending interrupt would prevent OMAP from entering suspend */ | ||
313 | omap_ack_irq(NULL); | ||
314 | } | ||
315 | |||
316 | void omap3_intc_prepare_idle(void) | ||
317 | { | ||
318 | /* | ||
319 | * Disable autoidle as it can stall interrupt controller, | ||
320 | * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) | ||
321 | */ | ||
322 | intc_writel(INTC_SYSCONFIG, 0); | ||
323 | } | ||
324 | |||
325 | void omap3_intc_resume_idle(void) | ||
326 | { | ||
327 | /* Re-enable autoidle */ | ||
328 | intc_writel(INTC_SYSCONFIG, 1); | ||
329 | } | ||
330 | |||
331 | asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs) | 330 | asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs) |
332 | { | 331 | { |
333 | omap_intc_handle_irq(regs); | 332 | omap_intc_handle_irq(regs); |