diff options
Diffstat (limited to 'sound/soc/davinci/davinci-mcasp.h')
-rw-r--r-- | sound/soc/davinci/davinci-mcasp.h | 304 |
1 files changed, 266 insertions, 38 deletions
diff --git a/sound/soc/davinci/davinci-mcasp.h b/sound/soc/davinci/davinci-mcasp.h index a2e27e1c32f3..8fed757d6087 100644 --- a/sound/soc/davinci/davinci-mcasp.h +++ b/sound/soc/davinci/davinci-mcasp.h | |||
@@ -18,43 +18,271 @@ | |||
18 | #ifndef DAVINCI_MCASP_H | 18 | #ifndef DAVINCI_MCASP_H |
19 | #define DAVINCI_MCASP_H | 19 | #define DAVINCI_MCASP_H |
20 | 20 | ||
21 | #include <linux/io.h> | 21 | /* |
22 | #include <linux/platform_data/davinci_asp.h> | 22 | * McASP register definitions |
23 | 23 | */ | |
24 | #include "davinci-pcm.h" | 24 | #define DAVINCI_MCASP_PID_REG 0x00 |
25 | 25 | #define DAVINCI_MCASP_PWREMUMGT_REG 0x04 | |
26 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 | 26 | |
27 | #define DAVINCI_MCASP_I2S_DAI 0 | 27 | #define DAVINCI_MCASP_PFUNC_REG 0x10 |
28 | #define DAVINCI_MCASP_DIT_DAI 1 | 28 | #define DAVINCI_MCASP_PDIR_REG 0x14 |
29 | 29 | #define DAVINCI_MCASP_PDOUT_REG 0x18 | |
30 | struct davinci_audio_dev { | 30 | #define DAVINCI_MCASP_PDSET_REG 0x1c |
31 | struct davinci_pcm_dma_params dma_params[2]; | 31 | |
32 | void __iomem *base; | 32 | #define DAVINCI_MCASP_PDCLR_REG 0x20 |
33 | struct device *dev; | 33 | |
34 | 34 | #define DAVINCI_MCASP_TLGC_REG 0x30 | |
35 | /* McASP specific data */ | 35 | #define DAVINCI_MCASP_TLMR_REG 0x34 |
36 | int tdm_slots; | 36 | |
37 | u8 op_mode; | 37 | #define DAVINCI_MCASP_GBLCTL_REG 0x44 |
38 | u8 num_serializer; | 38 | #define DAVINCI_MCASP_AMUTE_REG 0x48 |
39 | u8 *serial_dir; | 39 | #define DAVINCI_MCASP_LBCTL_REG 0x4c |
40 | u8 version; | 40 | |
41 | u16 bclk_lrclk_ratio; | 41 | #define DAVINCI_MCASP_TXDITCTL_REG 0x50 |
42 | 42 | ||
43 | /* McASP FIFO related */ | 43 | #define DAVINCI_MCASP_GBLCTLR_REG 0x60 |
44 | u8 txnumevt; | 44 | #define DAVINCI_MCASP_RXMASK_REG 0x64 |
45 | u8 rxnumevt; | 45 | #define DAVINCI_MCASP_RXFMT_REG 0x68 |
46 | 46 | #define DAVINCI_MCASP_RXFMCTL_REG 0x6c | |
47 | #ifdef CONFIG_PM_SLEEP | 47 | |
48 | struct { | 48 | #define DAVINCI_MCASP_ACLKRCTL_REG 0x70 |
49 | u32 txfmtctl; | 49 | #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74 |
50 | u32 rxfmtctl; | 50 | #define DAVINCI_MCASP_RXTDM_REG 0x78 |
51 | u32 txfmt; | 51 | #define DAVINCI_MCASP_EVTCTLR_REG 0x7c |
52 | u32 rxfmt; | 52 | |
53 | u32 aclkxctl; | 53 | #define DAVINCI_MCASP_RXSTAT_REG 0x80 |
54 | u32 aclkrctl; | 54 | #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84 |
55 | u32 pdir; | 55 | #define DAVINCI_MCASP_RXCLKCHK_REG 0x88 |
56 | } context; | 56 | #define DAVINCI_MCASP_REVTCTL_REG 0x8c |
57 | #endif | 57 | |
58 | }; | 58 | #define DAVINCI_MCASP_GBLCTLX_REG 0xa0 |
59 | #define DAVINCI_MCASP_TXMASK_REG 0xa4 | ||
60 | #define DAVINCI_MCASP_TXFMT_REG 0xa8 | ||
61 | #define DAVINCI_MCASP_TXFMCTL_REG 0xac | ||
62 | |||
63 | #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0 | ||
64 | #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4 | ||
65 | #define DAVINCI_MCASP_TXTDM_REG 0xb8 | ||
66 | #define DAVINCI_MCASP_EVTCTLX_REG 0xbc | ||
67 | |||
68 | #define DAVINCI_MCASP_TXSTAT_REG 0xc0 | ||
69 | #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4 | ||
70 | #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8 | ||
71 | #define DAVINCI_MCASP_XEVTCTL_REG 0xcc | ||
72 | |||
73 | /* Left(even TDM Slot) Channel Status Register File */ | ||
74 | #define DAVINCI_MCASP_DITCSRA_REG 0x100 | ||
75 | /* Right(odd TDM slot) Channel Status Register File */ | ||
76 | #define DAVINCI_MCASP_DITCSRB_REG 0x118 | ||
77 | /* Left(even TDM slot) User Data Register File */ | ||
78 | #define DAVINCI_MCASP_DITUDRA_REG 0x130 | ||
79 | /* Right(odd TDM Slot) User Data Register File */ | ||
80 | #define DAVINCI_MCASP_DITUDRB_REG 0x148 | ||
81 | |||
82 | /* Serializer n Control Register */ | ||
83 | #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180 | ||
84 | #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \ | ||
85 | (n << 2)) | ||
86 | |||
87 | /* Transmit Buffer for Serializer n */ | ||
88 | #define DAVINCI_MCASP_TXBUF_REG 0x200 | ||
89 | /* Receive Buffer for Serializer n */ | ||
90 | #define DAVINCI_MCASP_RXBUF_REG 0x280 | ||
91 | |||
92 | /* McASP FIFO Registers */ | ||
93 | #define DAVINCI_MCASP_V2_AFIFO_BASE (0x1010) | ||
94 | #define DAVINCI_MCASP_V3_AFIFO_BASE (0x1000) | ||
95 | |||
96 | /* FIFO register offsets from AFIFO base */ | ||
97 | #define MCASP_WFIFOCTL_OFFSET (0x0) | ||
98 | #define MCASP_WFIFOSTS_OFFSET (0x4) | ||
99 | #define MCASP_RFIFOCTL_OFFSET (0x8) | ||
100 | #define MCASP_RFIFOSTS_OFFSET (0xc) | ||
101 | |||
102 | /* | ||
103 | * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management | ||
104 | * Register Bits | ||
105 | */ | ||
106 | #define MCASP_FREE BIT(0) | ||
107 | #define MCASP_SOFT BIT(1) | ||
108 | |||
109 | /* | ||
110 | * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits | ||
111 | */ | ||
112 | #define AXR(n) (1<<n) | ||
113 | #define PFUNC_AMUTE BIT(25) | ||
114 | #define ACLKX BIT(26) | ||
115 | #define AHCLKX BIT(27) | ||
116 | #define AFSX BIT(28) | ||
117 | #define ACLKR BIT(29) | ||
118 | #define AHCLKR BIT(30) | ||
119 | #define AFSR BIT(31) | ||
120 | |||
121 | /* | ||
122 | * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits | ||
123 | */ | ||
124 | #define AXR(n) (1<<n) | ||
125 | #define PDIR_AMUTE BIT(25) | ||
126 | #define ACLKX BIT(26) | ||
127 | #define AHCLKX BIT(27) | ||
128 | #define AFSX BIT(28) | ||
129 | #define ACLKR BIT(29) | ||
130 | #define AHCLKR BIT(30) | ||
131 | #define AFSR BIT(31) | ||
132 | |||
133 | /* | ||
134 | * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits | ||
135 | */ | ||
136 | #define DITEN BIT(0) /* Transmit DIT mode enable/disable */ | ||
137 | #define VA BIT(2) | ||
138 | #define VB BIT(3) | ||
139 | |||
140 | /* | ||
141 | * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits | ||
142 | */ | ||
143 | #define TXROT(val) (val) | ||
144 | #define TXSEL BIT(3) | ||
145 | #define TXSSZ(val) (val<<4) | ||
146 | #define TXPBIT(val) (val<<8) | ||
147 | #define TXPAD(val) (val<<13) | ||
148 | #define TXORD BIT(15) | ||
149 | #define FSXDLY(val) (val<<16) | ||
150 | |||
151 | /* | ||
152 | * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits | ||
153 | */ | ||
154 | #define RXROT(val) (val) | ||
155 | #define RXSEL BIT(3) | ||
156 | #define RXSSZ(val) (val<<4) | ||
157 | #define RXPBIT(val) (val<<8) | ||
158 | #define RXPAD(val) (val<<13) | ||
159 | #define RXORD BIT(15) | ||
160 | #define FSRDLY(val) (val<<16) | ||
161 | |||
162 | /* | ||
163 | * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits | ||
164 | */ | ||
165 | #define FSXPOL BIT(0) | ||
166 | #define AFSXE BIT(1) | ||
167 | #define FSXDUR BIT(4) | ||
168 | #define FSXMOD(val) (val<<7) | ||
169 | |||
170 | /* | ||
171 | * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits | ||
172 | */ | ||
173 | #define FSRPOL BIT(0) | ||
174 | #define AFSRE BIT(1) | ||
175 | #define FSRDUR BIT(4) | ||
176 | #define FSRMOD(val) (val<<7) | ||
177 | |||
178 | /* | ||
179 | * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits | ||
180 | */ | ||
181 | #define ACLKXDIV(val) (val) | ||
182 | #define ACLKXE BIT(5) | ||
183 | #define TX_ASYNC BIT(6) | ||
184 | #define ACLKXPOL BIT(7) | ||
185 | #define ACLKXDIV_MASK 0x1f | ||
186 | |||
187 | /* | ||
188 | * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits | ||
189 | */ | ||
190 | #define ACLKRDIV(val) (val) | ||
191 | #define ACLKRE BIT(5) | ||
192 | #define RX_ASYNC BIT(6) | ||
193 | #define ACLKRPOL BIT(7) | ||
194 | #define ACLKRDIV_MASK 0x1f | ||
195 | |||
196 | /* | ||
197 | * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control | ||
198 | * Register Bits | ||
199 | */ | ||
200 | #define AHCLKXDIV(val) (val) | ||
201 | #define AHCLKXPOL BIT(14) | ||
202 | #define AHCLKXE BIT(15) | ||
203 | #define AHCLKXDIV_MASK 0xfff | ||
204 | |||
205 | /* | ||
206 | * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control | ||
207 | * Register Bits | ||
208 | */ | ||
209 | #define AHCLKRDIV(val) (val) | ||
210 | #define AHCLKRPOL BIT(14) | ||
211 | #define AHCLKRE BIT(15) | ||
212 | #define AHCLKRDIV_MASK 0xfff | ||
213 | |||
214 | /* | ||
215 | * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits | ||
216 | */ | ||
217 | #define MODE(val) (val) | ||
218 | #define DISMOD (val)(val<<2) | ||
219 | #define TXSTATE BIT(4) | ||
220 | #define RXSTATE BIT(5) | ||
221 | #define SRMOD_MASK 3 | ||
222 | #define SRMOD_INACTIVE 0 | ||
223 | |||
224 | /* | ||
225 | * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits | ||
226 | */ | ||
227 | #define LBEN BIT(0) | ||
228 | #define LBORD BIT(1) | ||
229 | #define LBGENMODE(val) (val<<2) | ||
230 | |||
231 | /* | ||
232 | * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration | ||
233 | */ | ||
234 | #define TXTDMS(n) (1<<n) | ||
235 | |||
236 | /* | ||
237 | * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration | ||
238 | */ | ||
239 | #define RXTDMS(n) (1<<n) | ||
240 | |||
241 | /* | ||
242 | * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits | ||
243 | */ | ||
244 | #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */ | ||
245 | #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */ | ||
246 | #define RXSERCLR BIT(2) /* Receiver Serializer Clear */ | ||
247 | #define RXSMRST BIT(3) /* Receiver State Machine Reset */ | ||
248 | #define RXFSRST BIT(4) /* Frame Sync Generator Reset */ | ||
249 | #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */ | ||
250 | #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/ | ||
251 | #define TXSERCLR BIT(10) /* Transmit Serializer Clear */ | ||
252 | #define TXSMRST BIT(11) /* Transmitter State Machine Reset */ | ||
253 | #define TXFSRST BIT(12) /* Frame Sync Generator Reset */ | ||
254 | |||
255 | /* | ||
256 | * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits | ||
257 | */ | ||
258 | #define MUTENA(val) (val) | ||
259 | #define MUTEINPOL BIT(2) | ||
260 | #define MUTEINENA BIT(3) | ||
261 | #define MUTEIN BIT(4) | ||
262 | #define MUTER BIT(5) | ||
263 | #define MUTEX BIT(6) | ||
264 | #define MUTEFSR BIT(7) | ||
265 | #define MUTEFSX BIT(8) | ||
266 | #define MUTEBADCLKR BIT(9) | ||
267 | #define MUTEBADCLKX BIT(10) | ||
268 | #define MUTERXDMAERR BIT(11) | ||
269 | #define MUTETXDMAERR BIT(12) | ||
270 | |||
271 | /* | ||
272 | * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits | ||
273 | */ | ||
274 | #define RXDATADMADIS BIT(0) | ||
275 | |||
276 | /* | ||
277 | * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits | ||
278 | */ | ||
279 | #define TXDATADMADIS BIT(0) | ||
280 | |||
281 | /* | ||
282 | * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits | ||
283 | */ | ||
284 | #define FIFO_ENABLE BIT(16) | ||
285 | #define NUMEVT_MASK (0xFF << 8) | ||
286 | #define NUMDMA_MASK (0xFF) | ||
59 | 287 | ||
60 | #endif /* DAVINCI_MCASP_H */ | 288 | #endif /* DAVINCI_MCASP_H */ |