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-rw-r--r--sound/soc/codecs/Kconfig8
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/rt5670-dsp.h54
-rw-r--r--sound/soc/codecs/rt5670.c2657
-rw-r--r--sound/soc/codecs/rt5670.h2000
-rw-r--r--sound/soc/codecs/rt5677.c272
-rw-r--r--sound/soc/codecs/rt5677.h15
7 files changed, 4812 insertions, 196 deletions
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 4c7542571484..a445b448d41d 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -80,6 +80,7 @@ config SND_SOC_ALL_CODECS
80 select SND_SOC_RT5640 if I2C 80 select SND_SOC_RT5640 if I2C
81 select SND_SOC_RT5645 if I2C 81 select SND_SOC_RT5645 if I2C
82 select SND_SOC_RT5651 if I2C 82 select SND_SOC_RT5651 if I2C
83 select SND_SOC_RT5670 if I2C
83 select SND_SOC_RT5677 if I2C 84 select SND_SOC_RT5677 if I2C
84 select SND_SOC_SGTL5000 if I2C 85 select SND_SOC_SGTL5000 if I2C
85 select SND_SOC_SI476X if MFD_SI476X_CORE 86 select SND_SOC_SI476X if MFD_SI476X_CORE
@@ -452,9 +453,13 @@ config SND_SOC_RL6231
452 default y if SND_SOC_RT5640=y 453 default y if SND_SOC_RT5640=y
453 default y if SND_SOC_RT5645=y 454 default y if SND_SOC_RT5645=y
454 default y if SND_SOC_RT5651=y 455 default y if SND_SOC_RT5651=y
456 default y if SND_SOC_RT5670=y
457 default y if SND_SOC_RT5677=y
455 default m if SND_SOC_RT5640=m 458 default m if SND_SOC_RT5640=m
456 default m if SND_SOC_RT5645=m 459 default m if SND_SOC_RT5645=m
457 default m if SND_SOC_RT5651=m 460 default m if SND_SOC_RT5651=m
461 default m if SND_SOC_RT5670=m
462 default m if SND_SOC_RT5677=m
458 463
459config SND_SOC_RT286 464config SND_SOC_RT286
460 tristate 465 tristate
@@ -471,6 +476,9 @@ config SND_SOC_RT5645
471config SND_SOC_RT5651 476config SND_SOC_RT5651
472 tristate 477 tristate
473 478
479config SND_SOC_RT5670
480 tristate
481
474config SND_SOC_RT5677 482config SND_SOC_RT5677
475 tristate 483 tristate
476 484
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index ade412e49bd0..a29da79a4359 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -74,6 +74,7 @@ snd-soc-rt5631-objs := rt5631.o
74snd-soc-rt5640-objs := rt5640.o 74snd-soc-rt5640-objs := rt5640.o
75snd-soc-rt5645-objs := rt5645.o 75snd-soc-rt5645-objs := rt5645.o
76snd-soc-rt5651-objs := rt5651.o 76snd-soc-rt5651-objs := rt5651.o
77snd-soc-rt5670-objs := rt5670.o
77snd-soc-rt5677-objs := rt5677.o 78snd-soc-rt5677-objs := rt5677.o
78snd-soc-sgtl5000-objs := sgtl5000.o 79snd-soc-sgtl5000-objs := sgtl5000.o
79snd-soc-alc5623-objs := alc5623.o 80snd-soc-alc5623-objs := alc5623.o
@@ -243,6 +244,7 @@ obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
243obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o 244obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
244obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o 245obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
245obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o 246obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o
247obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o
246obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o 248obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o
247obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o 249obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
248obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o 250obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o
diff --git a/sound/soc/codecs/rt5670-dsp.h b/sound/soc/codecs/rt5670-dsp.h
new file mode 100644
index 000000000000..a34d0cdb8198
--- /dev/null
+++ b/sound/soc/codecs/rt5670-dsp.h
@@ -0,0 +1,54 @@
1/*
2 * rt5670-dsp.h -- RT5670 ALSA SoC DSP driver
3 *
4 * Copyright 2014 Realtek Microelectronics
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5670_DSP_H__
13#define __RT5670_DSP_H__
14
15#define RT5670_DSP_CTRL1 0xe0
16#define RT5670_DSP_CTRL2 0xe1
17#define RT5670_DSP_CTRL3 0xe2
18#define RT5670_DSP_CTRL4 0xe3
19#define RT5670_DSP_CTRL5 0xe4
20
21/* DSP Control 1 (0xe0) */
22#define RT5670_DSP_CMD_MASK (0xff << 8)
23#define RT5670_DSP_CMD_PE (0x0d << 8) /* Patch Entry */
24#define RT5670_DSP_CMD_MW (0x3b << 8) /* Memory Write */
25#define RT5670_DSP_CMD_MR (0x37 << 8) /* Memory Read */
26#define RT5670_DSP_CMD_RR (0x60 << 8) /* Register Read */
27#define RT5670_DSP_CMD_RW (0x68 << 8) /* Register Write */
28#define RT5670_DSP_REG_DATHI (0x26 << 8) /* High Data Addr */
29#define RT5670_DSP_REG_DATLO (0x25 << 8) /* Low Data Addr */
30#define RT5670_DSP_CLK_MASK (0x3 << 6)
31#define RT5670_DSP_CLK_SFT 6
32#define RT5670_DSP_CLK_768K (0x0 << 6)
33#define RT5670_DSP_CLK_384K (0x1 << 6)
34#define RT5670_DSP_CLK_192K (0x2 << 6)
35#define RT5670_DSP_CLK_96K (0x3 << 6)
36#define RT5670_DSP_BUSY_MASK (0x1 << 5)
37#define RT5670_DSP_RW_MASK (0x1 << 4)
38#define RT5670_DSP_DL_MASK (0x3 << 2)
39#define RT5670_DSP_DL_0 (0x0 << 2)
40#define RT5670_DSP_DL_1 (0x1 << 2)
41#define RT5670_DSP_DL_2 (0x2 << 2)
42#define RT5670_DSP_DL_3 (0x3 << 2)
43#define RT5670_DSP_I2C_AL_16 (0x1 << 1)
44#define RT5670_DSP_CMD_EN (0x1)
45
46struct rt5670_dsp_param {
47 u16 cmd_fmt;
48 u16 addr;
49 u16 data;
50 u8 cmd;
51};
52
53#endif /* __RT5670_DSP_H__ */
54
diff --git a/sound/soc/codecs/rt5670.c b/sound/soc/codecs/rt5670.c
new file mode 100644
index 000000000000..ba9d9b4d4857
--- /dev/null
+++ b/sound/soc/codecs/rt5670.c
@@ -0,0 +1,2657 @@
1/*
2 * rt5670.c -- RT5670 ALSA SoC audio codec driver
3 *
4 * Copyright 2014 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/jack.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28#include <sound/rt5670.h>
29
30#include "rl6231.h"
31#include "rt5670.h"
32#include "rt5670-dsp.h"
33
34#define RT5670_DEVICE_ID 0x6271
35
36#define RT5670_PR_RANGE_BASE (0xff + 1)
37#define RT5670_PR_SPACING 0x100
38
39#define RT5670_PR_BASE (RT5670_PR_RANGE_BASE + (0 * RT5670_PR_SPACING))
40
41static const struct regmap_range_cfg rt5670_ranges[] = {
42 { .name = "PR", .range_min = RT5670_PR_BASE,
43 .range_max = RT5670_PR_BASE + 0xf8,
44 .selector_reg = RT5670_PRIV_INDEX,
45 .selector_mask = 0xff,
46 .selector_shift = 0x0,
47 .window_start = RT5670_PRIV_DATA,
48 .window_len = 0x1, },
49};
50
51static struct reg_default init_list[] = {
52 { RT5670_PR_BASE + 0x14, 0x9a8a },
53 { RT5670_PR_BASE + 0x38, 0x3ba1 },
54 { RT5670_PR_BASE + 0x3d, 0x3640 },
55};
56#define RT5670_INIT_REG_LEN ARRAY_SIZE(init_list)
57
58static const struct reg_default rt5670_reg[] = {
59 { 0x00, 0x0000 },
60 { 0x02, 0x8888 },
61 { 0x03, 0x8888 },
62 { 0x0a, 0x0001 },
63 { 0x0b, 0x0827 },
64 { 0x0c, 0x0000 },
65 { 0x0d, 0x0008 },
66 { 0x0e, 0x0000 },
67 { 0x0f, 0x0808 },
68 { 0x19, 0xafaf },
69 { 0x1a, 0xafaf },
70 { 0x1b, 0x0011 },
71 { 0x1c, 0x2f2f },
72 { 0x1d, 0x2f2f },
73 { 0x1e, 0x0000 },
74 { 0x1f, 0x2f2f },
75 { 0x20, 0x0000 },
76 { 0x26, 0x7860 },
77 { 0x27, 0x7860 },
78 { 0x28, 0x7871 },
79 { 0x29, 0x8080 },
80 { 0x2a, 0x5656 },
81 { 0x2b, 0x5454 },
82 { 0x2c, 0xaaa0 },
83 { 0x2d, 0x0000 },
84 { 0x2e, 0x2f2f },
85 { 0x2f, 0x1002 },
86 { 0x30, 0x0000 },
87 { 0x31, 0x5f00 },
88 { 0x32, 0x0000 },
89 { 0x33, 0x0000 },
90 { 0x34, 0x0000 },
91 { 0x35, 0x0000 },
92 { 0x36, 0x0000 },
93 { 0x37, 0x0000 },
94 { 0x38, 0x0000 },
95 { 0x3b, 0x0000 },
96 { 0x3c, 0x007f },
97 { 0x3d, 0x0000 },
98 { 0x3e, 0x007f },
99 { 0x45, 0xe00f },
100 { 0x4c, 0x5380 },
101 { 0x4f, 0x0073 },
102 { 0x52, 0x00d3 },
103 { 0x53, 0xf0f0 },
104 { 0x61, 0x0000 },
105 { 0x62, 0x0001 },
106 { 0x63, 0x00c3 },
107 { 0x64, 0x0000 },
108 { 0x65, 0x0000 },
109 { 0x66, 0x0000 },
110 { 0x6f, 0x8000 },
111 { 0x70, 0x8000 },
112 { 0x71, 0x8000 },
113 { 0x72, 0x8000 },
114 { 0x73, 0x1110 },
115 { 0x74, 0x0e00 },
116 { 0x75, 0x1505 },
117 { 0x76, 0x0015 },
118 { 0x77, 0x0c00 },
119 { 0x78, 0x4000 },
120 { 0x79, 0x0123 },
121 { 0x7f, 0x1100 },
122 { 0x80, 0x0000 },
123 { 0x81, 0x0000 },
124 { 0x82, 0x0000 },
125 { 0x83, 0x0000 },
126 { 0x84, 0x0000 },
127 { 0x85, 0x0000 },
128 { 0x86, 0x0008 },
129 { 0x87, 0x0000 },
130 { 0x88, 0x0000 },
131 { 0x89, 0x0000 },
132 { 0x8a, 0x0000 },
133 { 0x8b, 0x0000 },
134 { 0x8c, 0x0007 },
135 { 0x8d, 0x0000 },
136 { 0x8e, 0x0004 },
137 { 0x8f, 0x1100 },
138 { 0x90, 0x0646 },
139 { 0x91, 0x0c06 },
140 { 0x93, 0x0000 },
141 { 0x94, 0x0000 },
142 { 0x95, 0x0000 },
143 { 0x97, 0x0000 },
144 { 0x98, 0x0000 },
145 { 0x99, 0x0000 },
146 { 0x9a, 0x2184 },
147 { 0x9b, 0x010a },
148 { 0x9c, 0x0aea },
149 { 0x9d, 0x000c },
150 { 0x9e, 0x0400 },
151 { 0xae, 0x7000 },
152 { 0xaf, 0x0000 },
153 { 0xb0, 0x6000 },
154 { 0xb1, 0x0000 },
155 { 0xb2, 0x0000 },
156 { 0xb3, 0x001f },
157 { 0xb4, 0x2206 },
158 { 0xb5, 0x1f00 },
159 { 0xb6, 0x0000 },
160 { 0xb7, 0x0000 },
161 { 0xbb, 0x0000 },
162 { 0xbc, 0x0000 },
163 { 0xbd, 0x0000 },
164 { 0xbe, 0x0000 },
165 { 0xbf, 0x0000 },
166 { 0xc0, 0x0000 },
167 { 0xc1, 0x0000 },
168 { 0xc2, 0x0000 },
169 { 0xcd, 0x0000 },
170 { 0xce, 0x0000 },
171 { 0xcf, 0x1813 },
172 { 0xd0, 0x0690 },
173 { 0xd1, 0x1c17 },
174 { 0xd3, 0xb320 },
175 { 0xd4, 0x0000 },
176 { 0xd6, 0x0400 },
177 { 0xd9, 0x0809 },
178 { 0xda, 0x0000 },
179 { 0xdb, 0x0001 },
180 { 0xdc, 0x0049 },
181 { 0xdd, 0x0009 },
182 { 0xe6, 0x8000 },
183 { 0xe7, 0x0000 },
184 { 0xec, 0xb300 },
185 { 0xed, 0x0000 },
186 { 0xee, 0xb300 },
187 { 0xef, 0x0000 },
188 { 0xf8, 0x0000 },
189 { 0xf9, 0x0000 },
190 { 0xfa, 0x8010 },
191 { 0xfb, 0x0033 },
192 { 0xfc, 0x0080 },
193};
194
195static bool rt5670_volatile_register(struct device *dev, unsigned int reg)
196{
197 int i;
198
199 for (i = 0; i < ARRAY_SIZE(rt5670_ranges); i++) {
200 if ((reg >= rt5670_ranges[i].window_start &&
201 reg <= rt5670_ranges[i].window_start +
202 rt5670_ranges[i].window_len) ||
203 (reg >= rt5670_ranges[i].range_min &&
204 reg <= rt5670_ranges[i].range_max)) {
205 return true;
206 }
207 }
208
209 switch (reg) {
210 case RT5670_RESET:
211 case RT5670_PDM_DATA_CTRL1:
212 case RT5670_PDM1_DATA_CTRL4:
213 case RT5670_PDM2_DATA_CTRL4:
214 case RT5670_PRIV_DATA:
215 case RT5670_ASRC_5:
216 case RT5670_CJ_CTRL1:
217 case RT5670_CJ_CTRL2:
218 case RT5670_CJ_CTRL3:
219 case RT5670_A_JD_CTRL1:
220 case RT5670_A_JD_CTRL2:
221 case RT5670_VAD_CTRL5:
222 case RT5670_ADC_EQ_CTRL1:
223 case RT5670_EQ_CTRL1:
224 case RT5670_ALC_CTRL_1:
225 case RT5670_IRQ_CTRL1:
226 case RT5670_IRQ_CTRL2:
227 case RT5670_INT_IRQ_ST:
228 case RT5670_IL_CMD:
229 case RT5670_DSP_CTRL1:
230 case RT5670_DSP_CTRL2:
231 case RT5670_DSP_CTRL3:
232 case RT5670_DSP_CTRL4:
233 case RT5670_DSP_CTRL5:
234 case RT5670_VENDOR_ID:
235 case RT5670_VENDOR_ID1:
236 case RT5670_VENDOR_ID2:
237 return true;
238 default:
239 return false;
240 }
241}
242
243static bool rt5670_readable_register(struct device *dev, unsigned int reg)
244{
245 int i;
246
247 for (i = 0; i < ARRAY_SIZE(rt5670_ranges); i++) {
248 if ((reg >= rt5670_ranges[i].window_start &&
249 reg <= rt5670_ranges[i].window_start +
250 rt5670_ranges[i].window_len) ||
251 (reg >= rt5670_ranges[i].range_min &&
252 reg <= rt5670_ranges[i].range_max)) {
253 return true;
254 }
255 }
256
257 switch (reg) {
258 case RT5670_RESET:
259 case RT5670_HP_VOL:
260 case RT5670_LOUT1:
261 case RT5670_CJ_CTRL1:
262 case RT5670_CJ_CTRL2:
263 case RT5670_CJ_CTRL3:
264 case RT5670_IN2:
265 case RT5670_INL1_INR1_VOL:
266 case RT5670_DAC1_DIG_VOL:
267 case RT5670_DAC2_DIG_VOL:
268 case RT5670_DAC_CTRL:
269 case RT5670_STO1_ADC_DIG_VOL:
270 case RT5670_MONO_ADC_DIG_VOL:
271 case RT5670_STO2_ADC_DIG_VOL:
272 case RT5670_ADC_BST_VOL1:
273 case RT5670_ADC_BST_VOL2:
274 case RT5670_STO2_ADC_MIXER:
275 case RT5670_STO1_ADC_MIXER:
276 case RT5670_MONO_ADC_MIXER:
277 case RT5670_AD_DA_MIXER:
278 case RT5670_STO_DAC_MIXER:
279 case RT5670_DD_MIXER:
280 case RT5670_DIG_MIXER:
281 case RT5670_DSP_PATH1:
282 case RT5670_DSP_PATH2:
283 case RT5670_DIG_INF1_DATA:
284 case RT5670_DIG_INF2_DATA:
285 case RT5670_PDM_OUT_CTRL:
286 case RT5670_PDM_DATA_CTRL1:
287 case RT5670_PDM1_DATA_CTRL2:
288 case RT5670_PDM1_DATA_CTRL3:
289 case RT5670_PDM1_DATA_CTRL4:
290 case RT5670_PDM2_DATA_CTRL2:
291 case RT5670_PDM2_DATA_CTRL3:
292 case RT5670_PDM2_DATA_CTRL4:
293 case RT5670_REC_L1_MIXER:
294 case RT5670_REC_L2_MIXER:
295 case RT5670_REC_R1_MIXER:
296 case RT5670_REC_R2_MIXER:
297 case RT5670_HPO_MIXER:
298 case RT5670_MONO_MIXER:
299 case RT5670_OUT_L1_MIXER:
300 case RT5670_OUT_R1_MIXER:
301 case RT5670_LOUT_MIXER:
302 case RT5670_PWR_DIG1:
303 case RT5670_PWR_DIG2:
304 case RT5670_PWR_ANLG1:
305 case RT5670_PWR_ANLG2:
306 case RT5670_PWR_MIXER:
307 case RT5670_PWR_VOL:
308 case RT5670_PRIV_INDEX:
309 case RT5670_PRIV_DATA:
310 case RT5670_I2S4_SDP:
311 case RT5670_I2S1_SDP:
312 case RT5670_I2S2_SDP:
313 case RT5670_I2S3_SDP:
314 case RT5670_ADDA_CLK1:
315 case RT5670_ADDA_CLK2:
316 case RT5670_DMIC_CTRL1:
317 case RT5670_DMIC_CTRL2:
318 case RT5670_TDM_CTRL_1:
319 case RT5670_TDM_CTRL_2:
320 case RT5670_TDM_CTRL_3:
321 case RT5670_DSP_CLK:
322 case RT5670_GLB_CLK:
323 case RT5670_PLL_CTRL1:
324 case RT5670_PLL_CTRL2:
325 case RT5670_ASRC_1:
326 case RT5670_ASRC_2:
327 case RT5670_ASRC_3:
328 case RT5670_ASRC_4:
329 case RT5670_ASRC_5:
330 case RT5670_ASRC_7:
331 case RT5670_ASRC_8:
332 case RT5670_ASRC_9:
333 case RT5670_ASRC_10:
334 case RT5670_ASRC_11:
335 case RT5670_ASRC_12:
336 case RT5670_ASRC_13:
337 case RT5670_ASRC_14:
338 case RT5670_DEPOP_M1:
339 case RT5670_DEPOP_M2:
340 case RT5670_DEPOP_M3:
341 case RT5670_CHARGE_PUMP:
342 case RT5670_MICBIAS:
343 case RT5670_A_JD_CTRL1:
344 case RT5670_A_JD_CTRL2:
345 case RT5670_VAD_CTRL1:
346 case RT5670_VAD_CTRL2:
347 case RT5670_VAD_CTRL3:
348 case RT5670_VAD_CTRL4:
349 case RT5670_VAD_CTRL5:
350 case RT5670_ADC_EQ_CTRL1:
351 case RT5670_ADC_EQ_CTRL2:
352 case RT5670_EQ_CTRL1:
353 case RT5670_EQ_CTRL2:
354 case RT5670_ALC_DRC_CTRL1:
355 case RT5670_ALC_DRC_CTRL2:
356 case RT5670_ALC_CTRL_1:
357 case RT5670_ALC_CTRL_2:
358 case RT5670_ALC_CTRL_3:
359 case RT5670_JD_CTRL:
360 case RT5670_IRQ_CTRL1:
361 case RT5670_IRQ_CTRL2:
362 case RT5670_INT_IRQ_ST:
363 case RT5670_GPIO_CTRL1:
364 case RT5670_GPIO_CTRL2:
365 case RT5670_GPIO_CTRL3:
366 case RT5670_SCRABBLE_FUN:
367 case RT5670_SCRABBLE_CTRL:
368 case RT5670_BASE_BACK:
369 case RT5670_MP3_PLUS1:
370 case RT5670_MP3_PLUS2:
371 case RT5670_ADJ_HPF1:
372 case RT5670_ADJ_HPF2:
373 case RT5670_HP_CALIB_AMP_DET:
374 case RT5670_SV_ZCD1:
375 case RT5670_SV_ZCD2:
376 case RT5670_IL_CMD:
377 case RT5670_IL_CMD2:
378 case RT5670_IL_CMD3:
379 case RT5670_DRC_HL_CTRL1:
380 case RT5670_DRC_HL_CTRL2:
381 case RT5670_ADC_MONO_HP_CTRL1:
382 case RT5670_ADC_MONO_HP_CTRL2:
383 case RT5670_ADC_STO2_HP_CTRL1:
384 case RT5670_ADC_STO2_HP_CTRL2:
385 case RT5670_JD_CTRL3:
386 case RT5670_JD_CTRL4:
387 case RT5670_DIG_MISC:
388 case RT5670_DSP_CTRL1:
389 case RT5670_DSP_CTRL2:
390 case RT5670_DSP_CTRL3:
391 case RT5670_DSP_CTRL4:
392 case RT5670_DSP_CTRL5:
393 case RT5670_GEN_CTRL2:
394 case RT5670_GEN_CTRL3:
395 case RT5670_VENDOR_ID:
396 case RT5670_VENDOR_ID1:
397 case RT5670_VENDOR_ID2:
398 return true;
399 default:
400 return false;
401 }
402}
403
404static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
405static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
406static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
407static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
408static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
409
410/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
411static unsigned int bst_tlv[] = {
412 TLV_DB_RANGE_HEAD(7),
413 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
414 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
415 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
416 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
417 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
418 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
419 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
420};
421
422/* Interface data select */
423static const char * const rt5670_data_select[] = {
424 "Normal", "Swap", "left copy to right", "right copy to left"
425};
426
427static SOC_ENUM_SINGLE_DECL(rt5670_if2_dac_enum, RT5670_DIG_INF1_DATA,
428 RT5670_IF2_DAC_SEL_SFT, rt5670_data_select);
429
430static SOC_ENUM_SINGLE_DECL(rt5670_if2_adc_enum, RT5670_DIG_INF1_DATA,
431 RT5670_IF2_ADC_SEL_SFT, rt5670_data_select);
432
433static const struct snd_kcontrol_new rt5670_snd_controls[] = {
434 /* Headphone Output Volume */
435 SOC_DOUBLE("HP Playback Switch", RT5670_HP_VOL,
436 RT5670_L_MUTE_SFT, RT5670_R_MUTE_SFT, 1, 1),
437 SOC_DOUBLE_TLV("HP Playback Volume", RT5670_HP_VOL,
438 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
439 39, 0, out_vol_tlv),
440 /* OUTPUT Control */
441 SOC_DOUBLE("OUT Channel Switch", RT5670_LOUT1,
442 RT5670_VOL_L_SFT, RT5670_VOL_R_SFT, 1, 1),
443 SOC_DOUBLE_TLV("OUT Playback Volume", RT5670_LOUT1,
444 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT, 39, 1, out_vol_tlv),
445 /* DAC Digital Volume */
446 SOC_DOUBLE("DAC2 Playback Switch", RT5670_DAC_CTRL,
447 RT5670_M_DAC_L2_VOL_SFT, RT5670_M_DAC_R2_VOL_SFT, 1, 1),
448 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5670_DAC1_DIG_VOL,
449 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
450 175, 0, dac_vol_tlv),
451 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5670_DAC2_DIG_VOL,
452 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
453 175, 0, dac_vol_tlv),
454 /* IN1/IN2 Control */
455 SOC_SINGLE_TLV("IN1 Boost Volume", RT5670_CJ_CTRL1,
456 RT5670_BST_SFT1, 8, 0, bst_tlv),
457 SOC_SINGLE_TLV("IN2 Boost Volume", RT5670_IN2,
458 RT5670_BST_SFT1, 8, 0, bst_tlv),
459 /* INL/INR Volume Control */
460 SOC_DOUBLE_TLV("IN Capture Volume", RT5670_INL1_INR1_VOL,
461 RT5670_INL_VOL_SFT, RT5670_INR_VOL_SFT,
462 31, 1, in_vol_tlv),
463 /* ADC Digital Volume Control */
464 SOC_DOUBLE("ADC Capture Switch", RT5670_STO1_ADC_DIG_VOL,
465 RT5670_L_MUTE_SFT, RT5670_R_MUTE_SFT, 1, 1),
466 SOC_DOUBLE_TLV("ADC Capture Volume", RT5670_STO1_ADC_DIG_VOL,
467 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
468 127, 0, adc_vol_tlv),
469
470 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5670_MONO_ADC_DIG_VOL,
471 RT5670_L_VOL_SFT, RT5670_R_VOL_SFT,
472 127, 0, adc_vol_tlv),
473
474 /* ADC Boost Volume Control */
475 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5670_ADC_BST_VOL1,
476 RT5670_STO1_ADC_L_BST_SFT, RT5670_STO1_ADC_R_BST_SFT,
477 3, 0, adc_bst_tlv),
478
479 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5670_ADC_BST_VOL1,
480 RT5670_STO2_ADC_L_BST_SFT, RT5670_STO2_ADC_R_BST_SFT,
481 3, 0, adc_bst_tlv),
482
483 SOC_ENUM("ADC IF2 Data Switch", rt5670_if2_adc_enum),
484 SOC_ENUM("DAC IF2 Data Switch", rt5670_if2_dac_enum),
485};
486
487/**
488 * set_dmic_clk - Set parameter of dmic.
489 *
490 * @w: DAPM widget.
491 * @kcontrol: The kcontrol of this widget.
492 * @event: Event id.
493 *
494 * Choose dmic clock between 1MHz and 3MHz.
495 * It is better for clock to approximate 3MHz.
496 */
497static int set_dmic_clk(struct snd_soc_dapm_widget *w,
498 struct snd_kcontrol *kcontrol, int event)
499{
500 struct snd_soc_codec *codec = w->codec;
501 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
502 int idx = -EINVAL;
503
504 idx = rl6231_calc_dmic_clk(rt5670->sysclk);
505
506 if (idx < 0)
507 dev_err(codec->dev, "Failed to set DMIC clock\n");
508 else
509 snd_soc_update_bits(codec, RT5670_DMIC_CTRL1,
510 RT5670_DMIC_CLK_MASK, idx << RT5670_DMIC_CLK_SFT);
511 return idx;
512}
513
514static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
515 struct snd_soc_dapm_widget *sink)
516{
517 unsigned int val;
518
519 val = snd_soc_read(source->codec, RT5670_GLB_CLK);
520 val &= RT5670_SCLK_SRC_MASK;
521 if (val == RT5670_SCLK_SRC_PLL1)
522 return 1;
523 else
524 return 0;
525}
526
527static int is_using_asrc(struct snd_soc_dapm_widget *source,
528 struct snd_soc_dapm_widget *sink)
529{
530 unsigned int reg, shift, val;
531
532 switch (source->shift) {
533 case 0:
534 reg = RT5670_ASRC_3;
535 shift = 0;
536 break;
537 case 1:
538 reg = RT5670_ASRC_3;
539 shift = 4;
540 break;
541 case 2:
542 reg = RT5670_ASRC_5;
543 shift = 12;
544 break;
545 case 3:
546 reg = RT5670_ASRC_2;
547 shift = 0;
548 break;
549 case 8:
550 reg = RT5670_ASRC_2;
551 shift = 4;
552 break;
553 case 9:
554 reg = RT5670_ASRC_2;
555 shift = 8;
556 break;
557 case 10:
558 reg = RT5670_ASRC_2;
559 shift = 12;
560 break;
561 default:
562 return 0;
563 }
564
565 val = (snd_soc_read(source->codec, reg) >> shift) & 0xf;
566 switch (val) {
567 case 1:
568 case 2:
569 case 3:
570 case 4:
571 return 1;
572 default:
573 return 0;
574 }
575
576}
577
578/* Digital Mixer */
579static const struct snd_kcontrol_new rt5670_sto1_adc_l_mix[] = {
580 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO1_ADC_MIXER,
581 RT5670_M_ADC_L1_SFT, 1, 1),
582 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO1_ADC_MIXER,
583 RT5670_M_ADC_L2_SFT, 1, 1),
584};
585
586static const struct snd_kcontrol_new rt5670_sto1_adc_r_mix[] = {
587 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO1_ADC_MIXER,
588 RT5670_M_ADC_R1_SFT, 1, 1),
589 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO1_ADC_MIXER,
590 RT5670_M_ADC_R2_SFT, 1, 1),
591};
592
593static const struct snd_kcontrol_new rt5670_sto2_adc_l_mix[] = {
594 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO2_ADC_MIXER,
595 RT5670_M_ADC_L1_SFT, 1, 1),
596 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO2_ADC_MIXER,
597 RT5670_M_ADC_L2_SFT, 1, 1),
598};
599
600static const struct snd_kcontrol_new rt5670_sto2_adc_r_mix[] = {
601 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_STO2_ADC_MIXER,
602 RT5670_M_ADC_R1_SFT, 1, 1),
603 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_STO2_ADC_MIXER,
604 RT5670_M_ADC_R2_SFT, 1, 1),
605};
606
607static const struct snd_kcontrol_new rt5670_mono_adc_l_mix[] = {
608 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_MONO_ADC_MIXER,
609 RT5670_M_MONO_ADC_L1_SFT, 1, 1),
610 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_MONO_ADC_MIXER,
611 RT5670_M_MONO_ADC_L2_SFT, 1, 1),
612};
613
614static const struct snd_kcontrol_new rt5670_mono_adc_r_mix[] = {
615 SOC_DAPM_SINGLE("ADC1 Switch", RT5670_MONO_ADC_MIXER,
616 RT5670_M_MONO_ADC_R1_SFT, 1, 1),
617 SOC_DAPM_SINGLE("ADC2 Switch", RT5670_MONO_ADC_MIXER,
618 RT5670_M_MONO_ADC_R2_SFT, 1, 1),
619};
620
621static const struct snd_kcontrol_new rt5670_dac_l_mix[] = {
622 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5670_AD_DA_MIXER,
623 RT5670_M_ADCMIX_L_SFT, 1, 1),
624 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_AD_DA_MIXER,
625 RT5670_M_DAC1_L_SFT, 1, 1),
626};
627
628static const struct snd_kcontrol_new rt5670_dac_r_mix[] = {
629 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5670_AD_DA_MIXER,
630 RT5670_M_ADCMIX_R_SFT, 1, 1),
631 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_AD_DA_MIXER,
632 RT5670_M_DAC1_R_SFT, 1, 1),
633};
634
635static const struct snd_kcontrol_new rt5670_sto_dac_l_mix[] = {
636 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_STO_DAC_MIXER,
637 RT5670_M_DAC_L1_SFT, 1, 1),
638 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_STO_DAC_MIXER,
639 RT5670_M_DAC_L2_SFT, 1, 1),
640 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_STO_DAC_MIXER,
641 RT5670_M_DAC_R1_STO_L_SFT, 1, 1),
642};
643
644static const struct snd_kcontrol_new rt5670_sto_dac_r_mix[] = {
645 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_STO_DAC_MIXER,
646 RT5670_M_DAC_R1_SFT, 1, 1),
647 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_STO_DAC_MIXER,
648 RT5670_M_DAC_R2_SFT, 1, 1),
649 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_STO_DAC_MIXER,
650 RT5670_M_DAC_L1_STO_R_SFT, 1, 1),
651};
652
653static const struct snd_kcontrol_new rt5670_mono_dac_l_mix[] = {
654 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_DD_MIXER,
655 RT5670_M_DAC_L1_MONO_L_SFT, 1, 1),
656 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DD_MIXER,
657 RT5670_M_DAC_L2_MONO_L_SFT, 1, 1),
658 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DD_MIXER,
659 RT5670_M_DAC_R2_MONO_L_SFT, 1, 1),
660};
661
662static const struct snd_kcontrol_new rt5670_mono_dac_r_mix[] = {
663 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_DD_MIXER,
664 RT5670_M_DAC_R1_MONO_R_SFT, 1, 1),
665 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DD_MIXER,
666 RT5670_M_DAC_R2_MONO_R_SFT, 1, 1),
667 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DD_MIXER,
668 RT5670_M_DAC_L2_MONO_R_SFT, 1, 1),
669};
670
671static const struct snd_kcontrol_new rt5670_dig_l_mix[] = {
672 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5670_DIG_MIXER,
673 RT5670_M_STO_L_DAC_L_SFT, 1, 1),
674 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DIG_MIXER,
675 RT5670_M_DAC_L2_DAC_L_SFT, 1, 1),
676 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DIG_MIXER,
677 RT5670_M_DAC_R2_DAC_L_SFT, 1, 1),
678};
679
680static const struct snd_kcontrol_new rt5670_dig_r_mix[] = {
681 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5670_DIG_MIXER,
682 RT5670_M_STO_R_DAC_R_SFT, 1, 1),
683 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DIG_MIXER,
684 RT5670_M_DAC_R2_DAC_R_SFT, 1, 1),
685 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_DIG_MIXER,
686 RT5670_M_DAC_L2_DAC_R_SFT, 1, 1),
687};
688
689/* Analog Input Mixer */
690static const struct snd_kcontrol_new rt5670_rec_l_mix[] = {
691 SOC_DAPM_SINGLE("INL Switch", RT5670_REC_L2_MIXER,
692 RT5670_M_IN_L_RM_L_SFT, 1, 1),
693 SOC_DAPM_SINGLE("BST2 Switch", RT5670_REC_L2_MIXER,
694 RT5670_M_BST2_RM_L_SFT, 1, 1),
695 SOC_DAPM_SINGLE("BST1 Switch", RT5670_REC_L2_MIXER,
696 RT5670_M_BST1_RM_L_SFT, 1, 1),
697};
698
699static const struct snd_kcontrol_new rt5670_rec_r_mix[] = {
700 SOC_DAPM_SINGLE("INR Switch", RT5670_REC_R2_MIXER,
701 RT5670_M_IN_R_RM_R_SFT, 1, 1),
702 SOC_DAPM_SINGLE("BST2 Switch", RT5670_REC_R2_MIXER,
703 RT5670_M_BST2_RM_R_SFT, 1, 1),
704 SOC_DAPM_SINGLE("BST1 Switch", RT5670_REC_R2_MIXER,
705 RT5670_M_BST1_RM_R_SFT, 1, 1),
706};
707
708static const struct snd_kcontrol_new rt5670_out_l_mix[] = {
709 SOC_DAPM_SINGLE("BST1 Switch", RT5670_OUT_L1_MIXER,
710 RT5670_M_BST1_OM_L_SFT, 1, 1),
711 SOC_DAPM_SINGLE("INL Switch", RT5670_OUT_L1_MIXER,
712 RT5670_M_IN_L_OM_L_SFT, 1, 1),
713 SOC_DAPM_SINGLE("DAC L2 Switch", RT5670_OUT_L1_MIXER,
714 RT5670_M_DAC_L2_OM_L_SFT, 1, 1),
715 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_OUT_L1_MIXER,
716 RT5670_M_DAC_L1_OM_L_SFT, 1, 1),
717};
718
719static const struct snd_kcontrol_new rt5670_out_r_mix[] = {
720 SOC_DAPM_SINGLE("BST2 Switch", RT5670_OUT_R1_MIXER,
721 RT5670_M_BST2_OM_R_SFT, 1, 1),
722 SOC_DAPM_SINGLE("INR Switch", RT5670_OUT_R1_MIXER,
723 RT5670_M_IN_R_OM_R_SFT, 1, 1),
724 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_OUT_R1_MIXER,
725 RT5670_M_DAC_R2_OM_R_SFT, 1, 1),
726 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_OUT_R1_MIXER,
727 RT5670_M_DAC_R1_OM_R_SFT, 1, 1),
728};
729
730static const struct snd_kcontrol_new rt5670_hpo_mix[] = {
731 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
732 RT5670_M_DAC1_HM_SFT, 1, 1),
733 SOC_DAPM_SINGLE("HPVOL Switch", RT5670_HPO_MIXER,
734 RT5670_M_HPVOL_HM_SFT, 1, 1),
735};
736
737static const struct snd_kcontrol_new rt5670_hpvoll_mix[] = {
738 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
739 RT5670_M_DACL1_HML_SFT, 1, 1),
740 SOC_DAPM_SINGLE("INL Switch", RT5670_HPO_MIXER,
741 RT5670_M_INL1_HML_SFT, 1, 1),
742};
743
744static const struct snd_kcontrol_new rt5670_hpvolr_mix[] = {
745 SOC_DAPM_SINGLE("DAC1 Switch", RT5670_HPO_MIXER,
746 RT5670_M_DACR1_HMR_SFT, 1, 1),
747 SOC_DAPM_SINGLE("INR Switch", RT5670_HPO_MIXER,
748 RT5670_M_INR1_HMR_SFT, 1, 1),
749};
750
751static const struct snd_kcontrol_new rt5670_lout_mix[] = {
752 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_LOUT_MIXER,
753 RT5670_M_DAC_L1_LM_SFT, 1, 1),
754 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_LOUT_MIXER,
755 RT5670_M_DAC_R1_LM_SFT, 1, 1),
756 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5670_LOUT_MIXER,
757 RT5670_M_OV_L_LM_SFT, 1, 1),
758 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5670_LOUT_MIXER,
759 RT5670_M_OV_R_LM_SFT, 1, 1),
760};
761
762static const struct snd_kcontrol_new rt5670_hpl_mix[] = {
763 SOC_DAPM_SINGLE("DAC L1 Switch", RT5670_HPO_MIXER,
764 RT5670_M_DACL1_HML_SFT, 1, 1),
765 SOC_DAPM_SINGLE("INL1 Switch", RT5670_HPO_MIXER,
766 RT5670_M_INL1_HML_SFT, 1, 1),
767};
768
769static const struct snd_kcontrol_new rt5670_hpr_mix[] = {
770 SOC_DAPM_SINGLE("DAC R1 Switch", RT5670_HPO_MIXER,
771 RT5670_M_DACR1_HMR_SFT, 1, 1),
772 SOC_DAPM_SINGLE("INR1 Switch", RT5670_HPO_MIXER,
773 RT5670_M_INR1_HMR_SFT, 1, 1),
774};
775
776static const struct snd_kcontrol_new lout_l_enable_control =
777 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5670_LOUT1,
778 RT5670_L_MUTE_SFT, 1, 1);
779
780static const struct snd_kcontrol_new lout_r_enable_control =
781 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5670_LOUT1,
782 RT5670_R_MUTE_SFT, 1, 1);
783
784/* DAC1 L/R source */ /* MX-29 [9:8] [11:10] */
785static const char * const rt5670_dac1_src[] = {
786 "IF1 DAC", "IF2 DAC"
787};
788
789static SOC_ENUM_SINGLE_DECL(rt5670_dac1l_enum, RT5670_AD_DA_MIXER,
790 RT5670_DAC1_L_SEL_SFT, rt5670_dac1_src);
791
792static const struct snd_kcontrol_new rt5670_dac1l_mux =
793 SOC_DAPM_ENUM("DAC1 L source", rt5670_dac1l_enum);
794
795static SOC_ENUM_SINGLE_DECL(rt5670_dac1r_enum, RT5670_AD_DA_MIXER,
796 RT5670_DAC1_R_SEL_SFT, rt5670_dac1_src);
797
798static const struct snd_kcontrol_new rt5670_dac1r_mux =
799 SOC_DAPM_ENUM("DAC1 R source", rt5670_dac1r_enum);
800
801/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
802/* TODO Use SOC_VALUE_ENUM_SINGLE_DECL */
803static const char * const rt5670_dac12_src[] = {
804 "IF1 DAC", "IF2 DAC", "IF3 DAC", "TxDC DAC",
805 "Bass", "VAD_ADC", "IF4 DAC"
806};
807
808static SOC_ENUM_SINGLE_DECL(rt5670_dac2l_enum, RT5670_DAC_CTRL,
809 RT5670_DAC2_L_SEL_SFT, rt5670_dac12_src);
810
811static const struct snd_kcontrol_new rt5670_dac_l2_mux =
812 SOC_DAPM_ENUM("DAC2 L source", rt5670_dac2l_enum);
813
814static const char * const rt5670_dacr2_src[] = {
815 "IF1 DAC", "IF2 DAC", "IF3 DAC", "TxDC DAC", "TxDP ADC", "IF4 DAC"
816};
817
818static SOC_ENUM_SINGLE_DECL(rt5670_dac2r_enum, RT5670_DAC_CTRL,
819 RT5670_DAC2_R_SEL_SFT, rt5670_dacr2_src);
820
821static const struct snd_kcontrol_new rt5670_dac_r2_mux =
822 SOC_DAPM_ENUM("DAC2 R source", rt5670_dac2r_enum);
823
824/*RxDP source*/ /* MX-2D [15:13] */
825static const char * const rt5670_rxdp_src[] = {
826 "IF2 DAC", "IF1 DAC", "STO1 ADC Mixer", "STO2 ADC Mixer",
827 "Mono ADC Mixer L", "Mono ADC Mixer R", "DAC1"
828};
829
830static SOC_ENUM_SINGLE_DECL(rt5670_rxdp_enum, RT5670_DSP_PATH1,
831 RT5670_RXDP_SEL_SFT, rt5670_rxdp_src);
832
833static const struct snd_kcontrol_new rt5670_rxdp_mux =
834 SOC_DAPM_ENUM("DAC2 L source", rt5670_rxdp_enum);
835
836/* MX-2D [1] [0] */
837static const char * const rt5670_dsp_bypass_src[] = {
838 "DSP", "Bypass"
839};
840
841static SOC_ENUM_SINGLE_DECL(rt5670_dsp_ul_enum, RT5670_DSP_PATH1,
842 RT5670_DSP_UL_SFT, rt5670_dsp_bypass_src);
843
844static const struct snd_kcontrol_new rt5670_dsp_ul_mux =
845 SOC_DAPM_ENUM("DSP UL source", rt5670_dsp_ul_enum);
846
847static SOC_ENUM_SINGLE_DECL(rt5670_dsp_dl_enum, RT5670_DSP_PATH1,
848 RT5670_DSP_DL_SFT, rt5670_dsp_bypass_src);
849
850static const struct snd_kcontrol_new rt5670_dsp_dl_mux =
851 SOC_DAPM_ENUM("DSP DL source", rt5670_dsp_dl_enum);
852
853/* Stereo2 ADC source */
854/* MX-26 [15] */
855static const char * const rt5670_stereo2_adc_lr_src[] = {
856 "L", "LR"
857};
858
859static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc_lr_enum, RT5670_STO2_ADC_MIXER,
860 RT5670_STO2_ADC_SRC_SFT, rt5670_stereo2_adc_lr_src);
861
862static const struct snd_kcontrol_new rt5670_sto2_adc_lr_mux =
863 SOC_DAPM_ENUM("Stereo2 ADC LR source", rt5670_stereo2_adc_lr_enum);
864
865/* Stereo1 ADC source */
866/* MX-27 MX-26 [12] */
867static const char * const rt5670_stereo_adc1_src[] = {
868 "DAC MIX", "ADC"
869};
870
871static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_adc1_enum, RT5670_STO1_ADC_MIXER,
872 RT5670_ADC_1_SRC_SFT, rt5670_stereo_adc1_src);
873
874static const struct snd_kcontrol_new rt5670_sto_adc_l1_mux =
875 SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5670_stereo1_adc1_enum);
876
877static const struct snd_kcontrol_new rt5670_sto_adc_r1_mux =
878 SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5670_stereo1_adc1_enum);
879
880static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc1_enum, RT5670_STO2_ADC_MIXER,
881 RT5670_ADC_1_SRC_SFT, rt5670_stereo_adc1_src);
882
883static const struct snd_kcontrol_new rt5670_sto2_adc_l1_mux =
884 SOC_DAPM_ENUM("Stereo2 ADC L1 source", rt5670_stereo2_adc1_enum);
885
886static const struct snd_kcontrol_new rt5670_sto2_adc_r1_mux =
887 SOC_DAPM_ENUM("Stereo2 ADC R1 source", rt5670_stereo2_adc1_enum);
888
889/* MX-27 MX-26 [11] */
890static const char * const rt5670_stereo_adc2_src[] = {
891 "DAC MIX", "DMIC"
892};
893
894static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_adc2_enum, RT5670_STO1_ADC_MIXER,
895 RT5670_ADC_2_SRC_SFT, rt5670_stereo_adc2_src);
896
897static const struct snd_kcontrol_new rt5670_sto_adc_l2_mux =
898 SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5670_stereo1_adc2_enum);
899
900static const struct snd_kcontrol_new rt5670_sto_adc_r2_mux =
901 SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5670_stereo1_adc2_enum);
902
903static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc2_enum, RT5670_STO2_ADC_MIXER,
904 RT5670_ADC_2_SRC_SFT, rt5670_stereo_adc2_src);
905
906static const struct snd_kcontrol_new rt5670_sto2_adc_l2_mux =
907 SOC_DAPM_ENUM("Stereo2 ADC L2 source", rt5670_stereo2_adc2_enum);
908
909static const struct snd_kcontrol_new rt5670_sto2_adc_r2_mux =
910 SOC_DAPM_ENUM("Stereo2 ADC R2 source", rt5670_stereo2_adc2_enum);
911
912/* MX-27 MX26 [10] */
913static const char * const rt5670_stereo_adc_src[] = {
914 "ADC1L ADC2R", "ADC3"
915};
916
917static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_adc_enum, RT5670_STO1_ADC_MIXER,
918 RT5670_ADC_SRC_SFT, rt5670_stereo_adc_src);
919
920static const struct snd_kcontrol_new rt5670_sto_adc_mux =
921 SOC_DAPM_ENUM("Stereo1 ADC source", rt5670_stereo1_adc_enum);
922
923static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_adc_enum, RT5670_STO2_ADC_MIXER,
924 RT5670_ADC_SRC_SFT, rt5670_stereo_adc_src);
925
926static const struct snd_kcontrol_new rt5670_sto2_adc_mux =
927 SOC_DAPM_ENUM("Stereo2 ADC source", rt5670_stereo2_adc_enum);
928
929/* MX-27 MX-26 [9:8] */
930static const char * const rt5670_stereo_dmic_src[] = {
931 "DMIC1", "DMIC2", "DMIC3"
932};
933
934static SOC_ENUM_SINGLE_DECL(rt5670_stereo1_dmic_enum, RT5670_STO1_ADC_MIXER,
935 RT5670_DMIC_SRC_SFT, rt5670_stereo_dmic_src);
936
937static const struct snd_kcontrol_new rt5670_sto1_dmic_mux =
938 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5670_stereo1_dmic_enum);
939
940static SOC_ENUM_SINGLE_DECL(rt5670_stereo2_dmic_enum, RT5670_STO2_ADC_MIXER,
941 RT5670_DMIC_SRC_SFT, rt5670_stereo_dmic_src);
942
943static const struct snd_kcontrol_new rt5670_sto2_dmic_mux =
944 SOC_DAPM_ENUM("Stereo2 DMIC source", rt5670_stereo2_dmic_enum);
945
946/* MX-27 [0] */
947static const char * const rt5670_stereo_dmic3_src[] = {
948 "DMIC3", "PDM ADC"
949};
950
951static SOC_ENUM_SINGLE_DECL(rt5670_stereo_dmic3_enum, RT5670_STO1_ADC_MIXER,
952 RT5670_DMIC3_SRC_SFT, rt5670_stereo_dmic3_src);
953
954static const struct snd_kcontrol_new rt5670_sto_dmic3_mux =
955 SOC_DAPM_ENUM("Stereo DMIC3 source", rt5670_stereo_dmic3_enum);
956
957/* Mono ADC source */
958/* MX-28 [12] */
959static const char * const rt5670_mono_adc_l1_src[] = {
960 "Mono DAC MIXL", "ADC1"
961};
962
963static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_l1_enum, RT5670_MONO_ADC_MIXER,
964 RT5670_MONO_ADC_L1_SRC_SFT, rt5670_mono_adc_l1_src);
965
966static const struct snd_kcontrol_new rt5670_mono_adc_l1_mux =
967 SOC_DAPM_ENUM("Mono ADC1 left source", rt5670_mono_adc_l1_enum);
968/* MX-28 [11] */
969static const char * const rt5670_mono_adc_l2_src[] = {
970 "Mono DAC MIXL", "DMIC"
971};
972
973static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_l2_enum, RT5670_MONO_ADC_MIXER,
974 RT5670_MONO_ADC_L2_SRC_SFT, rt5670_mono_adc_l2_src);
975
976static const struct snd_kcontrol_new rt5670_mono_adc_l2_mux =
977 SOC_DAPM_ENUM("Mono ADC2 left source", rt5670_mono_adc_l2_enum);
978
979/* MX-28 [9:8] */
980static const char * const rt5670_mono_dmic_src[] = {
981 "DMIC1", "DMIC2", "DMIC3"
982};
983
984static SOC_ENUM_SINGLE_DECL(rt5670_mono_dmic_l_enum, RT5670_MONO_ADC_MIXER,
985 RT5670_MONO_DMIC_L_SRC_SFT, rt5670_mono_dmic_src);
986
987static const struct snd_kcontrol_new rt5670_mono_dmic_l_mux =
988 SOC_DAPM_ENUM("Mono DMIC left source", rt5670_mono_dmic_l_enum);
989/* MX-28 [1:0] */
990static SOC_ENUM_SINGLE_DECL(rt5670_mono_dmic_r_enum, RT5670_MONO_ADC_MIXER,
991 RT5670_MONO_DMIC_R_SRC_SFT, rt5670_mono_dmic_src);
992
993static const struct snd_kcontrol_new rt5670_mono_dmic_r_mux =
994 SOC_DAPM_ENUM("Mono DMIC Right source", rt5670_mono_dmic_r_enum);
995/* MX-28 [4] */
996static const char * const rt5670_mono_adc_r1_src[] = {
997 "Mono DAC MIXR", "ADC2"
998};
999
1000static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_r1_enum, RT5670_MONO_ADC_MIXER,
1001 RT5670_MONO_ADC_R1_SRC_SFT, rt5670_mono_adc_r1_src);
1002
1003static const struct snd_kcontrol_new rt5670_mono_adc_r1_mux =
1004 SOC_DAPM_ENUM("Mono ADC1 right source", rt5670_mono_adc_r1_enum);
1005/* MX-28 [3] */
1006static const char * const rt5670_mono_adc_r2_src[] = {
1007 "Mono DAC MIXR", "DMIC"
1008};
1009
1010static SOC_ENUM_SINGLE_DECL(rt5670_mono_adc_r2_enum, RT5670_MONO_ADC_MIXER,
1011 RT5670_MONO_ADC_R2_SRC_SFT, rt5670_mono_adc_r2_src);
1012
1013static const struct snd_kcontrol_new rt5670_mono_adc_r2_mux =
1014 SOC_DAPM_ENUM("Mono ADC2 right source", rt5670_mono_adc_r2_enum);
1015
1016/* MX-2D [3:2] */
1017static const char * const rt5670_txdp_slot_src[] = {
1018 "Slot 0-1", "Slot 2-3", "Slot 4-5", "Slot 6-7"
1019};
1020
1021static SOC_ENUM_SINGLE_DECL(rt5670_txdp_slot_enum, RT5670_DSP_PATH1,
1022 RT5670_TXDP_SLOT_SEL_SFT, rt5670_txdp_slot_src);
1023
1024static const struct snd_kcontrol_new rt5670_txdp_slot_mux =
1025 SOC_DAPM_ENUM("TxDP Slot source", rt5670_txdp_slot_enum);
1026
1027/* MX-2F [15] */
1028static const char * const rt5670_if1_adc2_in_src[] = {
1029 "IF_ADC2", "VAD_ADC"
1030};
1031
1032static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc2_in_enum, RT5670_DIG_INF1_DATA,
1033 RT5670_IF1_ADC2_IN_SFT, rt5670_if1_adc2_in_src);
1034
1035static const struct snd_kcontrol_new rt5670_if1_adc2_in_mux =
1036 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5670_if1_adc2_in_enum);
1037
1038/* MX-2F [14:12] */
1039static const char * const rt5670_if2_adc_in_src[] = {
1040 "IF_ADC1", "IF_ADC2", "IF_ADC3", "TxDC_DAC", "TxDP_ADC", "VAD_ADC"
1041};
1042
1043static SOC_ENUM_SINGLE_DECL(rt5670_if2_adc_in_enum, RT5670_DIG_INF1_DATA,
1044 RT5670_IF2_ADC_IN_SFT, rt5670_if2_adc_in_src);
1045
1046static const struct snd_kcontrol_new rt5670_if2_adc_in_mux =
1047 SOC_DAPM_ENUM("IF2 ADC IN source", rt5670_if2_adc_in_enum);
1048
1049/* MX-30 [5:4] */
1050static const char * const rt5670_if4_adc_in_src[] = {
1051 "IF_ADC1", "IF_ADC2", "IF_ADC3"
1052};
1053
1054static SOC_ENUM_SINGLE_DECL(rt5670_if4_adc_in_enum, RT5670_DIG_INF2_DATA,
1055 RT5670_IF4_ADC_IN_SFT, rt5670_if4_adc_in_src);
1056
1057static const struct snd_kcontrol_new rt5670_if4_adc_in_mux =
1058 SOC_DAPM_ENUM("IF4 ADC IN source", rt5670_if4_adc_in_enum);
1059
1060/* MX-31 [15] [13] [11] [9] */
1061static const char * const rt5670_pdm_src[] = {
1062 "Mono DAC", "Stereo DAC"
1063};
1064
1065static SOC_ENUM_SINGLE_DECL(rt5670_pdm1_l_enum, RT5670_PDM_OUT_CTRL,
1066 RT5670_PDM1_L_SFT, rt5670_pdm_src);
1067
1068static const struct snd_kcontrol_new rt5670_pdm1_l_mux =
1069 SOC_DAPM_ENUM("PDM1 L source", rt5670_pdm1_l_enum);
1070
1071static SOC_ENUM_SINGLE_DECL(rt5670_pdm1_r_enum, RT5670_PDM_OUT_CTRL,
1072 RT5670_PDM1_R_SFT, rt5670_pdm_src);
1073
1074static const struct snd_kcontrol_new rt5670_pdm1_r_mux =
1075 SOC_DAPM_ENUM("PDM1 R source", rt5670_pdm1_r_enum);
1076
1077static SOC_ENUM_SINGLE_DECL(rt5670_pdm2_l_enum, RT5670_PDM_OUT_CTRL,
1078 RT5670_PDM2_L_SFT, rt5670_pdm_src);
1079
1080static const struct snd_kcontrol_new rt5670_pdm2_l_mux =
1081 SOC_DAPM_ENUM("PDM2 L source", rt5670_pdm2_l_enum);
1082
1083static SOC_ENUM_SINGLE_DECL(rt5670_pdm2_r_enum, RT5670_PDM_OUT_CTRL,
1084 RT5670_PDM2_R_SFT, rt5670_pdm_src);
1085
1086static const struct snd_kcontrol_new rt5670_pdm2_r_mux =
1087 SOC_DAPM_ENUM("PDM2 R source", rt5670_pdm2_r_enum);
1088
1089/* MX-FA [12] */
1090static const char * const rt5670_if1_adc1_in1_src[] = {
1091 "IF_ADC1", "IF1_ADC3"
1092};
1093
1094static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc1_in1_enum, RT5670_DIG_MISC,
1095 RT5670_IF1_ADC1_IN1_SFT, rt5670_if1_adc1_in1_src);
1096
1097static const struct snd_kcontrol_new rt5670_if1_adc1_in1_mux =
1098 SOC_DAPM_ENUM("IF1 ADC1 IN1 source", rt5670_if1_adc1_in1_enum);
1099
1100/* MX-FA [11] */
1101static const char * const rt5670_if1_adc1_in2_src[] = {
1102 "IF1_ADC1_IN1", "IF1_ADC4"
1103};
1104
1105static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc1_in2_enum, RT5670_DIG_MISC,
1106 RT5670_IF1_ADC1_IN2_SFT, rt5670_if1_adc1_in2_src);
1107
1108static const struct snd_kcontrol_new rt5670_if1_adc1_in2_mux =
1109 SOC_DAPM_ENUM("IF1 ADC1 IN2 source", rt5670_if1_adc1_in2_enum);
1110
1111/* MX-FA [10] */
1112static const char * const rt5670_if1_adc2_in1_src[] = {
1113 "IF1_ADC2_IN", "IF1_ADC4"
1114};
1115
1116static SOC_ENUM_SINGLE_DECL(rt5670_if1_adc2_in1_enum, RT5670_DIG_MISC,
1117 RT5670_IF1_ADC2_IN1_SFT, rt5670_if1_adc2_in1_src);
1118
1119static const struct snd_kcontrol_new rt5670_if1_adc2_in1_mux =
1120 SOC_DAPM_ENUM("IF1 ADC2 IN1 source", rt5670_if1_adc2_in1_enum);
1121
1122/* MX-9D [9:8] */
1123static const char * const rt5670_vad_adc_src[] = {
1124 "Sto1 ADC L", "Mono ADC L", "Mono ADC R", "Sto2 ADC L"
1125};
1126
1127static SOC_ENUM_SINGLE_DECL(rt5670_vad_adc_enum, RT5670_VAD_CTRL4,
1128 RT5670_VAD_SEL_SFT, rt5670_vad_adc_src);
1129
1130static const struct snd_kcontrol_new rt5670_vad_adc_mux =
1131 SOC_DAPM_ENUM("VAD ADC source", rt5670_vad_adc_enum);
1132
1133static int rt5670_hp_power_event(struct snd_soc_dapm_widget *w,
1134 struct snd_kcontrol *kcontrol, int event)
1135{
1136 struct snd_soc_codec *codec = w->codec;
1137 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
1138
1139 switch (event) {
1140 case SND_SOC_DAPM_POST_PMU:
1141 regmap_update_bits(rt5670->regmap, RT5670_CHARGE_PUMP,
1142 RT5670_PM_HP_MASK, RT5670_PM_HP_HV);
1143 regmap_update_bits(rt5670->regmap, RT5670_GEN_CTRL2,
1144 0x0400, 0x0400);
1145 /* headphone amp power on */
1146 regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
1147 RT5670_PWR_HA | RT5670_PWR_FV1 |
1148 RT5670_PWR_FV2, RT5670_PWR_HA |
1149 RT5670_PWR_FV1 | RT5670_PWR_FV2);
1150 /* depop parameters */
1151 regmap_write(rt5670->regmap, RT5670_DEPOP_M2, 0x3100);
1152 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8009);
1153 regmap_write(rt5670->regmap, RT5670_PR_BASE +
1154 RT5670_HP_DCC_INT1, 0x9f00);
1155 mdelay(20);
1156 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
1157 break;
1158 case SND_SOC_DAPM_PRE_PMD:
1159 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x0004);
1160 msleep(30);
1161 break;
1162 default:
1163 return 0;
1164 }
1165
1166 return 0;
1167}
1168
1169static int rt5670_hp_event(struct snd_soc_dapm_widget *w,
1170 struct snd_kcontrol *kcontrol, int event)
1171{
1172 struct snd_soc_codec *codec = w->codec;
1173 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
1174
1175 switch (event) {
1176 case SND_SOC_DAPM_POST_PMU:
1177 /* headphone unmute sequence */
1178 regmap_write(rt5670->regmap, RT5670_PR_BASE +
1179 RT5670_MAMP_INT_REG2, 0xb400);
1180 regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0772);
1181 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x805d);
1182 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x831d);
1183 regmap_update_bits(rt5670->regmap, RT5670_GEN_CTRL2,
1184 0x0300, 0x0300);
1185 regmap_update_bits(rt5670->regmap, RT5670_HP_VOL,
1186 RT5670_L_MUTE | RT5670_R_MUTE, 0);
1187 msleep(80);
1188 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
1189 break;
1190
1191 case SND_SOC_DAPM_PRE_PMD:
1192 /* headphone mute sequence */
1193 regmap_write(rt5670->regmap, RT5670_PR_BASE +
1194 RT5670_MAMP_INT_REG2, 0xb400);
1195 regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0772);
1196 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x803d);
1197 mdelay(10);
1198 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x831d);
1199 mdelay(10);
1200 regmap_update_bits(rt5670->regmap, RT5670_HP_VOL,
1201 RT5670_L_MUTE | RT5670_R_MUTE,
1202 RT5670_L_MUTE | RT5670_R_MUTE);
1203 msleep(20);
1204 regmap_update_bits(rt5670->regmap,
1205 RT5670_GEN_CTRL2, 0x0300, 0x0);
1206 regmap_write(rt5670->regmap, RT5670_DEPOP_M1, 0x8019);
1207 regmap_write(rt5670->regmap, RT5670_DEPOP_M3, 0x0707);
1208 regmap_write(rt5670->regmap, RT5670_PR_BASE +
1209 RT5670_MAMP_INT_REG2, 0xfc00);
1210 break;
1211
1212 default:
1213 return 0;
1214 }
1215
1216 return 0;
1217}
1218
1219static int rt5670_bst1_event(struct snd_soc_dapm_widget *w,
1220 struct snd_kcontrol *kcontrol, int event)
1221{
1222 struct snd_soc_codec *codec = w->codec;
1223
1224 switch (event) {
1225 case SND_SOC_DAPM_POST_PMU:
1226 snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
1227 RT5670_PWR_BST1_P, RT5670_PWR_BST1_P);
1228 break;
1229
1230 case SND_SOC_DAPM_PRE_PMD:
1231 snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
1232 RT5670_PWR_BST1_P, 0);
1233 break;
1234
1235 default:
1236 return 0;
1237 }
1238
1239 return 0;
1240}
1241
1242static int rt5670_bst2_event(struct snd_soc_dapm_widget *w,
1243 struct snd_kcontrol *kcontrol, int event)
1244{
1245 struct snd_soc_codec *codec = w->codec;
1246
1247 switch (event) {
1248 case SND_SOC_DAPM_POST_PMU:
1249 snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
1250 RT5670_PWR_BST2_P, RT5670_PWR_BST2_P);
1251 break;
1252
1253 case SND_SOC_DAPM_PRE_PMD:
1254 snd_soc_update_bits(codec, RT5670_PWR_ANLG2,
1255 RT5670_PWR_BST2_P, 0);
1256 break;
1257
1258 default:
1259 return 0;
1260 }
1261
1262 return 0;
1263}
1264
1265static const struct snd_soc_dapm_widget rt5670_dapm_widgets[] = {
1266 SND_SOC_DAPM_SUPPLY("PLL1", RT5670_PWR_ANLG2,
1267 RT5670_PWR_PLL_BIT, 0, NULL, 0),
1268 SND_SOC_DAPM_SUPPLY("I2S DSP", RT5670_PWR_DIG2,
1269 RT5670_PWR_I2S_DSP_BIT, 0, NULL, 0),
1270 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5670_PWR_VOL,
1271 RT5670_PWR_MIC_DET_BIT, 0, NULL, 0),
1272
1273 /* ASRC */
1274 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5670_ASRC_1,
1275 11, 0, NULL, 0),
1276 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5670_ASRC_1,
1277 12, 0, NULL, 0),
1278 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5670_ASRC_1,
1279 10, 0, NULL, 0),
1280 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5670_ASRC_1,
1281 9, 0, NULL, 0),
1282 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5670_ASRC_1,
1283 8, 0, NULL, 0),
1284 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5670_ASRC_1,
1285 3, 0, NULL, 0),
1286 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5670_ASRC_1,
1287 2, 0, NULL, 0),
1288 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5670_ASRC_1,
1289 1, 0, NULL, 0),
1290 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5670_ASRC_1,
1291 0, 0, NULL, 0),
1292
1293 /* Input Side */
1294 /* micbias */
1295 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5670_PWR_ANLG2,
1296 RT5670_PWR_MB1_BIT, 0, NULL, 0),
1297
1298 /* Input Lines */
1299 SND_SOC_DAPM_INPUT("DMIC L1"),
1300 SND_SOC_DAPM_INPUT("DMIC R1"),
1301 SND_SOC_DAPM_INPUT("DMIC L2"),
1302 SND_SOC_DAPM_INPUT("DMIC R2"),
1303 SND_SOC_DAPM_INPUT("DMIC L3"),
1304 SND_SOC_DAPM_INPUT("DMIC R3"),
1305
1306 SND_SOC_DAPM_INPUT("IN1P"),
1307 SND_SOC_DAPM_INPUT("IN1N"),
1308 SND_SOC_DAPM_INPUT("IN2P"),
1309 SND_SOC_DAPM_INPUT("IN2N"),
1310
1311 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1312 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1313 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1314
1315 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1316 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1317 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5670_DMIC_CTRL1,
1318 RT5670_DMIC_1_EN_SFT, 0, NULL, 0),
1319 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5670_DMIC_CTRL1,
1320 RT5670_DMIC_2_EN_SFT, 0, NULL, 0),
1321 SND_SOC_DAPM_SUPPLY("DMIC3 Power", RT5670_DMIC_CTRL1,
1322 RT5670_DMIC_3_EN_SFT, 0, NULL, 0),
1323 /* Boost */
1324 SND_SOC_DAPM_PGA_E("BST1", RT5670_PWR_ANLG2, RT5670_PWR_BST1_BIT,
1325 0, NULL, 0, rt5670_bst1_event,
1326 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1327 SND_SOC_DAPM_PGA_E("BST2", RT5670_PWR_ANLG2, RT5670_PWR_BST2_BIT,
1328 0, NULL, 0, rt5670_bst2_event,
1329 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1330 /* Input Volume */
1331 SND_SOC_DAPM_PGA("INL VOL", RT5670_PWR_VOL,
1332 RT5670_PWR_IN_L_BIT, 0, NULL, 0),
1333 SND_SOC_DAPM_PGA("INR VOL", RT5670_PWR_VOL,
1334 RT5670_PWR_IN_R_BIT, 0, NULL, 0),
1335
1336 /* REC Mixer */
1337 SND_SOC_DAPM_MIXER("RECMIXL", RT5670_PWR_MIXER, RT5670_PWR_RM_L_BIT, 0,
1338 rt5670_rec_l_mix, ARRAY_SIZE(rt5670_rec_l_mix)),
1339 SND_SOC_DAPM_MIXER("RECMIXR", RT5670_PWR_MIXER, RT5670_PWR_RM_R_BIT, 0,
1340 rt5670_rec_r_mix, ARRAY_SIZE(rt5670_rec_r_mix)),
1341 /* ADCs */
1342 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
1343 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, 0, 0),
1344
1345 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
1346
1347 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5670_PWR_DIG1,
1348 RT5670_PWR_ADC_L_BIT, 0, NULL, 0),
1349 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5670_PWR_DIG1,
1350 RT5670_PWR_ADC_R_BIT, 0, NULL, 0),
1351 SND_SOC_DAPM_SUPPLY("ADC clock", RT5670_PR_BASE +
1352 RT5670_CHOP_DAC_ADC, 12, 0, NULL, 0),
1353 /* ADC Mux */
1354 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1355 &rt5670_sto1_dmic_mux),
1356 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1357 &rt5670_sto_adc_l2_mux),
1358 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1359 &rt5670_sto_adc_r2_mux),
1360 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1361 &rt5670_sto_adc_l1_mux),
1362 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1363 &rt5670_sto_adc_r1_mux),
1364 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
1365 &rt5670_sto2_dmic_mux),
1366 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1367 &rt5670_sto2_adc_l2_mux),
1368 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1369 &rt5670_sto2_adc_r2_mux),
1370 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1371 &rt5670_sto2_adc_l1_mux),
1372 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1373 &rt5670_sto2_adc_r1_mux),
1374 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
1375 &rt5670_sto2_adc_lr_mux),
1376 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1377 &rt5670_mono_dmic_l_mux),
1378 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1379 &rt5670_mono_dmic_r_mux),
1380 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1381 &rt5670_mono_adc_l2_mux),
1382 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1383 &rt5670_mono_adc_l1_mux),
1384 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1385 &rt5670_mono_adc_r1_mux),
1386 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1387 &rt5670_mono_adc_r2_mux),
1388 /* ADC Mixer */
1389 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5670_PWR_DIG2,
1390 RT5670_PWR_ADC_S1F_BIT, 0, NULL, 0),
1391 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5670_PWR_DIG2,
1392 RT5670_PWR_ADC_S2F_BIT, 0, NULL, 0),
1393 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", RT5670_STO1_ADC_DIG_VOL,
1394 RT5670_L_MUTE_SFT, 1, rt5670_sto1_adc_l_mix,
1395 ARRAY_SIZE(rt5670_sto1_adc_l_mix)),
1396 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", RT5670_STO1_ADC_DIG_VOL,
1397 RT5670_R_MUTE_SFT, 1, rt5670_sto1_adc_r_mix,
1398 ARRAY_SIZE(rt5670_sto1_adc_r_mix)),
1399 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1400 rt5670_sto2_adc_l_mix,
1401 ARRAY_SIZE(rt5670_sto2_adc_l_mix)),
1402 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1403 rt5670_sto2_adc_r_mix,
1404 ARRAY_SIZE(rt5670_sto2_adc_r_mix)),
1405 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5670_PWR_DIG2,
1406 RT5670_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1407 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5670_MONO_ADC_DIG_VOL,
1408 RT5670_L_MUTE_SFT, 1, rt5670_mono_adc_l_mix,
1409 ARRAY_SIZE(rt5670_mono_adc_l_mix)),
1410 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5670_PWR_DIG2,
1411 RT5670_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1412 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5670_MONO_ADC_DIG_VOL,
1413 RT5670_R_MUTE_SFT, 1, rt5670_mono_adc_r_mix,
1414 ARRAY_SIZE(rt5670_mono_adc_r_mix)),
1415
1416 /* ADC PGA */
1417 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1418 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1419 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1420 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1421 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1422 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1423 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1424 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1425 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1426 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1427 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1428 SND_SOC_DAPM_PGA("IF_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1429 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1430 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1431 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1432 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1433
1434 /* DSP */
1435 SND_SOC_DAPM_PGA("TxDP_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1436 SND_SOC_DAPM_PGA("TxDP_ADC_L", SND_SOC_NOPM, 0, 0, NULL, 0),
1437 SND_SOC_DAPM_PGA("TxDP_ADC_R", SND_SOC_NOPM, 0, 0, NULL, 0),
1438 SND_SOC_DAPM_PGA("TxDC_DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1439
1440 SND_SOC_DAPM_MUX("TDM Data Mux", SND_SOC_NOPM, 0, 0,
1441 &rt5670_txdp_slot_mux),
1442
1443 SND_SOC_DAPM_MUX("DSP UL Mux", SND_SOC_NOPM, 0, 0,
1444 &rt5670_dsp_ul_mux),
1445 SND_SOC_DAPM_MUX("DSP DL Mux", SND_SOC_NOPM, 0, 0,
1446 &rt5670_dsp_dl_mux),
1447
1448 SND_SOC_DAPM_MUX("RxDP Mux", SND_SOC_NOPM, 0, 0,
1449 &rt5670_rxdp_mux),
1450
1451 /* IF2 Mux */
1452 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0,
1453 &rt5670_if2_adc_in_mux),
1454
1455 /* Digital Interface */
1456 SND_SOC_DAPM_SUPPLY("I2S1", RT5670_PWR_DIG1,
1457 RT5670_PWR_I2S1_BIT, 0, NULL, 0),
1458 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1459 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1460 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1461 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1462 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1463 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1464 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1465 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1466 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1467 SND_SOC_DAPM_SUPPLY("I2S2", RT5670_PWR_DIG1,
1468 RT5670_PWR_I2S2_BIT, 0, NULL, 0),
1469 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1470 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1471 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1472 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1473 SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1474 SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1475
1476 /* Digital Interface Select */
1477 SND_SOC_DAPM_MUX("IF1 ADC1 IN1 Mux", SND_SOC_NOPM, 0, 0,
1478 &rt5670_if1_adc1_in1_mux),
1479 SND_SOC_DAPM_MUX("IF1 ADC1 IN2 Mux", SND_SOC_NOPM, 0, 0,
1480 &rt5670_if1_adc1_in2_mux),
1481 SND_SOC_DAPM_MUX("IF1 ADC2 IN Mux", SND_SOC_NOPM, 0, 0,
1482 &rt5670_if1_adc2_in_mux),
1483 SND_SOC_DAPM_MUX("IF1 ADC2 IN1 Mux", SND_SOC_NOPM, 0, 0,
1484 &rt5670_if1_adc2_in1_mux),
1485 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
1486 &rt5670_vad_adc_mux),
1487
1488 /* Audio Interface */
1489 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1490 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1491 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1492 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1493 RT5670_GPIO_CTRL1, RT5670_I2S2_PIN_SFT, 1),
1494
1495 /* Audio DSP */
1496 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1497
1498 /* Output Side */
1499 /* DAC mixer before sound effect */
1500 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1501 rt5670_dac_l_mix, ARRAY_SIZE(rt5670_dac_l_mix)),
1502 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1503 rt5670_dac_r_mix, ARRAY_SIZE(rt5670_dac_r_mix)),
1504 SND_SOC_DAPM_PGA("DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1505
1506 /* DAC2 channel Mux */
1507 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
1508 &rt5670_dac_l2_mux),
1509 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
1510 &rt5670_dac_r2_mux),
1511 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5670_PWR_DIG1,
1512 RT5670_PWR_DAC_L2_BIT, 0, NULL, 0),
1513 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5670_PWR_DIG1,
1514 RT5670_PWR_DAC_R2_BIT, 0, NULL, 0),
1515
1516 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5670_dac1l_mux),
1517 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5670_dac1r_mux),
1518
1519 /* DAC Mixer */
1520 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5670_PWR_DIG2,
1521 RT5670_PWR_DAC_S1F_BIT, 0, NULL, 0),
1522 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5670_PWR_DIG2,
1523 RT5670_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1524 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5670_PWR_DIG2,
1525 RT5670_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1526 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1527 rt5670_sto_dac_l_mix,
1528 ARRAY_SIZE(rt5670_sto_dac_l_mix)),
1529 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1530 rt5670_sto_dac_r_mix,
1531 ARRAY_SIZE(rt5670_sto_dac_r_mix)),
1532 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1533 rt5670_mono_dac_l_mix,
1534 ARRAY_SIZE(rt5670_mono_dac_l_mix)),
1535 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1536 rt5670_mono_dac_r_mix,
1537 ARRAY_SIZE(rt5670_mono_dac_r_mix)),
1538 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1539 rt5670_dig_l_mix,
1540 ARRAY_SIZE(rt5670_dig_l_mix)),
1541 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1542 rt5670_dig_r_mix,
1543 ARRAY_SIZE(rt5670_dig_r_mix)),
1544
1545 /* DACs */
1546 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5670_PWR_DIG1,
1547 RT5670_PWR_DAC_L1_BIT, 0, NULL, 0),
1548 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5670_PWR_DIG1,
1549 RT5670_PWR_DAC_R1_BIT, 0, NULL, 0),
1550 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
1551 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
1552 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5670_PWR_DIG1,
1553 RT5670_PWR_DAC_L2_BIT, 0),
1554
1555 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5670_PWR_DIG1,
1556 RT5670_PWR_DAC_R2_BIT, 0),
1557 /* OUT Mixer */
1558
1559 SND_SOC_DAPM_MIXER("OUT MIXL", RT5670_PWR_MIXER, RT5670_PWR_OM_L_BIT,
1560 0, rt5670_out_l_mix, ARRAY_SIZE(rt5670_out_l_mix)),
1561 SND_SOC_DAPM_MIXER("OUT MIXR", RT5670_PWR_MIXER, RT5670_PWR_OM_R_BIT,
1562 0, rt5670_out_r_mix, ARRAY_SIZE(rt5670_out_r_mix)),
1563 /* Ouput Volume */
1564 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5670_PWR_VOL,
1565 RT5670_PWR_HV_L_BIT, 0,
1566 rt5670_hpvoll_mix, ARRAY_SIZE(rt5670_hpvoll_mix)),
1567 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5670_PWR_VOL,
1568 RT5670_PWR_HV_R_BIT, 0,
1569 rt5670_hpvolr_mix, ARRAY_SIZE(rt5670_hpvolr_mix)),
1570 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1571 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1572 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1573
1574 /* HPO/LOUT/Mono Mixer */
1575 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
1576 rt5670_hpo_mix, ARRAY_SIZE(rt5670_hpo_mix)),
1577 SND_SOC_DAPM_MIXER("LOUT MIX", RT5670_PWR_ANLG1, RT5670_PWR_LM_BIT,
1578 0, rt5670_lout_mix, ARRAY_SIZE(rt5670_lout_mix)),
1579 SND_SOC_DAPM_SUPPLY_S("Improve HP Amp Drv", 1, SND_SOC_NOPM, 0, 0,
1580 rt5670_hp_power_event, SND_SOC_DAPM_POST_PMU |
1581 SND_SOC_DAPM_PRE_PMD),
1582 SND_SOC_DAPM_SUPPLY("HP L Amp", RT5670_PWR_ANLG1,
1583 RT5670_PWR_HP_L_BIT, 0, NULL, 0),
1584 SND_SOC_DAPM_SUPPLY("HP R Amp", RT5670_PWR_ANLG1,
1585 RT5670_PWR_HP_R_BIT, 0, NULL, 0),
1586 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0,
1587 rt5670_hp_event, SND_SOC_DAPM_PRE_PMD |
1588 SND_SOC_DAPM_POST_PMU),
1589 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
1590 &lout_l_enable_control),
1591 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
1592 &lout_r_enable_control),
1593 SND_SOC_DAPM_PGA("LOUT Amp", SND_SOC_NOPM, 0, 0, NULL, 0),
1594
1595 /* PDM */
1596 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5670_PWR_DIG2,
1597 RT5670_PWR_PDM1_BIT, 0, NULL, 0),
1598 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5670_PWR_DIG2,
1599 RT5670_PWR_PDM2_BIT, 0, NULL, 0),
1600
1601 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5670_PDM_OUT_CTRL,
1602 RT5670_M_PDM1_L_SFT, 1, &rt5670_pdm1_l_mux),
1603 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5670_PDM_OUT_CTRL,
1604 RT5670_M_PDM1_R_SFT, 1, &rt5670_pdm1_r_mux),
1605 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5670_PDM_OUT_CTRL,
1606 RT5670_M_PDM2_L_SFT, 1, &rt5670_pdm2_l_mux),
1607 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5670_PDM_OUT_CTRL,
1608 RT5670_M_PDM2_R_SFT, 1, &rt5670_pdm2_r_mux),
1609
1610 /* Output Lines */
1611 SND_SOC_DAPM_OUTPUT("HPOL"),
1612 SND_SOC_DAPM_OUTPUT("HPOR"),
1613 SND_SOC_DAPM_OUTPUT("LOUTL"),
1614 SND_SOC_DAPM_OUTPUT("LOUTR"),
1615 SND_SOC_DAPM_OUTPUT("PDM1L"),
1616 SND_SOC_DAPM_OUTPUT("PDM1R"),
1617 SND_SOC_DAPM_OUTPUT("PDM2L"),
1618 SND_SOC_DAPM_OUTPUT("PDM2R"),
1619};
1620
1621static const struct snd_soc_dapm_route rt5670_dapm_routes[] = {
1622 { "ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc },
1623 { "ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc },
1624 { "ADC Mono Left Filter", NULL, "ADC MONO L ASRC", is_using_asrc },
1625 { "ADC Mono Right Filter", NULL, "ADC MONO R ASRC", is_using_asrc },
1626 { "DAC Mono Left Filter", NULL, "DAC MONO L ASRC", is_using_asrc },
1627 { "DAC Mono Right Filter", NULL, "DAC MONO R ASRC", is_using_asrc },
1628 { "DAC Stereo1 Filter", NULL, "DAC STO ASRC", is_using_asrc },
1629
1630 { "I2S1", NULL, "I2S1 ASRC" },
1631 { "I2S2", NULL, "I2S2 ASRC" },
1632
1633 { "DMIC1", NULL, "DMIC L1" },
1634 { "DMIC1", NULL, "DMIC R1" },
1635 { "DMIC2", NULL, "DMIC L2" },
1636 { "DMIC2", NULL, "DMIC R2" },
1637 { "DMIC3", NULL, "DMIC L3" },
1638 { "DMIC3", NULL, "DMIC R3" },
1639
1640 { "BST1", NULL, "IN1P" },
1641 { "BST1", NULL, "IN1N" },
1642 { "BST1", NULL, "Mic Det Power" },
1643 { "BST2", NULL, "IN2P" },
1644 { "BST2", NULL, "IN2N" },
1645
1646 { "INL VOL", NULL, "IN2P" },
1647 { "INR VOL", NULL, "IN2N" },
1648
1649 { "RECMIXL", "INL Switch", "INL VOL" },
1650 { "RECMIXL", "BST2 Switch", "BST2" },
1651 { "RECMIXL", "BST1 Switch", "BST1" },
1652
1653 { "RECMIXR", "INR Switch", "INR VOL" },
1654 { "RECMIXR", "BST2 Switch", "BST2" },
1655 { "RECMIXR", "BST1 Switch", "BST1" },
1656
1657 { "ADC 1", NULL, "RECMIXL" },
1658 { "ADC 1", NULL, "ADC 1 power" },
1659 { "ADC 1", NULL, "ADC clock" },
1660 { "ADC 2", NULL, "RECMIXR" },
1661 { "ADC 2", NULL, "ADC 2 power" },
1662 { "ADC 2", NULL, "ADC clock" },
1663
1664 { "DMIC L1", NULL, "DMIC CLK" },
1665 { "DMIC L1", NULL, "DMIC1 Power" },
1666 { "DMIC R1", NULL, "DMIC CLK" },
1667 { "DMIC R1", NULL, "DMIC1 Power" },
1668 { "DMIC L2", NULL, "DMIC CLK" },
1669 { "DMIC L2", NULL, "DMIC2 Power" },
1670 { "DMIC R2", NULL, "DMIC CLK" },
1671 { "DMIC R2", NULL, "DMIC2 Power" },
1672 { "DMIC L3", NULL, "DMIC CLK" },
1673 { "DMIC L3", NULL, "DMIC3 Power" },
1674 { "DMIC R3", NULL, "DMIC CLK" },
1675 { "DMIC R3", NULL, "DMIC3 Power" },
1676
1677 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1678 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
1679 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
1680
1681 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
1682 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
1683 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
1684
1685 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1686 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
1687 { "Mono DMIC L Mux", "DMIC3", "DMIC L3" },
1688
1689 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1690 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
1691 { "Mono DMIC R Mux", "DMIC3", "DMIC R3" },
1692
1693 { "ADC 1_2", NULL, "ADC 1" },
1694 { "ADC 1_2", NULL, "ADC 2" },
1695
1696 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1697 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1698 { "Stereo1 ADC L1 Mux", "ADC", "ADC 1_2" },
1699 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1700
1701 { "Stereo1 ADC R1 Mux", "ADC", "ADC 1_2" },
1702 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1703 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1704 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1705
1706 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
1707 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1708 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1709 { "Mono ADC L1 Mux", "ADC1", "ADC 1" },
1710
1711 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1712 { "Mono ADC R1 Mux", "ADC2", "ADC 2" },
1713 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
1714 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1715
1716 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
1717 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
1718 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
1719 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
1720
1721 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
1722 { "Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter" },
1723 { "ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
1724
1725 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
1726 { "Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter" },
1727 { "ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll },
1728
1729 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
1730 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
1731 { "Mono ADC MIXL", NULL, "ADC Mono Left Filter" },
1732 { "ADC Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll },
1733
1734 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
1735 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
1736 { "Mono ADC MIXR", NULL, "ADC Mono Right Filter" },
1737 { "ADC Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll },
1738
1739 { "Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC Mux" },
1740 { "Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1741 { "Stereo2 ADC L1 Mux", "ADC", "ADC 1_2" },
1742 { "Stereo2 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1743
1744 { "Stereo2 ADC R1 Mux", "ADC", "ADC 1_2" },
1745 { "Stereo2 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1746 { "Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC Mux" },
1747 { "Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1748
1749 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux" },
1750 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux" },
1751 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux" },
1752 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux" },
1753
1754 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
1755 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
1756
1757 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
1758 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
1759
1760 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
1761 { "Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter" },
1762 { "ADC Stereo2 Filter", NULL, "PLL1", is_sys_clk_from_pll },
1763
1764 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
1765 { "Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter" },
1766 { "ADC Stereo2 Filter", NULL, "PLL1", is_sys_clk_from_pll },
1767
1768 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
1769 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
1770 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
1771 { "VAD ADC Mux", "Sto2 ADC L", "Sto2 ADC MIXL" },
1772
1773 { "VAD_ADC", NULL, "VAD ADC Mux" },
1774
1775 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
1776 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
1777 { "IF_ADC2", NULL, "Mono ADC MIXL" },
1778 { "IF_ADC2", NULL, "Mono ADC MIXR" },
1779 { "IF_ADC3", NULL, "Stereo2 ADC MIXL" },
1780 { "IF_ADC3", NULL, "Stereo2 ADC MIXR" },
1781
1782 { "IF1 ADC1 IN1 Mux", "IF_ADC1", "IF_ADC1" },
1783 { "IF1 ADC1 IN1 Mux", "IF1_ADC3", "IF1_ADC3" },
1784
1785 { "IF1 ADC1 IN2 Mux", "IF1_ADC1_IN1", "IF1 ADC1 IN1 Mux" },
1786 { "IF1 ADC1 IN2 Mux", "IF1_ADC4", "IF1_ADC4" },
1787
1788 { "IF1 ADC2 IN Mux", "IF_ADC2", "IF_ADC2" },
1789 { "IF1 ADC2 IN Mux", "VAD_ADC", "VAD_ADC" },
1790
1791 { "IF1 ADC2 IN1 Mux", "IF1_ADC2_IN", "IF1 ADC2 IN Mux" },
1792 { "IF1 ADC2 IN1 Mux", "IF1_ADC4", "IF1_ADC4" },
1793
1794 { "IF1_ADC1" , NULL, "IF1 ADC1 IN2 Mux" },
1795 { "IF1_ADC2" , NULL, "IF1 ADC2 IN1 Mux" },
1796
1797 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
1798 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
1799 { "Stereo2 ADC MIX", NULL, "Sto2 ADC MIXL" },
1800 { "Stereo2 ADC MIX", NULL, "Sto2 ADC MIXR" },
1801 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
1802 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
1803
1804 { "RxDP Mux", "IF2 DAC", "IF2 DAC" },
1805 { "RxDP Mux", "IF1 DAC", "IF1 DAC2" },
1806 { "RxDP Mux", "STO1 ADC Mixer", "Stereo1 ADC MIX" },
1807 { "RxDP Mux", "STO2 ADC Mixer", "Stereo2 ADC MIX" },
1808 { "RxDP Mux", "Mono ADC Mixer L", "Mono ADC MIXL" },
1809 { "RxDP Mux", "Mono ADC Mixer R", "Mono ADC MIXR" },
1810 { "RxDP Mux", "DAC1", "DAC MIX" },
1811
1812 { "TDM Data Mux", "Slot 0-1", "Stereo1 ADC MIX" },
1813 { "TDM Data Mux", "Slot 2-3", "Mono ADC MIX" },
1814 { "TDM Data Mux", "Slot 4-5", "Stereo2 ADC MIX" },
1815 { "TDM Data Mux", "Slot 6-7", "IF2 DAC" },
1816
1817 { "DSP UL Mux", "Bypass", "TDM Data Mux" },
1818 { "DSP UL Mux", NULL, "I2S DSP" },
1819 { "DSP DL Mux", "Bypass", "RxDP Mux" },
1820 { "DSP DL Mux", NULL, "I2S DSP" },
1821
1822 { "TxDP_ADC_L", NULL, "DSP UL Mux" },
1823 { "TxDP_ADC_R", NULL, "DSP UL Mux" },
1824 { "TxDC_DAC", NULL, "DSP DL Mux" },
1825
1826 { "TxDP_ADC", NULL, "TxDP_ADC_L" },
1827 { "TxDP_ADC", NULL, "TxDP_ADC_R" },
1828
1829 { "IF1 ADC", NULL, "I2S1" },
1830 { "IF1 ADC", NULL, "IF1_ADC1" },
1831 { "IF1 ADC", NULL, "IF1_ADC2" },
1832 { "IF1 ADC", NULL, "IF_ADC3" },
1833 { "IF1 ADC", NULL, "TxDP_ADC" },
1834
1835 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
1836 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
1837 { "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" },
1838 { "IF2 ADC Mux", "TxDC_DAC", "TxDC_DAC" },
1839 { "IF2 ADC Mux", "TxDP_ADC", "TxDP_ADC" },
1840 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
1841
1842 { "IF2 ADC L", NULL, "IF2 ADC Mux" },
1843 { "IF2 ADC R", NULL, "IF2 ADC Mux" },
1844
1845 { "IF2 ADC", NULL, "I2S2" },
1846 { "IF2 ADC", NULL, "IF2 ADC L" },
1847 { "IF2 ADC", NULL, "IF2 ADC R" },
1848
1849 { "AIF1TX", NULL, "IF1 ADC" },
1850 { "AIF2TX", NULL, "IF2 ADC" },
1851
1852 { "IF1 DAC1", NULL, "AIF1RX" },
1853 { "IF1 DAC2", NULL, "AIF1RX" },
1854 { "IF2 DAC", NULL, "AIF2RX" },
1855
1856 { "IF1 DAC1", NULL, "I2S1" },
1857 { "IF1 DAC2", NULL, "I2S1" },
1858 { "IF2 DAC", NULL, "I2S2" },
1859
1860 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
1861 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
1862 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
1863 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
1864 { "IF2 DAC L", NULL, "IF2 DAC" },
1865 { "IF2 DAC R", NULL, "IF2 DAC" },
1866
1867 { "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
1868 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1869
1870 { "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
1871 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
1872
1873 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
1874 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
1875 { "DAC1 MIXL", NULL, "DAC Stereo1 Filter" },
1876 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
1877 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
1878 { "DAC1 MIXR", NULL, "DAC Stereo1 Filter" },
1879
1880 { "DAC MIX", NULL, "DAC1 MIXL" },
1881 { "DAC MIX", NULL, "DAC1 MIXR" },
1882
1883 { "Audio DSP", NULL, "DAC1 MIXL" },
1884 { "Audio DSP", NULL, "DAC1 MIXR" },
1885
1886 { "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
1887 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
1888 { "DAC L2 Mux", "TxDC DAC", "TxDC_DAC" },
1889 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
1890 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
1891 { "DAC L2 Volume", NULL, "DAC Mono Left Filter" },
1892
1893 { "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
1894 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
1895 { "DAC R2 Mux", "TxDC DAC", "TxDC_DAC" },
1896 { "DAC R2 Mux", "TxDP ADC", "TxDP_ADC" },
1897 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
1898 { "DAC R2 Volume", NULL, "DAC Mono Right Filter" },
1899
1900 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1901 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
1902 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1903 { "Stereo DAC MIXL", NULL, "DAC Stereo1 Filter" },
1904 { "Stereo DAC MIXL", NULL, "DAC L1 Power" },
1905 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1906 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
1907 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1908 { "Stereo DAC MIXR", NULL, "DAC Stereo1 Filter" },
1909 { "Stereo DAC MIXR", NULL, "DAC R1 Power" },
1910
1911 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1912 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1913 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1914 { "Mono DAC MIXL", NULL, "DAC Mono Left Filter" },
1915 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1916 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1917 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1918 { "Mono DAC MIXR", NULL, "DAC Mono Right Filter" },
1919
1920 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
1921 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1922 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1923 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
1924 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1925 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1926
1927 { "DAC L1", NULL, "DAC L1 Power" },
1928 { "DAC L1", NULL, "Stereo DAC MIXL" },
1929 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1930 { "DAC R1", NULL, "DAC R1 Power" },
1931 { "DAC R1", NULL, "Stereo DAC MIXR" },
1932 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1933 { "DAC L2", NULL, "Mono DAC MIXL" },
1934 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1935 { "DAC R2", NULL, "Mono DAC MIXR" },
1936 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
1937
1938 { "OUT MIXL", "BST1 Switch", "BST1" },
1939 { "OUT MIXL", "INL Switch", "INL VOL" },
1940 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
1941 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
1942
1943 { "OUT MIXR", "BST2 Switch", "BST2" },
1944 { "OUT MIXR", "INR Switch", "INR VOL" },
1945 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
1946 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
1947
1948 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
1949 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
1950 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
1951 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
1952
1953 { "DAC 2", NULL, "DAC L2" },
1954 { "DAC 2", NULL, "DAC R2" },
1955 { "DAC 1", NULL, "DAC L1" },
1956 { "DAC 1", NULL, "DAC R1" },
1957 { "HPOVOL", NULL, "HPOVOL MIXL" },
1958 { "HPOVOL", NULL, "HPOVOL MIXR" },
1959 { "HPO MIX", "DAC1 Switch", "DAC 1" },
1960 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
1961
1962 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
1963 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
1964 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
1965 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
1966
1967 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
1968 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
1969 { "PDM1 L Mux", NULL, "PDM1 Power" },
1970 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
1971 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
1972 { "PDM1 R Mux", NULL, "PDM1 Power" },
1973 { "PDM2 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
1974 { "PDM2 L Mux", "Mono DAC", "Mono DAC MIXL" },
1975 { "PDM2 L Mux", NULL, "PDM2 Power" },
1976 { "PDM2 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
1977 { "PDM2 R Mux", "Mono DAC", "Mono DAC MIXR" },
1978 { "PDM2 R Mux", NULL, "PDM2 Power" },
1979
1980 { "HP Amp", NULL, "HPO MIX" },
1981 { "HP Amp", NULL, "Mic Det Power" },
1982 { "HPOL", NULL, "HP Amp" },
1983 { "HPOL", NULL, "HP L Amp" },
1984 { "HPOL", NULL, "Improve HP Amp Drv" },
1985 { "HPOR", NULL, "HP Amp" },
1986 { "HPOR", NULL, "HP R Amp" },
1987 { "HPOR", NULL, "Improve HP Amp Drv" },
1988
1989 { "LOUT Amp", NULL, "LOUT MIX" },
1990 { "LOUT L Playback", "Switch", "LOUT Amp" },
1991 { "LOUT R Playback", "Switch", "LOUT Amp" },
1992 { "LOUTL", NULL, "LOUT L Playback" },
1993 { "LOUTR", NULL, "LOUT R Playback" },
1994 { "LOUTL", NULL, "Improve HP Amp Drv" },
1995 { "LOUTR", NULL, "Improve HP Amp Drv" },
1996
1997 { "PDM1L", NULL, "PDM1 L Mux" },
1998 { "PDM1R", NULL, "PDM1 R Mux" },
1999 { "PDM2L", NULL, "PDM2 L Mux" },
2000 { "PDM2R", NULL, "PDM2 R Mux" },
2001};
2002
2003static int rt5670_hw_params(struct snd_pcm_substream *substream,
2004 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2005{
2006 struct snd_soc_codec *codec = dai->codec;
2007 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2008 unsigned int val_len = 0, val_clk, mask_clk;
2009 int pre_div, bclk_ms, frame_size;
2010
2011 rt5670->lrck[dai->id] = params_rate(params);
2012 pre_div = rl6231_get_clk_info(rt5670->sysclk, rt5670->lrck[dai->id]);
2013 if (pre_div < 0) {
2014 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
2015 rt5670->lrck[dai->id], dai->id);
2016 return -EINVAL;
2017 }
2018 frame_size = snd_soc_params_to_frame_size(params);
2019 if (frame_size < 0) {
2020 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2021 return -EINVAL;
2022 }
2023 bclk_ms = frame_size > 32;
2024 rt5670->bclk[dai->id] = rt5670->lrck[dai->id] * (32 << bclk_ms);
2025
2026 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2027 rt5670->bclk[dai->id], rt5670->lrck[dai->id]);
2028 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2029 bclk_ms, pre_div, dai->id);
2030
2031 switch (params_width(params)) {
2032 case 16:
2033 break;
2034 case 20:
2035 val_len |= RT5670_I2S_DL_20;
2036 break;
2037 case 24:
2038 val_len |= RT5670_I2S_DL_24;
2039 break;
2040 case 8:
2041 val_len |= RT5670_I2S_DL_8;
2042 break;
2043 default:
2044 return -EINVAL;
2045 }
2046
2047 switch (dai->id) {
2048 case RT5670_AIF1:
2049 mask_clk = RT5670_I2S_BCLK_MS1_MASK | RT5670_I2S_PD1_MASK;
2050 val_clk = bclk_ms << RT5670_I2S_BCLK_MS1_SFT |
2051 pre_div << RT5670_I2S_PD1_SFT;
2052 snd_soc_update_bits(codec, RT5670_I2S1_SDP,
2053 RT5670_I2S_DL_MASK, val_len);
2054 snd_soc_update_bits(codec, RT5670_ADDA_CLK1, mask_clk, val_clk);
2055 break;
2056 case RT5670_AIF2:
2057 mask_clk = RT5670_I2S_BCLK_MS2_MASK | RT5670_I2S_PD2_MASK;
2058 val_clk = bclk_ms << RT5670_I2S_BCLK_MS2_SFT |
2059 pre_div << RT5670_I2S_PD2_SFT;
2060 snd_soc_update_bits(codec, RT5670_I2S2_SDP,
2061 RT5670_I2S_DL_MASK, val_len);
2062 snd_soc_update_bits(codec, RT5670_ADDA_CLK1, mask_clk, val_clk);
2063 break;
2064 default:
2065 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2066 return -EINVAL;
2067 }
2068
2069 return 0;
2070}
2071
2072static int rt5670_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2073{
2074 struct snd_soc_codec *codec = dai->codec;
2075 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2076 unsigned int reg_val = 0;
2077
2078 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2079 case SND_SOC_DAIFMT_CBM_CFM:
2080 rt5670->master[dai->id] = 1;
2081 break;
2082 case SND_SOC_DAIFMT_CBS_CFS:
2083 reg_val |= RT5670_I2S_MS_S;
2084 rt5670->master[dai->id] = 0;
2085 break;
2086 default:
2087 return -EINVAL;
2088 }
2089
2090 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2091 case SND_SOC_DAIFMT_NB_NF:
2092 break;
2093 case SND_SOC_DAIFMT_IB_NF:
2094 reg_val |= RT5670_I2S_BP_INV;
2095 break;
2096 default:
2097 return -EINVAL;
2098 }
2099
2100 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2101 case SND_SOC_DAIFMT_I2S:
2102 break;
2103 case SND_SOC_DAIFMT_LEFT_J:
2104 reg_val |= RT5670_I2S_DF_LEFT;
2105 break;
2106 case SND_SOC_DAIFMT_DSP_A:
2107 reg_val |= RT5670_I2S_DF_PCM_A;
2108 break;
2109 case SND_SOC_DAIFMT_DSP_B:
2110 reg_val |= RT5670_I2S_DF_PCM_B;
2111 break;
2112 default:
2113 return -EINVAL;
2114 }
2115
2116 switch (dai->id) {
2117 case RT5670_AIF1:
2118 snd_soc_update_bits(codec, RT5670_I2S1_SDP,
2119 RT5670_I2S_MS_MASK | RT5670_I2S_BP_MASK |
2120 RT5670_I2S_DF_MASK, reg_val);
2121 break;
2122 case RT5670_AIF2:
2123 snd_soc_update_bits(codec, RT5670_I2S2_SDP,
2124 RT5670_I2S_MS_MASK | RT5670_I2S_BP_MASK |
2125 RT5670_I2S_DF_MASK, reg_val);
2126 break;
2127 default:
2128 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2129 return -EINVAL;
2130 }
2131 return 0;
2132}
2133
2134static int rt5670_set_dai_sysclk(struct snd_soc_dai *dai,
2135 int clk_id, unsigned int freq, int dir)
2136{
2137 struct snd_soc_codec *codec = dai->codec;
2138 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2139 unsigned int reg_val = 0;
2140
2141 if (freq == rt5670->sysclk && clk_id == rt5670->sysclk_src)
2142 return 0;
2143
2144 switch (clk_id) {
2145 case RT5670_SCLK_S_MCLK:
2146 reg_val |= RT5670_SCLK_SRC_MCLK;
2147 break;
2148 case RT5670_SCLK_S_PLL1:
2149 reg_val |= RT5670_SCLK_SRC_PLL1;
2150 break;
2151 case RT5670_SCLK_S_RCCLK:
2152 reg_val |= RT5670_SCLK_SRC_RCCLK;
2153 break;
2154 default:
2155 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2156 return -EINVAL;
2157 }
2158 snd_soc_update_bits(codec, RT5670_GLB_CLK,
2159 RT5670_SCLK_SRC_MASK, reg_val);
2160 rt5670->sysclk = freq;
2161 rt5670->sysclk_src = clk_id;
2162
2163 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2164
2165 return 0;
2166}
2167
2168static int rt5670_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2169 unsigned int freq_in, unsigned int freq_out)
2170{
2171 struct snd_soc_codec *codec = dai->codec;
2172 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2173 struct rl6231_pll_code pll_code;
2174 int ret;
2175
2176 if (source == rt5670->pll_src && freq_in == rt5670->pll_in &&
2177 freq_out == rt5670->pll_out)
2178 return 0;
2179
2180 if (!freq_in || !freq_out) {
2181 dev_dbg(codec->dev, "PLL disabled\n");
2182
2183 rt5670->pll_in = 0;
2184 rt5670->pll_out = 0;
2185 snd_soc_update_bits(codec, RT5670_GLB_CLK,
2186 RT5670_SCLK_SRC_MASK, RT5670_SCLK_SRC_MCLK);
2187 return 0;
2188 }
2189
2190 switch (source) {
2191 case RT5670_PLL1_S_MCLK:
2192 snd_soc_update_bits(codec, RT5670_GLB_CLK,
2193 RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_MCLK);
2194 break;
2195 case RT5670_PLL1_S_BCLK1:
2196 case RT5670_PLL1_S_BCLK2:
2197 case RT5670_PLL1_S_BCLK3:
2198 case RT5670_PLL1_S_BCLK4:
2199 switch (dai->id) {
2200 case RT5670_AIF1:
2201 snd_soc_update_bits(codec, RT5670_GLB_CLK,
2202 RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_BCLK1);
2203 break;
2204 case RT5670_AIF2:
2205 snd_soc_update_bits(codec, RT5670_GLB_CLK,
2206 RT5670_PLL1_SRC_MASK, RT5670_PLL1_SRC_BCLK2);
2207 break;
2208 default:
2209 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2210 return -EINVAL;
2211 }
2212 break;
2213 default:
2214 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2215 return -EINVAL;
2216 }
2217
2218 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2219 if (ret < 0) {
2220 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2221 return ret;
2222 }
2223
2224 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2225 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2226 pll_code.n_code, pll_code.k_code);
2227
2228 snd_soc_write(codec, RT5670_PLL_CTRL1,
2229 pll_code.n_code << RT5670_PLL_N_SFT | pll_code.k_code);
2230 snd_soc_write(codec, RT5670_PLL_CTRL2,
2231 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5670_PLL_M_SFT |
2232 pll_code.m_bp << RT5670_PLL_M_BP_SFT);
2233
2234 rt5670->pll_in = freq_in;
2235 rt5670->pll_out = freq_out;
2236 rt5670->pll_src = source;
2237
2238 return 0;
2239}
2240
2241static int rt5670_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2242 unsigned int rx_mask, int slots, int slot_width)
2243{
2244 struct snd_soc_codec *codec = dai->codec;
2245 unsigned int val = 0;
2246
2247 if (rx_mask || tx_mask)
2248 val |= (1 << 14);
2249
2250 switch (slots) {
2251 case 4:
2252 val |= (1 << 12);
2253 break;
2254 case 6:
2255 val |= (2 << 12);
2256 break;
2257 case 8:
2258 val |= (3 << 12);
2259 break;
2260 case 2:
2261 break;
2262 default:
2263 return -EINVAL;
2264 }
2265
2266 switch (slot_width) {
2267 case 20:
2268 val |= (1 << 10);
2269 break;
2270 case 24:
2271 val |= (2 << 10);
2272 break;
2273 case 32:
2274 val |= (3 << 10);
2275 break;
2276 case 16:
2277 break;
2278 default:
2279 return -EINVAL;
2280 }
2281
2282 snd_soc_update_bits(codec, RT5670_TDM_CTRL_1, 0x7c00, val);
2283
2284 return 0;
2285}
2286
2287static int rt5670_set_bias_level(struct snd_soc_codec *codec,
2288 enum snd_soc_bias_level level)
2289{
2290 switch (level) {
2291 case SND_SOC_BIAS_PREPARE:
2292 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
2293 snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
2294 RT5670_PWR_VREF1 | RT5670_PWR_MB |
2295 RT5670_PWR_BG | RT5670_PWR_VREF2,
2296 RT5670_PWR_VREF1 | RT5670_PWR_MB |
2297 RT5670_PWR_BG | RT5670_PWR_VREF2);
2298 mdelay(10);
2299 snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
2300 RT5670_PWR_FV1 | RT5670_PWR_FV2,
2301 RT5670_PWR_FV1 | RT5670_PWR_FV2);
2302 snd_soc_update_bits(codec, RT5670_CHARGE_PUMP,
2303 RT5670_OSW_L_MASK | RT5670_OSW_R_MASK,
2304 RT5670_OSW_L_DIS | RT5670_OSW_R_DIS);
2305 snd_soc_update_bits(codec, RT5670_DIG_MISC, 0x1, 0x1);
2306 snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
2307 RT5670_LDO_SEL_MASK, 0x3);
2308 }
2309 break;
2310 case SND_SOC_BIAS_STANDBY:
2311 snd_soc_write(codec, RT5670_PWR_DIG1, 0x0000);
2312 snd_soc_write(codec, RT5670_PWR_DIG2, 0x0001);
2313 snd_soc_write(codec, RT5670_PWR_VOL, 0x0000);
2314 snd_soc_write(codec, RT5670_PWR_MIXER, 0x0001);
2315 snd_soc_write(codec, RT5670_PWR_ANLG1, 0x2800);
2316 snd_soc_write(codec, RT5670_PWR_ANLG2, 0x0004);
2317 snd_soc_update_bits(codec, RT5670_DIG_MISC, 0x1, 0x0);
2318 snd_soc_update_bits(codec, RT5670_PWR_ANLG1,
2319 RT5670_LDO_SEL_MASK, 0x1);
2320 break;
2321
2322 default:
2323 break;
2324 }
2325 codec->dapm.bias_level = level;
2326
2327 return 0;
2328}
2329
2330static int rt5670_probe(struct snd_soc_codec *codec)
2331{
2332 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2333
2334 rt5670->codec = codec;
2335
2336 return 0;
2337}
2338
2339static int rt5670_remove(struct snd_soc_codec *codec)
2340{
2341 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2342
2343 regmap_write(rt5670->regmap, RT5670_RESET, 0);
2344 return 0;
2345}
2346
2347#ifdef CONFIG_PM
2348static int rt5670_suspend(struct snd_soc_codec *codec)
2349{
2350 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2351
2352 regcache_cache_only(rt5670->regmap, true);
2353 regcache_mark_dirty(rt5670->regmap);
2354 return 0;
2355}
2356
2357static int rt5670_resume(struct snd_soc_codec *codec)
2358{
2359 struct rt5670_priv *rt5670 = snd_soc_codec_get_drvdata(codec);
2360
2361 regcache_cache_only(rt5670->regmap, false);
2362 regcache_sync(rt5670->regmap);
2363
2364 return 0;
2365}
2366#else
2367#define rt5670_suspend NULL
2368#define rt5670_resume NULL
2369#endif
2370
2371#define RT5670_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2372#define RT5670_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2373 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2374
2375static struct snd_soc_dai_ops rt5670_aif_dai_ops = {
2376 .hw_params = rt5670_hw_params,
2377 .set_fmt = rt5670_set_dai_fmt,
2378 .set_sysclk = rt5670_set_dai_sysclk,
2379 .set_tdm_slot = rt5670_set_tdm_slot,
2380 .set_pll = rt5670_set_dai_pll,
2381};
2382
2383static struct snd_soc_dai_driver rt5670_dai[] = {
2384 {
2385 .name = "rt5670-aif1",
2386 .id = RT5670_AIF1,
2387 .playback = {
2388 .stream_name = "AIF1 Playback",
2389 .channels_min = 1,
2390 .channels_max = 2,
2391 .rates = RT5670_STEREO_RATES,
2392 .formats = RT5670_FORMATS,
2393 },
2394 .capture = {
2395 .stream_name = "AIF1 Capture",
2396 .channels_min = 1,
2397 .channels_max = 2,
2398 .rates = RT5670_STEREO_RATES,
2399 .formats = RT5670_FORMATS,
2400 },
2401 .ops = &rt5670_aif_dai_ops,
2402 },
2403 {
2404 .name = "rt5670-aif2",
2405 .id = RT5670_AIF2,
2406 .playback = {
2407 .stream_name = "AIF2 Playback",
2408 .channels_min = 1,
2409 .channels_max = 2,
2410 .rates = RT5670_STEREO_RATES,
2411 .formats = RT5670_FORMATS,
2412 },
2413 .capture = {
2414 .stream_name = "AIF2 Capture",
2415 .channels_min = 1,
2416 .channels_max = 2,
2417 .rates = RT5670_STEREO_RATES,
2418 .formats = RT5670_FORMATS,
2419 },
2420 .ops = &rt5670_aif_dai_ops,
2421 },
2422};
2423
2424static struct snd_soc_codec_driver soc_codec_dev_rt5670 = {
2425 .probe = rt5670_probe,
2426 .remove = rt5670_remove,
2427 .suspend = rt5670_suspend,
2428 .resume = rt5670_resume,
2429 .set_bias_level = rt5670_set_bias_level,
2430 .idle_bias_off = true,
2431 .controls = rt5670_snd_controls,
2432 .num_controls = ARRAY_SIZE(rt5670_snd_controls),
2433 .dapm_widgets = rt5670_dapm_widgets,
2434 .num_dapm_widgets = ARRAY_SIZE(rt5670_dapm_widgets),
2435 .dapm_routes = rt5670_dapm_routes,
2436 .num_dapm_routes = ARRAY_SIZE(rt5670_dapm_routes),
2437};
2438
2439static const struct regmap_config rt5670_regmap = {
2440 .reg_bits = 8,
2441 .val_bits = 16,
2442 .max_register = RT5670_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5670_ranges) *
2443 RT5670_PR_SPACING),
2444 .volatile_reg = rt5670_volatile_register,
2445 .readable_reg = rt5670_readable_register,
2446 .cache_type = REGCACHE_RBTREE,
2447 .reg_defaults = rt5670_reg,
2448 .num_reg_defaults = ARRAY_SIZE(rt5670_reg),
2449 .ranges = rt5670_ranges,
2450 .num_ranges = ARRAY_SIZE(rt5670_ranges),
2451};
2452
2453static const struct i2c_device_id rt5670_i2c_id[] = {
2454 { "rt5670", 0 },
2455 { }
2456};
2457MODULE_DEVICE_TABLE(i2c, rt5670_i2c_id);
2458
2459static int rt5670_i2c_probe(struct i2c_client *i2c,
2460 const struct i2c_device_id *id)
2461{
2462 struct rt5670_platform_data *pdata = dev_get_platdata(&i2c->dev);
2463 struct rt5670_priv *rt5670;
2464 int ret;
2465 unsigned int val;
2466
2467 rt5670 = devm_kzalloc(&i2c->dev,
2468 sizeof(struct rt5670_priv),
2469 GFP_KERNEL);
2470 if (NULL == rt5670)
2471 return -ENOMEM;
2472
2473 i2c_set_clientdata(i2c, rt5670);
2474
2475 if (pdata)
2476 rt5670->pdata = *pdata;
2477
2478 rt5670->regmap = devm_regmap_init_i2c(i2c, &rt5670_regmap);
2479 if (IS_ERR(rt5670->regmap)) {
2480 ret = PTR_ERR(rt5670->regmap);
2481 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2482 ret);
2483 return ret;
2484 }
2485
2486 regmap_read(rt5670->regmap, RT5670_VENDOR_ID2, &val);
2487 if (val != RT5670_DEVICE_ID) {
2488 dev_err(&i2c->dev,
2489 "Device with ID register %x is not rt5670/72\n", val);
2490 return -ENODEV;
2491 }
2492
2493 regmap_write(rt5670->regmap, RT5670_RESET, 0);
2494 regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
2495 RT5670_PWR_HP_L | RT5670_PWR_HP_R |
2496 RT5670_PWR_VREF2, RT5670_PWR_VREF2);
2497 msleep(100);
2498
2499 regmap_write(rt5670->regmap, RT5670_RESET, 0);
2500
2501 ret = regmap_register_patch(rt5670->regmap, init_list,
2502 ARRAY_SIZE(init_list));
2503 if (ret != 0)
2504 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2505
2506 if (rt5670->pdata.in2_diff)
2507 regmap_update_bits(rt5670->regmap, RT5670_IN2,
2508 RT5670_IN_DF2, RT5670_IN_DF2);
2509
2510 if (i2c->irq) {
2511 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
2512 RT5670_GP1_PIN_MASK, RT5670_GP1_PIN_IRQ);
2513 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL2,
2514 RT5670_GP1_PF_MASK, RT5670_GP1_PF_OUT);
2515
2516 }
2517
2518 if (rt5670->pdata.jd_mode) {
2519 regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1,
2520 RT5670_PWR_MB, RT5670_PWR_MB);
2521 regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG2,
2522 RT5670_PWR_JD1, RT5670_PWR_JD1);
2523 regmap_update_bits(rt5670->regmap, RT5670_IRQ_CTRL1,
2524 RT5670_JD1_1_EN_MASK, RT5670_JD1_1_EN);
2525 regmap_update_bits(rt5670->regmap, RT5670_JD_CTRL3,
2526 RT5670_JD_TRI_CBJ_SEL_MASK |
2527 RT5670_JD_TRI_HPO_SEL_MASK,
2528 RT5670_JD_CBJ_JD1_1 | RT5670_JD_HPO_JD1_1);
2529 switch (rt5670->pdata.jd_mode) {
2530 case 1:
2531 regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
2532 RT5670_JD1_MODE_MASK,
2533 RT5670_JD1_MODE_0);
2534 break;
2535 case 2:
2536 regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
2537 RT5670_JD1_MODE_MASK,
2538 RT5670_JD1_MODE_1);
2539 break;
2540 case 3:
2541 regmap_update_bits(rt5670->regmap, RT5670_A_JD_CTRL1,
2542 RT5670_JD1_MODE_MASK,
2543 RT5670_JD1_MODE_2);
2544 break;
2545 default:
2546 break;
2547 }
2548 }
2549
2550 if (rt5670->pdata.dmic_en) {
2551 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
2552 RT5670_GP2_PIN_MASK,
2553 RT5670_GP2_PIN_DMIC1_SCL);
2554
2555 switch (rt5670->pdata.dmic1_data_pin) {
2556 case RT5670_DMIC_DATA_IN2P:
2557 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
2558 RT5670_DMIC_1_DP_MASK,
2559 RT5670_DMIC_1_DP_IN2P);
2560 break;
2561
2562 case RT5670_DMIC_DATA_GPIO6:
2563 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
2564 RT5670_DMIC_1_DP_MASK,
2565 RT5670_DMIC_1_DP_GPIO6);
2566 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
2567 RT5670_GP6_PIN_MASK,
2568 RT5670_GP6_PIN_DMIC1_SDA);
2569 break;
2570
2571 case RT5670_DMIC_DATA_GPIO7:
2572 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
2573 RT5670_DMIC_1_DP_MASK,
2574 RT5670_DMIC_1_DP_GPIO7);
2575 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
2576 RT5670_GP7_PIN_MASK,
2577 RT5670_GP7_PIN_DMIC1_SDA);
2578 break;
2579
2580 default:
2581 break;
2582 }
2583
2584 switch (rt5670->pdata.dmic2_data_pin) {
2585 case RT5670_DMIC_DATA_IN3N:
2586 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
2587 RT5670_DMIC_2_DP_MASK,
2588 RT5670_DMIC_2_DP_IN3N);
2589 break;
2590
2591 case RT5670_DMIC_DATA_GPIO8:
2592 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL1,
2593 RT5670_DMIC_2_DP_MASK,
2594 RT5670_DMIC_2_DP_GPIO8);
2595 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
2596 RT5670_GP8_PIN_MASK,
2597 RT5670_GP8_PIN_DMIC2_SDA);
2598 break;
2599
2600 default:
2601 break;
2602 }
2603
2604 switch (rt5670->pdata.dmic3_data_pin) {
2605 case RT5670_DMIC_DATA_GPIO5:
2606 regmap_update_bits(rt5670->regmap, RT5670_DMIC_CTRL2,
2607 RT5670_DMIC_3_DP_MASK,
2608 RT5670_DMIC_3_DP_GPIO5);
2609 regmap_update_bits(rt5670->regmap, RT5670_GPIO_CTRL1,
2610 RT5670_GP5_PIN_MASK,
2611 RT5670_GP5_PIN_DMIC3_SDA);
2612 break;
2613
2614 case RT5670_DMIC_DATA_GPIO9:
2615 case RT5670_DMIC_DATA_GPIO10:
2616 dev_err(&i2c->dev,
2617 "Always use GPIO5 as DMIC3 data pin\n");
2618 break;
2619
2620 default:
2621 break;
2622 }
2623
2624 }
2625
2626 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5670,
2627 rt5670_dai, ARRAY_SIZE(rt5670_dai));
2628 if (ret < 0)
2629 goto err;
2630
2631 return 0;
2632err:
2633 return ret;
2634}
2635
2636static int rt5670_i2c_remove(struct i2c_client *i2c)
2637{
2638 snd_soc_unregister_codec(&i2c->dev);
2639
2640 return 0;
2641}
2642
2643static struct i2c_driver rt5670_i2c_driver = {
2644 .driver = {
2645 .name = "rt5670",
2646 .owner = THIS_MODULE,
2647 },
2648 .probe = rt5670_i2c_probe,
2649 .remove = rt5670_i2c_remove,
2650 .id_table = rt5670_i2c_id,
2651};
2652
2653module_i2c_driver(rt5670_i2c_driver);
2654
2655MODULE_DESCRIPTION("ASoC RT5670 driver");
2656MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2657MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rt5670.h b/sound/soc/codecs/rt5670.h
new file mode 100644
index 000000000000..a0b5c855b492
--- /dev/null
+++ b/sound/soc/codecs/rt5670.h
@@ -0,0 +1,2000 @@
1/*
2 * rt5670.h -- RT5670 ALSA SoC audio driver
3 *
4 * Copyright 2014 Realtek Microelectronics
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5670_H__
13#define __RT5670_H__
14
15#include <sound/rt5670.h>
16
17/* Info */
18#define RT5670_RESET 0x00
19#define RT5670_VENDOR_ID 0xfd
20#define RT5670_VENDOR_ID1 0xfe
21#define RT5670_VENDOR_ID2 0xff
22/* I/O - Output */
23#define RT5670_HP_VOL 0x02
24#define RT5670_LOUT1 0x03
25/* I/O - Input */
26#define RT5670_CJ_CTRL1 0x0a
27#define RT5670_CJ_CTRL2 0x0b
28#define RT5670_CJ_CTRL3 0x0c
29#define RT5670_IN2 0x0e
30#define RT5670_INL1_INR1_VOL 0x0f
31/* I/O - ADC/DAC/DMIC */
32#define RT5670_DAC1_DIG_VOL 0x19
33#define RT5670_DAC2_DIG_VOL 0x1a
34#define RT5670_DAC_CTRL 0x1b
35#define RT5670_STO1_ADC_DIG_VOL 0x1c
36#define RT5670_MONO_ADC_DIG_VOL 0x1d
37#define RT5670_ADC_BST_VOL1 0x1e
38#define RT5670_STO2_ADC_DIG_VOL 0x1f
39/* Mixer - D-D */
40#define RT5670_ADC_BST_VOL2 0x20
41#define RT5670_STO2_ADC_MIXER 0x26
42#define RT5670_STO1_ADC_MIXER 0x27
43#define RT5670_MONO_ADC_MIXER 0x28
44#define RT5670_AD_DA_MIXER 0x29
45#define RT5670_STO_DAC_MIXER 0x2a
46#define RT5670_DD_MIXER 0x2b
47#define RT5670_DIG_MIXER 0x2c
48#define RT5670_DSP_PATH1 0x2d
49#define RT5670_DSP_PATH2 0x2e
50#define RT5670_DIG_INF1_DATA 0x2f
51#define RT5670_DIG_INF2_DATA 0x30
52/* Mixer - PDM */
53#define RT5670_PDM_OUT_CTRL 0x31
54#define RT5670_PDM_DATA_CTRL1 0x32
55#define RT5670_PDM1_DATA_CTRL2 0x33
56#define RT5670_PDM1_DATA_CTRL3 0x34
57#define RT5670_PDM1_DATA_CTRL4 0x35
58#define RT5670_PDM2_DATA_CTRL2 0x36
59#define RT5670_PDM2_DATA_CTRL3 0x37
60#define RT5670_PDM2_DATA_CTRL4 0x38
61/* Mixer - ADC */
62#define RT5670_REC_L1_MIXER 0x3b
63#define RT5670_REC_L2_MIXER 0x3c
64#define RT5670_REC_R1_MIXER 0x3d
65#define RT5670_REC_R2_MIXER 0x3e
66/* Mixer - DAC */
67#define RT5670_HPO_MIXER 0x45
68#define RT5670_MONO_MIXER 0x4c
69#define RT5670_OUT_L1_MIXER 0x4f
70#define RT5670_OUT_R1_MIXER 0x52
71#define RT5670_LOUT_MIXER 0x53
72/* Power */
73#define RT5670_PWR_DIG1 0x61
74#define RT5670_PWR_DIG2 0x62
75#define RT5670_PWR_ANLG1 0x63
76#define RT5670_PWR_ANLG2 0x64
77#define RT5670_PWR_MIXER 0x65
78#define RT5670_PWR_VOL 0x66
79/* Private Register Control */
80#define RT5670_PRIV_INDEX 0x6a
81#define RT5670_PRIV_DATA 0x6c
82/* Format - ADC/DAC */
83#define RT5670_I2S4_SDP 0x6f
84#define RT5670_I2S1_SDP 0x70
85#define RT5670_I2S2_SDP 0x71
86#define RT5670_I2S3_SDP 0x72
87#define RT5670_ADDA_CLK1 0x73
88#define RT5670_ADDA_CLK2 0x74
89#define RT5670_DMIC_CTRL1 0x75
90#define RT5670_DMIC_CTRL2 0x76
91/* Format - TDM Control */
92#define RT5670_TDM_CTRL_1 0x77
93#define RT5670_TDM_CTRL_2 0x78
94#define RT5670_TDM_CTRL_3 0x79
95
96/* Function - Analog */
97#define RT5670_DSP_CLK 0x7f
98#define RT5670_GLB_CLK 0x80
99#define RT5670_PLL_CTRL1 0x81
100#define RT5670_PLL_CTRL2 0x82
101#define RT5670_ASRC_1 0x83
102#define RT5670_ASRC_2 0x84
103#define RT5670_ASRC_3 0x85
104#define RT5670_ASRC_4 0x86
105#define RT5670_ASRC_5 0x87
106#define RT5670_ASRC_7 0x89
107#define RT5670_ASRC_8 0x8a
108#define RT5670_ASRC_9 0x8b
109#define RT5670_ASRC_10 0x8c
110#define RT5670_ASRC_11 0x8d
111#define RT5670_DEPOP_M1 0x8e
112#define RT5670_DEPOP_M2 0x8f
113#define RT5670_DEPOP_M3 0x90
114#define RT5670_CHARGE_PUMP 0x91
115#define RT5670_MICBIAS 0x93
116#define RT5670_A_JD_CTRL1 0x94
117#define RT5670_A_JD_CTRL2 0x95
118#define RT5670_ASRC_12 0x97
119#define RT5670_ASRC_13 0x98
120#define RT5670_ASRC_14 0x99
121#define RT5670_VAD_CTRL1 0x9a
122#define RT5670_VAD_CTRL2 0x9b
123#define RT5670_VAD_CTRL3 0x9c
124#define RT5670_VAD_CTRL4 0x9d
125#define RT5670_VAD_CTRL5 0x9e
126/* Function - Digital */
127#define RT5670_ADC_EQ_CTRL1 0xae
128#define RT5670_ADC_EQ_CTRL2 0xaf
129#define RT5670_EQ_CTRL1 0xb0
130#define RT5670_EQ_CTRL2 0xb1
131#define RT5670_ALC_DRC_CTRL1 0xb2
132#define RT5670_ALC_DRC_CTRL2 0xb3
133#define RT5670_ALC_CTRL_1 0xb4
134#define RT5670_ALC_CTRL_2 0xb5
135#define RT5670_ALC_CTRL_3 0xb6
136#define RT5670_ALC_CTRL_4 0xb7
137#define RT5670_JD_CTRL 0xbb
138#define RT5670_IRQ_CTRL1 0xbd
139#define RT5670_IRQ_CTRL2 0xbe
140#define RT5670_INT_IRQ_ST 0xbf
141#define RT5670_GPIO_CTRL1 0xc0
142#define RT5670_GPIO_CTRL2 0xc1
143#define RT5670_GPIO_CTRL3 0xc2
144#define RT5670_SCRABBLE_FUN 0xcd
145#define RT5670_SCRABBLE_CTRL 0xce
146#define RT5670_BASE_BACK 0xcf
147#define RT5670_MP3_PLUS1 0xd0
148#define RT5670_MP3_PLUS2 0xd1
149#define RT5670_ADJ_HPF1 0xd3
150#define RT5670_ADJ_HPF2 0xd4
151#define RT5670_HP_CALIB_AMP_DET 0xd6
152#define RT5670_SV_ZCD1 0xd9
153#define RT5670_SV_ZCD2 0xda
154#define RT5670_IL_CMD 0xdb
155#define RT5670_IL_CMD2 0xdc
156#define RT5670_IL_CMD3 0xdd
157#define RT5670_DRC_HL_CTRL1 0xe6
158#define RT5670_DRC_HL_CTRL2 0xe7
159#define RT5670_ADC_MONO_HP_CTRL1 0xec
160#define RT5670_ADC_MONO_HP_CTRL2 0xed
161#define RT5670_ADC_STO2_HP_CTRL1 0xee
162#define RT5670_ADC_STO2_HP_CTRL2 0xef
163#define RT5670_JD_CTRL3 0xf8
164#define RT5670_JD_CTRL4 0xf9
165/* General Control */
166#define RT5670_DIG_MISC 0xfa
167#define RT5670_GEN_CTRL2 0xfb
168#define RT5670_GEN_CTRL3 0xfc
169
170
171/* Index of Codec Private Register definition */
172#define RT5670_DIG_VOL 0x00
173#define RT5670_PR_ALC_CTRL_1 0x01
174#define RT5670_PR_ALC_CTRL_2 0x02
175#define RT5670_PR_ALC_CTRL_3 0x03
176#define RT5670_PR_ALC_CTRL_4 0x04
177#define RT5670_PR_ALC_CTRL_5 0x05
178#define RT5670_PR_ALC_CTRL_6 0x06
179#define RT5670_BIAS_CUR1 0x12
180#define RT5670_BIAS_CUR3 0x14
181#define RT5670_CLSD_INT_REG1 0x1c
182#define RT5670_MAMP_INT_REG2 0x37
183#define RT5670_CHOP_DAC_ADC 0x3d
184#define RT5670_MIXER_INT_REG 0x3f
185#define RT5670_3D_SPK 0x63
186#define RT5670_WND_1 0x6c
187#define RT5670_WND_2 0x6d
188#define RT5670_WND_3 0x6e
189#define RT5670_WND_4 0x6f
190#define RT5670_WND_5 0x70
191#define RT5670_WND_8 0x73
192#define RT5670_DIP_SPK_INF 0x75
193#define RT5670_HP_DCC_INT1 0x77
194#define RT5670_EQ_BW_LOP 0xa0
195#define RT5670_EQ_GN_LOP 0xa1
196#define RT5670_EQ_FC_BP1 0xa2
197#define RT5670_EQ_BW_BP1 0xa3
198#define RT5670_EQ_GN_BP1 0xa4
199#define RT5670_EQ_FC_BP2 0xa5
200#define RT5670_EQ_BW_BP2 0xa6
201#define RT5670_EQ_GN_BP2 0xa7
202#define RT5670_EQ_FC_BP3 0xa8
203#define RT5670_EQ_BW_BP3 0xa9
204#define RT5670_EQ_GN_BP3 0xaa
205#define RT5670_EQ_FC_BP4 0xab
206#define RT5670_EQ_BW_BP4 0xac
207#define RT5670_EQ_GN_BP4 0xad
208#define RT5670_EQ_FC_HIP1 0xae
209#define RT5670_EQ_GN_HIP1 0xaf
210#define RT5670_EQ_FC_HIP2 0xb0
211#define RT5670_EQ_BW_HIP2 0xb1
212#define RT5670_EQ_GN_HIP2 0xb2
213#define RT5670_EQ_PRE_VOL 0xb3
214#define RT5670_EQ_PST_VOL 0xb4
215
216
217/* global definition */
218#define RT5670_L_MUTE (0x1 << 15)
219#define RT5670_L_MUTE_SFT 15
220#define RT5670_VOL_L_MUTE (0x1 << 14)
221#define RT5670_VOL_L_SFT 14
222#define RT5670_R_MUTE (0x1 << 7)
223#define RT5670_R_MUTE_SFT 7
224#define RT5670_VOL_R_MUTE (0x1 << 6)
225#define RT5670_VOL_R_SFT 6
226#define RT5670_L_VOL_MASK (0x3f << 8)
227#define RT5670_L_VOL_SFT 8
228#define RT5670_R_VOL_MASK (0x3f)
229#define RT5670_R_VOL_SFT 0
230
231/* Combo Jack Control 1 (0x0a) */
232#define RT5670_CBJ_BST1_MASK (0xf << 12)
233#define RT5670_CBJ_BST1_SFT (12)
234#define RT5670_CBJ_JD_HP_EN (0x1 << 9)
235#define RT5670_CBJ_JD_MIC_EN (0x1 << 8)
236#define RT5670_CBJ_BST1_EN (0x1 << 2)
237
238/* Combo Jack Control 1 (0x0b) */
239#define RT5670_CBJ_MN_JD (0x1 << 12)
240#define RT5670_CAPLESS_EN (0x1 << 11)
241#define RT5670_CBJ_DET_MODE (0x1 << 7)
242
243/* IN2 Control (0x0e) */
244#define RT5670_BST_MASK1 (0xf<<12)
245#define RT5670_BST_SFT1 12
246#define RT5670_BST_MASK2 (0xf<<8)
247#define RT5670_BST_SFT2 8
248#define RT5670_IN_DF1 (0x1 << 7)
249#define RT5670_IN_SFT1 7
250#define RT5670_IN_DF2 (0x1 << 6)
251#define RT5670_IN_SFT2 6
252
253/* INL and INR Volume Control (0x0f) */
254#define RT5670_INL_SEL_MASK (0x1 << 15)
255#define RT5670_INL_SEL_SFT 15
256#define RT5670_INL_SEL_IN4P (0x0 << 15)
257#define RT5670_INL_SEL_MONOP (0x1 << 15)
258#define RT5670_INL_VOL_MASK (0x1f << 8)
259#define RT5670_INL_VOL_SFT 8
260#define RT5670_INR_SEL_MASK (0x1 << 7)
261#define RT5670_INR_SEL_SFT 7
262#define RT5670_INR_SEL_IN4N (0x0 << 7)
263#define RT5670_INR_SEL_MONON (0x1 << 7)
264#define RT5670_INR_VOL_MASK (0x1f)
265#define RT5670_INR_VOL_SFT 0
266
267/* Sidetone Control (0x18) */
268#define RT5670_ST_SEL_MASK (0x7 << 9)
269#define RT5670_ST_SEL_SFT 9
270#define RT5670_M_ST_DACR2 (0x1 << 8)
271#define RT5670_M_ST_DACR2_SFT 8
272#define RT5670_M_ST_DACL2 (0x1 << 7)
273#define RT5670_M_ST_DACL2_SFT 7
274#define RT5670_ST_EN (0x1 << 6)
275#define RT5670_ST_EN_SFT 6
276
277/* DAC1 Digital Volume (0x19) */
278#define RT5670_DAC_L1_VOL_MASK (0xff << 8)
279#define RT5670_DAC_L1_VOL_SFT 8
280#define RT5670_DAC_R1_VOL_MASK (0xff)
281#define RT5670_DAC_R1_VOL_SFT 0
282
283/* DAC2 Digital Volume (0x1a) */
284#define RT5670_DAC_L2_VOL_MASK (0xff << 8)
285#define RT5670_DAC_L2_VOL_SFT 8
286#define RT5670_DAC_R2_VOL_MASK (0xff)
287#define RT5670_DAC_R2_VOL_SFT 0
288
289/* DAC2 Control (0x1b) */
290#define RT5670_M_DAC_L2_VOL (0x1 << 13)
291#define RT5670_M_DAC_L2_VOL_SFT 13
292#define RT5670_M_DAC_R2_VOL (0x1 << 12)
293#define RT5670_M_DAC_R2_VOL_SFT 12
294#define RT5670_DAC2_L_SEL_MASK (0x7 << 4)
295#define RT5670_DAC2_L_SEL_SFT 4
296#define RT5670_DAC2_R_SEL_MASK (0x7 << 0)
297#define RT5670_DAC2_R_SEL_SFT 0
298
299/* ADC Digital Volume Control (0x1c) */
300#define RT5670_ADC_L_VOL_MASK (0x7f << 8)
301#define RT5670_ADC_L_VOL_SFT 8
302#define RT5670_ADC_R_VOL_MASK (0x7f)
303#define RT5670_ADC_R_VOL_SFT 0
304
305/* Mono ADC Digital Volume Control (0x1d) */
306#define RT5670_MONO_ADC_L_VOL_MASK (0x7f << 8)
307#define RT5670_MONO_ADC_L_VOL_SFT 8
308#define RT5670_MONO_ADC_R_VOL_MASK (0x7f)
309#define RT5670_MONO_ADC_R_VOL_SFT 0
310
311/* ADC Boost Volume Control (0x1e) */
312#define RT5670_STO1_ADC_L_BST_MASK (0x3 << 14)
313#define RT5670_STO1_ADC_L_BST_SFT 14
314#define RT5670_STO1_ADC_R_BST_MASK (0x3 << 12)
315#define RT5670_STO1_ADC_R_BST_SFT 12
316#define RT5670_STO1_ADC_COMP_MASK (0x3 << 10)
317#define RT5670_STO1_ADC_COMP_SFT 10
318#define RT5670_STO2_ADC_L_BST_MASK (0x3 << 8)
319#define RT5670_STO2_ADC_L_BST_SFT 8
320#define RT5670_STO2_ADC_R_BST_MASK (0x3 << 6)
321#define RT5670_STO2_ADC_R_BST_SFT 6
322#define RT5670_STO2_ADC_COMP_MASK (0x3 << 4)
323#define RT5670_STO2_ADC_COMP_SFT 4
324
325/* Stereo2 ADC Mixer Control (0x26) */
326#define RT5670_STO2_ADC_SRC_MASK (0x1 << 15)
327#define RT5670_STO2_ADC_SRC_SFT 15
328
329/* Stereo ADC Mixer Control (0x26 0x27) */
330#define RT5670_M_ADC_L1 (0x1 << 14)
331#define RT5670_M_ADC_L1_SFT 14
332#define RT5670_M_ADC_L2 (0x1 << 13)
333#define RT5670_M_ADC_L2_SFT 13
334#define RT5670_ADC_1_SRC_MASK (0x1 << 12)
335#define RT5670_ADC_1_SRC_SFT 12
336#define RT5670_ADC_1_SRC_ADC (0x1 << 12)
337#define RT5670_ADC_1_SRC_DACMIX (0x0 << 12)
338#define RT5670_ADC_2_SRC_MASK (0x1 << 11)
339#define RT5670_ADC_2_SRC_SFT 11
340#define RT5670_ADC_SRC_MASK (0x1 << 10)
341#define RT5670_ADC_SRC_SFT 10
342#define RT5670_DMIC_SRC_MASK (0x3 << 8)
343#define RT5670_DMIC_SRC_SFT 8
344#define RT5670_M_ADC_R1 (0x1 << 6)
345#define RT5670_M_ADC_R1_SFT 6
346#define RT5670_M_ADC_R2 (0x1 << 5)
347#define RT5670_M_ADC_R2_SFT 5
348#define RT5670_DMIC3_SRC_MASK (0x1 << 1)
349#define RT5670_DMIC3_SRC_SFT 0
350
351/* Mono ADC Mixer Control (0x28) */
352#define RT5670_M_MONO_ADC_L1 (0x1 << 14)
353#define RT5670_M_MONO_ADC_L1_SFT 14
354#define RT5670_M_MONO_ADC_L2 (0x1 << 13)
355#define RT5670_M_MONO_ADC_L2_SFT 13
356#define RT5670_MONO_ADC_L1_SRC_MASK (0x1 << 12)
357#define RT5670_MONO_ADC_L1_SRC_SFT 12
358#define RT5670_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
359#define RT5670_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
360#define RT5670_MONO_ADC_L2_SRC_MASK (0x1 << 11)
361#define RT5670_MONO_ADC_L2_SRC_SFT 11
362#define RT5670_MONO_ADC_L_SRC_MASK (0x1 << 10)
363#define RT5670_MONO_ADC_L_SRC_SFT 10
364#define RT5670_MONO_DMIC_L_SRC_MASK (0x3 << 8)
365#define RT5670_MONO_DMIC_L_SRC_SFT 8
366#define RT5670_M_MONO_ADC_R1 (0x1 << 6)
367#define RT5670_M_MONO_ADC_R1_SFT 6
368#define RT5670_M_MONO_ADC_R2 (0x1 << 5)
369#define RT5670_M_MONO_ADC_R2_SFT 5
370#define RT5670_MONO_ADC_R1_SRC_MASK (0x1 << 4)
371#define RT5670_MONO_ADC_R1_SRC_SFT 4
372#define RT5670_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
373#define RT5670_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
374#define RT5670_MONO_ADC_R2_SRC_MASK (0x1 << 3)
375#define RT5670_MONO_ADC_R2_SRC_SFT 3
376#define RT5670_MONO_DMIC_R_SRC_MASK (0x3)
377#define RT5670_MONO_DMIC_R_SRC_SFT 0
378
379/* ADC Mixer to DAC Mixer Control (0x29) */
380#define RT5670_M_ADCMIX_L (0x1 << 15)
381#define RT5670_M_ADCMIX_L_SFT 15
382#define RT5670_M_DAC1_L (0x1 << 14)
383#define RT5670_M_DAC1_L_SFT 14
384#define RT5670_DAC1_R_SEL_MASK (0x3 << 10)
385#define RT5670_DAC1_R_SEL_SFT 10
386#define RT5670_DAC1_R_SEL_IF1 (0x0 << 10)
387#define RT5670_DAC1_R_SEL_IF2 (0x1 << 10)
388#define RT5670_DAC1_R_SEL_IF3 (0x2 << 10)
389#define RT5670_DAC1_R_SEL_IF4 (0x3 << 10)
390#define RT5670_DAC1_L_SEL_MASK (0x3 << 8)
391#define RT5670_DAC1_L_SEL_SFT 8
392#define RT5670_DAC1_L_SEL_IF1 (0x0 << 8)
393#define RT5670_DAC1_L_SEL_IF2 (0x1 << 8)
394#define RT5670_DAC1_L_SEL_IF3 (0x2 << 8)
395#define RT5670_DAC1_L_SEL_IF4 (0x3 << 8)
396#define RT5670_M_ADCMIX_R (0x1 << 7)
397#define RT5670_M_ADCMIX_R_SFT 7
398#define RT5670_M_DAC1_R (0x1 << 6)
399#define RT5670_M_DAC1_R_SFT 6
400
401/* Stereo DAC Mixer Control (0x2a) */
402#define RT5670_M_DAC_L1 (0x1 << 14)
403#define RT5670_M_DAC_L1_SFT 14
404#define RT5670_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
405#define RT5670_DAC_L1_STO_L_VOL_SFT 13
406#define RT5670_M_DAC_L2 (0x1 << 12)
407#define RT5670_M_DAC_L2_SFT 12
408#define RT5670_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
409#define RT5670_DAC_L2_STO_L_VOL_SFT 11
410#define RT5670_M_DAC_R1_STO_L (0x1 << 9)
411#define RT5670_M_DAC_R1_STO_L_SFT 9
412#define RT5670_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
413#define RT5670_DAC_R1_STO_L_VOL_SFT 8
414#define RT5670_M_DAC_R1 (0x1 << 6)
415#define RT5670_M_DAC_R1_SFT 6
416#define RT5670_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
417#define RT5670_DAC_R1_STO_R_VOL_SFT 5
418#define RT5670_M_DAC_R2 (0x1 << 4)
419#define RT5670_M_DAC_R2_SFT 4
420#define RT5670_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
421#define RT5670_DAC_R2_STO_R_VOL_SFT 3
422#define RT5670_M_DAC_L1_STO_R (0x1 << 1)
423#define RT5670_M_DAC_L1_STO_R_SFT 1
424#define RT5670_DAC_L1_STO_R_VOL_MASK (0x1)
425#define RT5670_DAC_L1_STO_R_VOL_SFT 0
426
427/* Mono DAC Mixer Control (0x2b) */
428#define RT5670_M_DAC_L1_MONO_L (0x1 << 14)
429#define RT5670_M_DAC_L1_MONO_L_SFT 14
430#define RT5670_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
431#define RT5670_DAC_L1_MONO_L_VOL_SFT 13
432#define RT5670_M_DAC_L2_MONO_L (0x1 << 12)
433#define RT5670_M_DAC_L2_MONO_L_SFT 12
434#define RT5670_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
435#define RT5670_DAC_L2_MONO_L_VOL_SFT 11
436#define RT5670_M_DAC_R2_MONO_L (0x1 << 10)
437#define RT5670_M_DAC_R2_MONO_L_SFT 10
438#define RT5670_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
439#define RT5670_DAC_R2_MONO_L_VOL_SFT 9
440#define RT5670_M_DAC_R1_MONO_R (0x1 << 6)
441#define RT5670_M_DAC_R1_MONO_R_SFT 6
442#define RT5670_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
443#define RT5670_DAC_R1_MONO_R_VOL_SFT 5
444#define RT5670_M_DAC_R2_MONO_R (0x1 << 4)
445#define RT5670_M_DAC_R2_MONO_R_SFT 4
446#define RT5670_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
447#define RT5670_DAC_R2_MONO_R_VOL_SFT 3
448#define RT5670_M_DAC_L2_MONO_R (0x1 << 2)
449#define RT5670_M_DAC_L2_MONO_R_SFT 2
450#define RT5670_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
451#define RT5670_DAC_L2_MONO_R_VOL_SFT 1
452
453/* Digital Mixer Control (0x2c) */
454#define RT5670_M_STO_L_DAC_L (0x1 << 15)
455#define RT5670_M_STO_L_DAC_L_SFT 15
456#define RT5670_STO_L_DAC_L_VOL_MASK (0x1 << 14)
457#define RT5670_STO_L_DAC_L_VOL_SFT 14
458#define RT5670_M_DAC_L2_DAC_L (0x1 << 13)
459#define RT5670_M_DAC_L2_DAC_L_SFT 13
460#define RT5670_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
461#define RT5670_DAC_L2_DAC_L_VOL_SFT 12
462#define RT5670_M_STO_R_DAC_R (0x1 << 11)
463#define RT5670_M_STO_R_DAC_R_SFT 11
464#define RT5670_STO_R_DAC_R_VOL_MASK (0x1 << 10)
465#define RT5670_STO_R_DAC_R_VOL_SFT 10
466#define RT5670_M_DAC_R2_DAC_R (0x1 << 9)
467#define RT5670_M_DAC_R2_DAC_R_SFT 9
468#define RT5670_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
469#define RT5670_DAC_R2_DAC_R_VOL_SFT 8
470#define RT5670_M_DAC_R2_DAC_L (0x1 << 7)
471#define RT5670_M_DAC_R2_DAC_L_SFT 7
472#define RT5670_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
473#define RT5670_DAC_R2_DAC_L_VOL_SFT 6
474#define RT5670_M_DAC_L2_DAC_R (0x1 << 5)
475#define RT5670_M_DAC_L2_DAC_R_SFT 5
476#define RT5670_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
477#define RT5670_DAC_L2_DAC_R_VOL_SFT 4
478
479/* DSP Path Control 1 (0x2d) */
480#define RT5670_RXDP_SEL_MASK (0x7 << 13)
481#define RT5670_RXDP_SEL_SFT 13
482#define RT5670_RXDP_SRC_MASK (0x3 << 11)
483#define RT5670_RXDP_SRC_SFT 11
484#define RT5670_RXDP_SRC_NOR (0x0 << 11)
485#define RT5670_RXDP_SRC_DIV2 (0x1 << 11)
486#define RT5670_RXDP_SRC_DIV3 (0x2 << 11)
487#define RT5670_TXDP_SRC_MASK (0x3 << 4)
488#define RT5670_TXDP_SRC_SFT 4
489#define RT5670_TXDP_SRC_NOR (0x0 << 4)
490#define RT5670_TXDP_SRC_DIV2 (0x1 << 4)
491#define RT5670_TXDP_SRC_DIV3 (0x2 << 4)
492#define RT5670_TXDP_SLOT_SEL_MASK (0x3 << 2)
493#define RT5670_TXDP_SLOT_SEL_SFT 2
494#define RT5670_DSP_UL_SEL (0x1 << 1)
495#define RT5670_DSP_UL_SFT 1
496#define RT5670_DSP_DL_SEL 0x1
497#define RT5670_DSP_DL_SFT 0
498
499/* DSP Path Control 2 (0x2e) */
500#define RT5670_TXDP_L_VOL_MASK (0x7f << 8)
501#define RT5670_TXDP_L_VOL_SFT 8
502#define RT5670_TXDP_R_VOL_MASK (0x7f)
503#define RT5670_TXDP_R_VOL_SFT 0
504
505/* Digital Interface Data Control (0x2f) */
506#define RT5670_IF1_ADC2_IN_SEL (0x1 << 15)
507#define RT5670_IF1_ADC2_IN_SFT 15
508#define RT5670_IF2_ADC_IN_MASK (0x7 << 12)
509#define RT5670_IF2_ADC_IN_SFT 12
510#define RT5670_IF2_DAC_SEL_MASK (0x3 << 10)
511#define RT5670_IF2_DAC_SEL_SFT 10
512#define RT5670_IF2_ADC_SEL_MASK (0x3 << 8)
513#define RT5670_IF2_ADC_SEL_SFT 8
514
515/* Digital Interface Data Control (0x30) */
516#define RT5670_IF4_ADC_IN_MASK (0x3 << 4)
517#define RT5670_IF4_ADC_IN_SFT 4
518
519/* PDM Output Control (0x31) */
520#define RT5670_PDM1_L_MASK (0x1 << 15)
521#define RT5670_PDM1_L_SFT 15
522#define RT5670_M_PDM1_L (0x1 << 14)
523#define RT5670_M_PDM1_L_SFT 14
524#define RT5670_PDM1_R_MASK (0x1 << 13)
525#define RT5670_PDM1_R_SFT 13
526#define RT5670_M_PDM1_R (0x1 << 12)
527#define RT5670_M_PDM1_R_SFT 12
528#define RT5670_PDM2_L_MASK (0x1 << 11)
529#define RT5670_PDM2_L_SFT 11
530#define RT5670_M_PDM2_L (0x1 << 10)
531#define RT5670_M_PDM2_L_SFT 10
532#define RT5670_PDM2_R_MASK (0x1 << 9)
533#define RT5670_PDM2_R_SFT 9
534#define RT5670_M_PDM2_R (0x1 << 8)
535#define RT5670_M_PDM2_R_SFT 8
536#define RT5670_PDM2_BUSY (0x1 << 7)
537#define RT5670_PDM1_BUSY (0x1 << 6)
538#define RT5670_PDM_PATTERN (0x1 << 5)
539#define RT5670_PDM_GAIN (0x1 << 4)
540#define RT5670_PDM_DIV_MASK (0x3)
541
542/* REC Left Mixer Control 1 (0x3b) */
543#define RT5670_G_HP_L_RM_L_MASK (0x7 << 13)
544#define RT5670_G_HP_L_RM_L_SFT 13
545#define RT5670_G_IN_L_RM_L_MASK (0x7 << 10)
546#define RT5670_G_IN_L_RM_L_SFT 10
547#define RT5670_G_BST4_RM_L_MASK (0x7 << 7)
548#define RT5670_G_BST4_RM_L_SFT 7
549#define RT5670_G_BST3_RM_L_MASK (0x7 << 4)
550#define RT5670_G_BST3_RM_L_SFT 4
551#define RT5670_G_BST2_RM_L_MASK (0x7 << 1)
552#define RT5670_G_BST2_RM_L_SFT 1
553
554/* REC Left Mixer Control 2 (0x3c) */
555#define RT5670_G_BST1_RM_L_MASK (0x7 << 13)
556#define RT5670_G_BST1_RM_L_SFT 13
557#define RT5670_M_IN_L_RM_L (0x1 << 5)
558#define RT5670_M_IN_L_RM_L_SFT 5
559#define RT5670_M_BST2_RM_L (0x1 << 3)
560#define RT5670_M_BST2_RM_L_SFT 3
561#define RT5670_M_BST1_RM_L (0x1 << 1)
562#define RT5670_M_BST1_RM_L_SFT 1
563
564/* REC Right Mixer Control 1 (0x3d) */
565#define RT5670_G_HP_R_RM_R_MASK (0x7 << 13)
566#define RT5670_G_HP_R_RM_R_SFT 13
567#define RT5670_G_IN_R_RM_R_MASK (0x7 << 10)
568#define RT5670_G_IN_R_RM_R_SFT 10
569#define RT5670_G_BST4_RM_R_MASK (0x7 << 7)
570#define RT5670_G_BST4_RM_R_SFT 7
571#define RT5670_G_BST3_RM_R_MASK (0x7 << 4)
572#define RT5670_G_BST3_RM_R_SFT 4
573#define RT5670_G_BST2_RM_R_MASK (0x7 << 1)
574#define RT5670_G_BST2_RM_R_SFT 1
575
576/* REC Right Mixer Control 2 (0x3e) */
577#define RT5670_G_BST1_RM_R_MASK (0x7 << 13)
578#define RT5670_G_BST1_RM_R_SFT 13
579#define RT5670_M_IN_R_RM_R (0x1 << 5)
580#define RT5670_M_IN_R_RM_R_SFT 5
581#define RT5670_M_BST2_RM_R (0x1 << 3)
582#define RT5670_M_BST2_RM_R_SFT 3
583#define RT5670_M_BST1_RM_R (0x1 << 1)
584#define RT5670_M_BST1_RM_R_SFT 1
585
586/* HPMIX Control (0x45) */
587#define RT5670_M_DAC2_HM (0x1 << 15)
588#define RT5670_M_DAC2_HM_SFT 15
589#define RT5670_M_HPVOL_HM (0x1 << 14)
590#define RT5670_M_HPVOL_HM_SFT 14
591#define RT5670_M_DAC1_HM (0x1 << 13)
592#define RT5670_M_DAC1_HM_SFT 13
593#define RT5670_G_HPOMIX_MASK (0x1 << 12)
594#define RT5670_G_HPOMIX_SFT 12
595#define RT5670_M_INR1_HMR (0x1 << 3)
596#define RT5670_M_INR1_HMR_SFT 3
597#define RT5670_M_DACR1_HMR (0x1 << 2)
598#define RT5670_M_DACR1_HMR_SFT 2
599#define RT5670_M_INL1_HML (0x1 << 1)
600#define RT5670_M_INL1_HML_SFT 1
601#define RT5670_M_DACL1_HML (0x1)
602#define RT5670_M_DACL1_HML_SFT 0
603
604/* Mono Output Mixer Control (0x4c) */
605#define RT5670_M_DAC_R2_MA (0x1 << 15)
606#define RT5670_M_DAC_R2_MA_SFT 15
607#define RT5670_M_DAC_L2_MA (0x1 << 14)
608#define RT5670_M_DAC_L2_MA_SFT 14
609#define RT5670_M_OV_R_MM (0x1 << 13)
610#define RT5670_M_OV_R_MM_SFT 13
611#define RT5670_M_OV_L_MM (0x1 << 12)
612#define RT5670_M_OV_L_MM_SFT 12
613#define RT5670_G_MONOMIX_MASK (0x1 << 10)
614#define RT5670_G_MONOMIX_SFT 10
615#define RT5670_M_DAC_R2_MM (0x1 << 9)
616#define RT5670_M_DAC_R2_MM_SFT 9
617#define RT5670_M_DAC_L2_MM (0x1 << 8)
618#define RT5670_M_DAC_L2_MM_SFT 8
619#define RT5670_M_BST4_MM (0x1 << 7)
620#define RT5670_M_BST4_MM_SFT 7
621
622/* Output Left Mixer Control 1 (0x4d) */
623#define RT5670_G_BST3_OM_L_MASK (0x7 << 13)
624#define RT5670_G_BST3_OM_L_SFT 13
625#define RT5670_G_BST2_OM_L_MASK (0x7 << 10)
626#define RT5670_G_BST2_OM_L_SFT 10
627#define RT5670_G_BST1_OM_L_MASK (0x7 << 7)
628#define RT5670_G_BST1_OM_L_SFT 7
629#define RT5670_G_IN_L_OM_L_MASK (0x7 << 4)
630#define RT5670_G_IN_L_OM_L_SFT 4
631#define RT5670_G_RM_L_OM_L_MASK (0x7 << 1)
632#define RT5670_G_RM_L_OM_L_SFT 1
633
634/* Output Left Mixer Control 2 (0x4e) */
635#define RT5670_G_DAC_R2_OM_L_MASK (0x7 << 13)
636#define RT5670_G_DAC_R2_OM_L_SFT 13
637#define RT5670_G_DAC_L2_OM_L_MASK (0x7 << 10)
638#define RT5670_G_DAC_L2_OM_L_SFT 10
639#define RT5670_G_DAC_L1_OM_L_MASK (0x7 << 7)
640#define RT5670_G_DAC_L1_OM_L_SFT 7
641
642/* Output Left Mixer Control 3 (0x4f) */
643#define RT5670_M_BST1_OM_L (0x1 << 5)
644#define RT5670_M_BST1_OM_L_SFT 5
645#define RT5670_M_IN_L_OM_L (0x1 << 4)
646#define RT5670_M_IN_L_OM_L_SFT 4
647#define RT5670_M_DAC_L2_OM_L (0x1 << 1)
648#define RT5670_M_DAC_L2_OM_L_SFT 1
649#define RT5670_M_DAC_L1_OM_L (0x1)
650#define RT5670_M_DAC_L1_OM_L_SFT 0
651
652/* Output Right Mixer Control 1 (0x50) */
653#define RT5670_G_BST4_OM_R_MASK (0x7 << 13)
654#define RT5670_G_BST4_OM_R_SFT 13
655#define RT5670_G_BST2_OM_R_MASK (0x7 << 10)
656#define RT5670_G_BST2_OM_R_SFT 10
657#define RT5670_G_BST1_OM_R_MASK (0x7 << 7)
658#define RT5670_G_BST1_OM_R_SFT 7
659#define RT5670_G_IN_R_OM_R_MASK (0x7 << 4)
660#define RT5670_G_IN_R_OM_R_SFT 4
661#define RT5670_G_RM_R_OM_R_MASK (0x7 << 1)
662#define RT5670_G_RM_R_OM_R_SFT 1
663
664/* Output Right Mixer Control 2 (0x51) */
665#define RT5670_G_DAC_L2_OM_R_MASK (0x7 << 13)
666#define RT5670_G_DAC_L2_OM_R_SFT 13
667#define RT5670_G_DAC_R2_OM_R_MASK (0x7 << 10)
668#define RT5670_G_DAC_R2_OM_R_SFT 10
669#define RT5670_G_DAC_R1_OM_R_MASK (0x7 << 7)
670#define RT5670_G_DAC_R1_OM_R_SFT 7
671
672/* Output Right Mixer Control 3 (0x52) */
673#define RT5670_M_BST2_OM_R (0x1 << 6)
674#define RT5670_M_BST2_OM_R_SFT 6
675#define RT5670_M_IN_R_OM_R (0x1 << 4)
676#define RT5670_M_IN_R_OM_R_SFT 4
677#define RT5670_M_DAC_R2_OM_R (0x1 << 1)
678#define RT5670_M_DAC_R2_OM_R_SFT 1
679#define RT5670_M_DAC_R1_OM_R (0x1)
680#define RT5670_M_DAC_R1_OM_R_SFT 0
681
682/* LOUT Mixer Control (0x53) */
683#define RT5670_M_DAC_L1_LM (0x1 << 15)
684#define RT5670_M_DAC_L1_LM_SFT 15
685#define RT5670_M_DAC_R1_LM (0x1 << 14)
686#define RT5670_M_DAC_R1_LM_SFT 14
687#define RT5670_M_OV_L_LM (0x1 << 13)
688#define RT5670_M_OV_L_LM_SFT 13
689#define RT5670_M_OV_R_LM (0x1 << 12)
690#define RT5670_M_OV_R_LM_SFT 12
691#define RT5670_G_LOUTMIX_MASK (0x1 << 11)
692#define RT5670_G_LOUTMIX_SFT 11
693
694/* Power Management for Digital 1 (0x61) */
695#define RT5670_PWR_I2S1 (0x1 << 15)
696#define RT5670_PWR_I2S1_BIT 15
697#define RT5670_PWR_I2S2 (0x1 << 14)
698#define RT5670_PWR_I2S2_BIT 14
699#define RT5670_PWR_DAC_L1 (0x1 << 12)
700#define RT5670_PWR_DAC_L1_BIT 12
701#define RT5670_PWR_DAC_R1 (0x1 << 11)
702#define RT5670_PWR_DAC_R1_BIT 11
703#define RT5670_PWR_DAC_L2 (0x1 << 7)
704#define RT5670_PWR_DAC_L2_BIT 7
705#define RT5670_PWR_DAC_R2 (0x1 << 6)
706#define RT5670_PWR_DAC_R2_BIT 6
707#define RT5670_PWR_ADC_L (0x1 << 2)
708#define RT5670_PWR_ADC_L_BIT 2
709#define RT5670_PWR_ADC_R (0x1 << 1)
710#define RT5670_PWR_ADC_R_BIT 1
711#define RT5670_PWR_CLS_D (0x1)
712#define RT5670_PWR_CLS_D_BIT 0
713
714/* Power Management for Digital 2 (0x62) */
715#define RT5670_PWR_ADC_S1F (0x1 << 15)
716#define RT5670_PWR_ADC_S1F_BIT 15
717#define RT5670_PWR_ADC_MF_L (0x1 << 14)
718#define RT5670_PWR_ADC_MF_L_BIT 14
719#define RT5670_PWR_ADC_MF_R (0x1 << 13)
720#define RT5670_PWR_ADC_MF_R_BIT 13
721#define RT5670_PWR_I2S_DSP (0x1 << 12)
722#define RT5670_PWR_I2S_DSP_BIT 12
723#define RT5670_PWR_DAC_S1F (0x1 << 11)
724#define RT5670_PWR_DAC_S1F_BIT 11
725#define RT5670_PWR_DAC_MF_L (0x1 << 10)
726#define RT5670_PWR_DAC_MF_L_BIT 10
727#define RT5670_PWR_DAC_MF_R (0x1 << 9)
728#define RT5670_PWR_DAC_MF_R_BIT 9
729#define RT5670_PWR_ADC_S2F (0x1 << 8)
730#define RT5670_PWR_ADC_S2F_BIT 8
731#define RT5670_PWR_PDM1 (0x1 << 7)
732#define RT5670_PWR_PDM1_BIT 7
733#define RT5670_PWR_PDM2 (0x1 << 6)
734#define RT5670_PWR_PDM2_BIT 6
735
736/* Power Management for Analog 1 (0x63) */
737#define RT5670_PWR_VREF1 (0x1 << 15)
738#define RT5670_PWR_VREF1_BIT 15
739#define RT5670_PWR_FV1 (0x1 << 14)
740#define RT5670_PWR_FV1_BIT 14
741#define RT5670_PWR_MB (0x1 << 13)
742#define RT5670_PWR_MB_BIT 13
743#define RT5670_PWR_LM (0x1 << 12)
744#define RT5670_PWR_LM_BIT 12
745#define RT5670_PWR_BG (0x1 << 11)
746#define RT5670_PWR_BG_BIT 11
747#define RT5670_PWR_HP_L (0x1 << 7)
748#define RT5670_PWR_HP_L_BIT 7
749#define RT5670_PWR_HP_R (0x1 << 6)
750#define RT5670_PWR_HP_R_BIT 6
751#define RT5670_PWR_HA (0x1 << 5)
752#define RT5670_PWR_HA_BIT 5
753#define RT5670_PWR_VREF2 (0x1 << 4)
754#define RT5670_PWR_VREF2_BIT 4
755#define RT5670_PWR_FV2 (0x1 << 3)
756#define RT5670_PWR_FV2_BIT 3
757#define RT5670_LDO_SEL_MASK (0x3)
758#define RT5670_LDO_SEL_SFT 0
759
760/* Power Management for Analog 2 (0x64) */
761#define RT5670_PWR_BST1 (0x1 << 15)
762#define RT5670_PWR_BST1_BIT 15
763#define RT5670_PWR_BST2 (0x1 << 13)
764#define RT5670_PWR_BST2_BIT 13
765#define RT5670_PWR_MB1 (0x1 << 11)
766#define RT5670_PWR_MB1_BIT 11
767#define RT5670_PWR_MB2 (0x1 << 10)
768#define RT5670_PWR_MB2_BIT 10
769#define RT5670_PWR_PLL (0x1 << 9)
770#define RT5670_PWR_PLL_BIT 9
771#define RT5670_PWR_BST1_P (0x1 << 6)
772#define RT5670_PWR_BST1_P_BIT 6
773#define RT5670_PWR_BST2_P (0x1 << 4)
774#define RT5670_PWR_BST2_P_BIT 4
775#define RT5670_PWR_JD1 (0x1 << 2)
776#define RT5670_PWR_JD1_BIT 2
777#define RT5670_PWR_JD (0x1 << 1)
778#define RT5670_PWR_JD_BIT 1
779
780/* Power Management for Mixer (0x65) */
781#define RT5670_PWR_OM_L (0x1 << 15)
782#define RT5670_PWR_OM_L_BIT 15
783#define RT5670_PWR_OM_R (0x1 << 14)
784#define RT5670_PWR_OM_R_BIT 14
785#define RT5670_PWR_RM_L (0x1 << 11)
786#define RT5670_PWR_RM_L_BIT 11
787#define RT5670_PWR_RM_R (0x1 << 10)
788#define RT5670_PWR_RM_R_BIT 10
789
790/* Power Management for Volume (0x66) */
791#define RT5670_PWR_HV_L (0x1 << 11)
792#define RT5670_PWR_HV_L_BIT 11
793#define RT5670_PWR_HV_R (0x1 << 10)
794#define RT5670_PWR_HV_R_BIT 10
795#define RT5670_PWR_IN_L (0x1 << 9)
796#define RT5670_PWR_IN_L_BIT 9
797#define RT5670_PWR_IN_R (0x1 << 8)
798#define RT5670_PWR_IN_R_BIT 8
799#define RT5670_PWR_MIC_DET (0x1 << 5)
800#define RT5670_PWR_MIC_DET_BIT 5
801
802/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
803#define RT5670_I2S_MS_MASK (0x1 << 15)
804#define RT5670_I2S_MS_SFT 15
805#define RT5670_I2S_MS_M (0x0 << 15)
806#define RT5670_I2S_MS_S (0x1 << 15)
807#define RT5670_I2S_IF_MASK (0x7 << 12)
808#define RT5670_I2S_IF_SFT 12
809#define RT5670_I2S_O_CP_MASK (0x3 << 10)
810#define RT5670_I2S_O_CP_SFT 10
811#define RT5670_I2S_O_CP_OFF (0x0 << 10)
812#define RT5670_I2S_O_CP_U_LAW (0x1 << 10)
813#define RT5670_I2S_O_CP_A_LAW (0x2 << 10)
814#define RT5670_I2S_I_CP_MASK (0x3 << 8)
815#define RT5670_I2S_I_CP_SFT 8
816#define RT5670_I2S_I_CP_OFF (0x0 << 8)
817#define RT5670_I2S_I_CP_U_LAW (0x1 << 8)
818#define RT5670_I2S_I_CP_A_LAW (0x2 << 8)
819#define RT5670_I2S_BP_MASK (0x1 << 7)
820#define RT5670_I2S_BP_SFT 7
821#define RT5670_I2S_BP_NOR (0x0 << 7)
822#define RT5670_I2S_BP_INV (0x1 << 7)
823#define RT5670_I2S_DL_MASK (0x3 << 2)
824#define RT5670_I2S_DL_SFT 2
825#define RT5670_I2S_DL_16 (0x0 << 2)
826#define RT5670_I2S_DL_20 (0x1 << 2)
827#define RT5670_I2S_DL_24 (0x2 << 2)
828#define RT5670_I2S_DL_8 (0x3 << 2)
829#define RT5670_I2S_DF_MASK (0x3)
830#define RT5670_I2S_DF_SFT 0
831#define RT5670_I2S_DF_I2S (0x0)
832#define RT5670_I2S_DF_LEFT (0x1)
833#define RT5670_I2S_DF_PCM_A (0x2)
834#define RT5670_I2S_DF_PCM_B (0x3)
835
836/* I2S2 Audio Serial Data Port Control (0x71) */
837#define RT5670_I2S2_SDI_MASK (0x1 << 6)
838#define RT5670_I2S2_SDI_SFT 6
839#define RT5670_I2S2_SDI_I2S1 (0x0 << 6)
840#define RT5670_I2S2_SDI_I2S2 (0x1 << 6)
841
842/* ADC/DAC Clock Control 1 (0x73) */
843#define RT5670_I2S_BCLK_MS1_MASK (0x1 << 15)
844#define RT5670_I2S_BCLK_MS1_SFT 15
845#define RT5670_I2S_BCLK_MS1_32 (0x0 << 15)
846#define RT5670_I2S_BCLK_MS1_64 (0x1 << 15)
847#define RT5670_I2S_PD1_MASK (0x7 << 12)
848#define RT5670_I2S_PD1_SFT 12
849#define RT5670_I2S_PD1_1 (0x0 << 12)
850#define RT5670_I2S_PD1_2 (0x1 << 12)
851#define RT5670_I2S_PD1_3 (0x2 << 12)
852#define RT5670_I2S_PD1_4 (0x3 << 12)
853#define RT5670_I2S_PD1_6 (0x4 << 12)
854#define RT5670_I2S_PD1_8 (0x5 << 12)
855#define RT5670_I2S_PD1_12 (0x6 << 12)
856#define RT5670_I2S_PD1_16 (0x7 << 12)
857#define RT5670_I2S_BCLK_MS2_MASK (0x1 << 11)
858#define RT5670_I2S_BCLK_MS2_SFT 11
859#define RT5670_I2S_BCLK_MS2_32 (0x0 << 11)
860#define RT5670_I2S_BCLK_MS2_64 (0x1 << 11)
861#define RT5670_I2S_PD2_MASK (0x7 << 8)
862#define RT5670_I2S_PD2_SFT 8
863#define RT5670_I2S_PD2_1 (0x0 << 8)
864#define RT5670_I2S_PD2_2 (0x1 << 8)
865#define RT5670_I2S_PD2_3 (0x2 << 8)
866#define RT5670_I2S_PD2_4 (0x3 << 8)
867#define RT5670_I2S_PD2_6 (0x4 << 8)
868#define RT5670_I2S_PD2_8 (0x5 << 8)
869#define RT5670_I2S_PD2_12 (0x6 << 8)
870#define RT5670_I2S_PD2_16 (0x7 << 8)
871#define RT5670_I2S_BCLK_MS3_MASK (0x1 << 7)
872#define RT5670_I2S_BCLK_MS3_SFT 7
873#define RT5670_I2S_BCLK_MS3_32 (0x0 << 7)
874#define RT5670_I2S_BCLK_MS3_64 (0x1 << 7)
875#define RT5670_I2S_PD3_MASK (0x7 << 4)
876#define RT5670_I2S_PD3_SFT 4
877#define RT5670_I2S_PD3_1 (0x0 << 4)
878#define RT5670_I2S_PD3_2 (0x1 << 4)
879#define RT5670_I2S_PD3_3 (0x2 << 4)
880#define RT5670_I2S_PD3_4 (0x3 << 4)
881#define RT5670_I2S_PD3_6 (0x4 << 4)
882#define RT5670_I2S_PD3_8 (0x5 << 4)
883#define RT5670_I2S_PD3_12 (0x6 << 4)
884#define RT5670_I2S_PD3_16 (0x7 << 4)
885#define RT5670_DAC_OSR_MASK (0x3 << 2)
886#define RT5670_DAC_OSR_SFT 2
887#define RT5670_DAC_OSR_128 (0x0 << 2)
888#define RT5670_DAC_OSR_64 (0x1 << 2)
889#define RT5670_DAC_OSR_32 (0x2 << 2)
890#define RT5670_DAC_OSR_16 (0x3 << 2)
891#define RT5670_ADC_OSR_MASK (0x3)
892#define RT5670_ADC_OSR_SFT 0
893#define RT5670_ADC_OSR_128 (0x0)
894#define RT5670_ADC_OSR_64 (0x1)
895#define RT5670_ADC_OSR_32 (0x2)
896#define RT5670_ADC_OSR_16 (0x3)
897
898/* ADC/DAC Clock Control 2 (0x74) */
899#define RT5670_DAC_L_OSR_MASK (0x3 << 14)
900#define RT5670_DAC_L_OSR_SFT 14
901#define RT5670_DAC_L_OSR_128 (0x0 << 14)
902#define RT5670_DAC_L_OSR_64 (0x1 << 14)
903#define RT5670_DAC_L_OSR_32 (0x2 << 14)
904#define RT5670_DAC_L_OSR_16 (0x3 << 14)
905#define RT5670_ADC_R_OSR_MASK (0x3 << 12)
906#define RT5670_ADC_R_OSR_SFT 12
907#define RT5670_ADC_R_OSR_128 (0x0 << 12)
908#define RT5670_ADC_R_OSR_64 (0x1 << 12)
909#define RT5670_ADC_R_OSR_32 (0x2 << 12)
910#define RT5670_ADC_R_OSR_16 (0x3 << 12)
911#define RT5670_DAHPF_EN (0x1 << 11)
912#define RT5670_DAHPF_EN_SFT 11
913#define RT5670_ADHPF_EN (0x1 << 10)
914#define RT5670_ADHPF_EN_SFT 10
915
916/* Digital Microphone Control (0x75) */
917#define RT5670_DMIC_1_EN_MASK (0x1 << 15)
918#define RT5670_DMIC_1_EN_SFT 15
919#define RT5670_DMIC_1_DIS (0x0 << 15)
920#define RT5670_DMIC_1_EN (0x1 << 15)
921#define RT5670_DMIC_2_EN_MASK (0x1 << 14)
922#define RT5670_DMIC_2_EN_SFT 14
923#define RT5670_DMIC_2_DIS (0x0 << 14)
924#define RT5670_DMIC_2_EN (0x1 << 14)
925#define RT5670_DMIC_1L_LH_MASK (0x1 << 13)
926#define RT5670_DMIC_1L_LH_SFT 13
927#define RT5670_DMIC_1L_LH_FALLING (0x0 << 13)
928#define RT5670_DMIC_1L_LH_RISING (0x1 << 13)
929#define RT5670_DMIC_1R_LH_MASK (0x1 << 12)
930#define RT5670_DMIC_1R_LH_SFT 12
931#define RT5670_DMIC_1R_LH_FALLING (0x0 << 12)
932#define RT5670_DMIC_1R_LH_RISING (0x1 << 12)
933#define RT5670_DMIC_2_DP_MASK (0x1 << 10)
934#define RT5670_DMIC_2_DP_SFT 10
935#define RT5670_DMIC_2_DP_GPIO8 (0x0 << 10)
936#define RT5670_DMIC_2_DP_IN3N (0x1 << 10)
937#define RT5670_DMIC_2L_LH_MASK (0x1 << 9)
938#define RT5670_DMIC_2L_LH_SFT 9
939#define RT5670_DMIC_2L_LH_FALLING (0x0 << 9)
940#define RT5670_DMIC_2L_LH_RISING (0x1 << 9)
941#define RT5670_DMIC_2R_LH_MASK (0x1 << 8)
942#define RT5670_DMIC_2R_LH_SFT 8
943#define RT5670_DMIC_2R_LH_FALLING (0x0 << 8)
944#define RT5670_DMIC_2R_LH_RISING (0x1 << 8)
945#define RT5670_DMIC_CLK_MASK (0x7 << 5)
946#define RT5670_DMIC_CLK_SFT 5
947#define RT5670_DMIC_3_EN_MASK (0x1 << 4)
948#define RT5670_DMIC_3_EN_SFT 4
949#define RT5670_DMIC_3_DIS (0x0 << 4)
950#define RT5670_DMIC_3_EN (0x1 << 4)
951#define RT5670_DMIC_1_DP_MASK (0x3 << 0)
952#define RT5670_DMIC_1_DP_SFT 0
953#define RT5670_DMIC_1_DP_GPIO6 (0x0 << 0)
954#define RT5670_DMIC_1_DP_IN2P (0x1 << 0)
955#define RT5670_DMIC_1_DP_GPIO7 (0x2 << 0)
956
957/* Digital Microphone Control2 (0x76) */
958#define RT5670_DMIC_3_DP_MASK (0x3 << 6)
959#define RT5670_DMIC_3_DP_SFT 6
960#define RT5670_DMIC_3_DP_GPIO9 (0x0 << 6)
961#define RT5670_DMIC_3_DP_GPIO10 (0x1 << 6)
962#define RT5670_DMIC_3_DP_GPIO5 (0x2 << 6)
963
964/* Global Clock Control (0x80) */
965#define RT5670_SCLK_SRC_MASK (0x3 << 14)
966#define RT5670_SCLK_SRC_SFT 14
967#define RT5670_SCLK_SRC_MCLK (0x0 << 14)
968#define RT5670_SCLK_SRC_PLL1 (0x1 << 14)
969#define RT5670_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
970#define RT5670_PLL1_SRC_MASK (0x3 << 12)
971#define RT5670_PLL1_SRC_SFT 12
972#define RT5670_PLL1_SRC_MCLK (0x0 << 12)
973#define RT5670_PLL1_SRC_BCLK1 (0x1 << 12)
974#define RT5670_PLL1_SRC_BCLK2 (0x2 << 12)
975#define RT5670_PLL1_SRC_BCLK3 (0x3 << 12)
976#define RT5670_PLL1_PD_MASK (0x1 << 3)
977#define RT5670_PLL1_PD_SFT 3
978#define RT5670_PLL1_PD_1 (0x0 << 3)
979#define RT5670_PLL1_PD_2 (0x1 << 3)
980
981#define RT5670_PLL_INP_MAX 40000000
982#define RT5670_PLL_INP_MIN 256000
983/* PLL M/N/K Code Control 1 (0x81) */
984#define RT5670_PLL_N_MAX 0x1ff
985#define RT5670_PLL_N_MASK (RT5670_PLL_N_MAX << 7)
986#define RT5670_PLL_N_SFT 7
987#define RT5670_PLL_K_MAX 0x1f
988#define RT5670_PLL_K_MASK (RT5670_PLL_K_MAX)
989#define RT5670_PLL_K_SFT 0
990
991/* PLL M/N/K Code Control 2 (0x82) */
992#define RT5670_PLL_M_MAX 0xf
993#define RT5670_PLL_M_MASK (RT5670_PLL_M_MAX << 12)
994#define RT5670_PLL_M_SFT 12
995#define RT5670_PLL_M_BP (0x1 << 11)
996#define RT5670_PLL_M_BP_SFT 11
997
998/* ASRC Control 1 (0x83) */
999#define RT5670_STO_T_MASK (0x1 << 15)
1000#define RT5670_STO_T_SFT 15
1001#define RT5670_STO_T_SCLK (0x0 << 15)
1002#define RT5670_STO_T_LRCK1 (0x1 << 15)
1003#define RT5670_M1_T_MASK (0x1 << 14)
1004#define RT5670_M1_T_SFT 14
1005#define RT5670_M1_T_I2S2 (0x0 << 14)
1006#define RT5670_M1_T_I2S2_D3 (0x1 << 14)
1007#define RT5670_I2S2_F_MASK (0x1 << 12)
1008#define RT5670_I2S2_F_SFT 12
1009#define RT5670_I2S2_F_I2S2_D2 (0x0 << 12)
1010#define RT5670_I2S2_F_I2S1_TCLK (0x1 << 12)
1011#define RT5670_DMIC_1_M_MASK (0x1 << 9)
1012#define RT5670_DMIC_1_M_SFT 9
1013#define RT5670_DMIC_1_M_NOR (0x0 << 9)
1014#define RT5670_DMIC_1_M_ASYN (0x1 << 9)
1015#define RT5670_DMIC_2_M_MASK (0x1 << 8)
1016#define RT5670_DMIC_2_M_SFT 8
1017#define RT5670_DMIC_2_M_NOR (0x0 << 8)
1018#define RT5670_DMIC_2_M_ASYN (0x1 << 8)
1019
1020/* ASRC Control 2 (0x84) */
1021#define RT5670_MDA_L_M_MASK (0x1 << 15)
1022#define RT5670_MDA_L_M_SFT 15
1023#define RT5670_MDA_L_M_NOR (0x0 << 15)
1024#define RT5670_MDA_L_M_ASYN (0x1 << 15)
1025#define RT5670_MDA_R_M_MASK (0x1 << 14)
1026#define RT5670_MDA_R_M_SFT 14
1027#define RT5670_MDA_R_M_NOR (0x0 << 14)
1028#define RT5670_MDA_R_M_ASYN (0x1 << 14)
1029#define RT5670_MAD_L_M_MASK (0x1 << 13)
1030#define RT5670_MAD_L_M_SFT 13
1031#define RT5670_MAD_L_M_NOR (0x0 << 13)
1032#define RT5670_MAD_L_M_ASYN (0x1 << 13)
1033#define RT5670_MAD_R_M_MASK (0x1 << 12)
1034#define RT5670_MAD_R_M_SFT 12
1035#define RT5670_MAD_R_M_NOR (0x0 << 12)
1036#define RT5670_MAD_R_M_ASYN (0x1 << 12)
1037#define RT5670_ADC_M_MASK (0x1 << 11)
1038#define RT5670_ADC_M_SFT 11
1039#define RT5670_ADC_M_NOR (0x0 << 11)
1040#define RT5670_ADC_M_ASYN (0x1 << 11)
1041#define RT5670_STO_DAC_M_MASK (0x1 << 5)
1042#define RT5670_STO_DAC_M_SFT 5
1043#define RT5670_STO_DAC_M_NOR (0x0 << 5)
1044#define RT5670_STO_DAC_M_ASYN (0x1 << 5)
1045#define RT5670_I2S1_R_D_MASK (0x1 << 4)
1046#define RT5670_I2S1_R_D_SFT 4
1047#define RT5670_I2S1_R_D_DIS (0x0 << 4)
1048#define RT5670_I2S1_R_D_EN (0x1 << 4)
1049#define RT5670_I2S2_R_D_MASK (0x1 << 3)
1050#define RT5670_I2S2_R_D_SFT 3
1051#define RT5670_I2S2_R_D_DIS (0x0 << 3)
1052#define RT5670_I2S2_R_D_EN (0x1 << 3)
1053#define RT5670_PRE_SCLK_MASK (0x3)
1054#define RT5670_PRE_SCLK_SFT 0
1055#define RT5670_PRE_SCLK_512 (0x0)
1056#define RT5670_PRE_SCLK_1024 (0x1)
1057#define RT5670_PRE_SCLK_2048 (0x2)
1058
1059/* ASRC Control 3 (0x85) */
1060#define RT5670_I2S1_RATE_MASK (0xf << 12)
1061#define RT5670_I2S1_RATE_SFT 12
1062#define RT5670_I2S2_RATE_MASK (0xf << 8)
1063#define RT5670_I2S2_RATE_SFT 8
1064
1065/* ASRC Control 4 (0x89) */
1066#define RT5670_I2S1_PD_MASK (0x7 << 12)
1067#define RT5670_I2S1_PD_SFT 12
1068#define RT5670_I2S2_PD_MASK (0x7 << 8)
1069#define RT5670_I2S2_PD_SFT 8
1070
1071/* HPOUT Over Current Detection (0x8b) */
1072#define RT5670_HP_OVCD_MASK (0x1 << 10)
1073#define RT5670_HP_OVCD_SFT 10
1074#define RT5670_HP_OVCD_DIS (0x0 << 10)
1075#define RT5670_HP_OVCD_EN (0x1 << 10)
1076#define RT5670_HP_OC_TH_MASK (0x3 << 8)
1077#define RT5670_HP_OC_TH_SFT 8
1078#define RT5670_HP_OC_TH_90 (0x0 << 8)
1079#define RT5670_HP_OC_TH_105 (0x1 << 8)
1080#define RT5670_HP_OC_TH_120 (0x2 << 8)
1081#define RT5670_HP_OC_TH_135 (0x3 << 8)
1082
1083/* Class D Over Current Control (0x8c) */
1084#define RT5670_CLSD_OC_MASK (0x1 << 9)
1085#define RT5670_CLSD_OC_SFT 9
1086#define RT5670_CLSD_OC_PU (0x0 << 9)
1087#define RT5670_CLSD_OC_PD (0x1 << 9)
1088#define RT5670_AUTO_PD_MASK (0x1 << 8)
1089#define RT5670_AUTO_PD_SFT 8
1090#define RT5670_AUTO_PD_DIS (0x0 << 8)
1091#define RT5670_AUTO_PD_EN (0x1 << 8)
1092#define RT5670_CLSD_OC_TH_MASK (0x3f)
1093#define RT5670_CLSD_OC_TH_SFT 0
1094
1095/* Class D Output Control (0x8d) */
1096#define RT5670_CLSD_RATIO_MASK (0xf << 12)
1097#define RT5670_CLSD_RATIO_SFT 12
1098#define RT5670_CLSD_OM_MASK (0x1 << 11)
1099#define RT5670_CLSD_OM_SFT 11
1100#define RT5670_CLSD_OM_MONO (0x0 << 11)
1101#define RT5670_CLSD_OM_STO (0x1 << 11)
1102#define RT5670_CLSD_SCH_MASK (0x1 << 10)
1103#define RT5670_CLSD_SCH_SFT 10
1104#define RT5670_CLSD_SCH_L (0x0 << 10)
1105#define RT5670_CLSD_SCH_S (0x1 << 10)
1106
1107/* Depop Mode Control 1 (0x8e) */
1108#define RT5670_SMT_TRIG_MASK (0x1 << 15)
1109#define RT5670_SMT_TRIG_SFT 15
1110#define RT5670_SMT_TRIG_DIS (0x0 << 15)
1111#define RT5670_SMT_TRIG_EN (0x1 << 15)
1112#define RT5670_HP_L_SMT_MASK (0x1 << 9)
1113#define RT5670_HP_L_SMT_SFT 9
1114#define RT5670_HP_L_SMT_DIS (0x0 << 9)
1115#define RT5670_HP_L_SMT_EN (0x1 << 9)
1116#define RT5670_HP_R_SMT_MASK (0x1 << 8)
1117#define RT5670_HP_R_SMT_SFT 8
1118#define RT5670_HP_R_SMT_DIS (0x0 << 8)
1119#define RT5670_HP_R_SMT_EN (0x1 << 8)
1120#define RT5670_HP_CD_PD_MASK (0x1 << 7)
1121#define RT5670_HP_CD_PD_SFT 7
1122#define RT5670_HP_CD_PD_DIS (0x0 << 7)
1123#define RT5670_HP_CD_PD_EN (0x1 << 7)
1124#define RT5670_RSTN_MASK (0x1 << 6)
1125#define RT5670_RSTN_SFT 6
1126#define RT5670_RSTN_DIS (0x0 << 6)
1127#define RT5670_RSTN_EN (0x1 << 6)
1128#define RT5670_RSTP_MASK (0x1 << 5)
1129#define RT5670_RSTP_SFT 5
1130#define RT5670_RSTP_DIS (0x0 << 5)
1131#define RT5670_RSTP_EN (0x1 << 5)
1132#define RT5670_HP_CO_MASK (0x1 << 4)
1133#define RT5670_HP_CO_SFT 4
1134#define RT5670_HP_CO_DIS (0x0 << 4)
1135#define RT5670_HP_CO_EN (0x1 << 4)
1136#define RT5670_HP_CP_MASK (0x1 << 3)
1137#define RT5670_HP_CP_SFT 3
1138#define RT5670_HP_CP_PD (0x0 << 3)
1139#define RT5670_HP_CP_PU (0x1 << 3)
1140#define RT5670_HP_SG_MASK (0x1 << 2)
1141#define RT5670_HP_SG_SFT 2
1142#define RT5670_HP_SG_DIS (0x0 << 2)
1143#define RT5670_HP_SG_EN (0x1 << 2)
1144#define RT5670_HP_DP_MASK (0x1 << 1)
1145#define RT5670_HP_DP_SFT 1
1146#define RT5670_HP_DP_PD (0x0 << 1)
1147#define RT5670_HP_DP_PU (0x1 << 1)
1148#define RT5670_HP_CB_MASK (0x1)
1149#define RT5670_HP_CB_SFT 0
1150#define RT5670_HP_CB_PD (0x0)
1151#define RT5670_HP_CB_PU (0x1)
1152
1153/* Depop Mode Control 2 (0x8f) */
1154#define RT5670_DEPOP_MASK (0x1 << 13)
1155#define RT5670_DEPOP_SFT 13
1156#define RT5670_DEPOP_AUTO (0x0 << 13)
1157#define RT5670_DEPOP_MAN (0x1 << 13)
1158#define RT5670_RAMP_MASK (0x1 << 12)
1159#define RT5670_RAMP_SFT 12
1160#define RT5670_RAMP_DIS (0x0 << 12)
1161#define RT5670_RAMP_EN (0x1 << 12)
1162#define RT5670_BPS_MASK (0x1 << 11)
1163#define RT5670_BPS_SFT 11
1164#define RT5670_BPS_DIS (0x0 << 11)
1165#define RT5670_BPS_EN (0x1 << 11)
1166#define RT5670_FAST_UPDN_MASK (0x1 << 10)
1167#define RT5670_FAST_UPDN_SFT 10
1168#define RT5670_FAST_UPDN_DIS (0x0 << 10)
1169#define RT5670_FAST_UPDN_EN (0x1 << 10)
1170#define RT5670_MRES_MASK (0x3 << 8)
1171#define RT5670_MRES_SFT 8
1172#define RT5670_MRES_15MO (0x0 << 8)
1173#define RT5670_MRES_25MO (0x1 << 8)
1174#define RT5670_MRES_35MO (0x2 << 8)
1175#define RT5670_MRES_45MO (0x3 << 8)
1176#define RT5670_VLO_MASK (0x1 << 7)
1177#define RT5670_VLO_SFT 7
1178#define RT5670_VLO_3V (0x0 << 7)
1179#define RT5670_VLO_32V (0x1 << 7)
1180#define RT5670_DIG_DP_MASK (0x1 << 6)
1181#define RT5670_DIG_DP_SFT 6
1182#define RT5670_DIG_DP_DIS (0x0 << 6)
1183#define RT5670_DIG_DP_EN (0x1 << 6)
1184#define RT5670_DP_TH_MASK (0x3 << 4)
1185#define RT5670_DP_TH_SFT 4
1186
1187/* Depop Mode Control 3 (0x90) */
1188#define RT5670_CP_SYS_MASK (0x7 << 12)
1189#define RT5670_CP_SYS_SFT 12
1190#define RT5670_CP_FQ1_MASK (0x7 << 8)
1191#define RT5670_CP_FQ1_SFT 8
1192#define RT5670_CP_FQ2_MASK (0x7 << 4)
1193#define RT5670_CP_FQ2_SFT 4
1194#define RT5670_CP_FQ3_MASK (0x7)
1195#define RT5670_CP_FQ3_SFT 0
1196#define RT5670_CP_FQ_1_5_KHZ 0
1197#define RT5670_CP_FQ_3_KHZ 1
1198#define RT5670_CP_FQ_6_KHZ 2
1199#define RT5670_CP_FQ_12_KHZ 3
1200#define RT5670_CP_FQ_24_KHZ 4
1201#define RT5670_CP_FQ_48_KHZ 5
1202#define RT5670_CP_FQ_96_KHZ 6
1203#define RT5670_CP_FQ_192_KHZ 7
1204
1205/* HPOUT charge pump (0x91) */
1206#define RT5670_OSW_L_MASK (0x1 << 11)
1207#define RT5670_OSW_L_SFT 11
1208#define RT5670_OSW_L_DIS (0x0 << 11)
1209#define RT5670_OSW_L_EN (0x1 << 11)
1210#define RT5670_OSW_R_MASK (0x1 << 10)
1211#define RT5670_OSW_R_SFT 10
1212#define RT5670_OSW_R_DIS (0x0 << 10)
1213#define RT5670_OSW_R_EN (0x1 << 10)
1214#define RT5670_PM_HP_MASK (0x3 << 8)
1215#define RT5670_PM_HP_SFT 8
1216#define RT5670_PM_HP_LV (0x0 << 8)
1217#define RT5670_PM_HP_MV (0x1 << 8)
1218#define RT5670_PM_HP_HV (0x2 << 8)
1219#define RT5670_IB_HP_MASK (0x3 << 6)
1220#define RT5670_IB_HP_SFT 6
1221#define RT5670_IB_HP_125IL (0x0 << 6)
1222#define RT5670_IB_HP_25IL (0x1 << 6)
1223#define RT5670_IB_HP_5IL (0x2 << 6)
1224#define RT5670_IB_HP_1IL (0x3 << 6)
1225
1226/* PV detection and SPK gain control (0x92) */
1227#define RT5670_PVDD_DET_MASK (0x1 << 15)
1228#define RT5670_PVDD_DET_SFT 15
1229#define RT5670_PVDD_DET_DIS (0x0 << 15)
1230#define RT5670_PVDD_DET_EN (0x1 << 15)
1231#define RT5670_SPK_AG_MASK (0x1 << 14)
1232#define RT5670_SPK_AG_SFT 14
1233#define RT5670_SPK_AG_DIS (0x0 << 14)
1234#define RT5670_SPK_AG_EN (0x1 << 14)
1235
1236/* Micbias Control (0x93) */
1237#define RT5670_MIC1_BS_MASK (0x1 << 15)
1238#define RT5670_MIC1_BS_SFT 15
1239#define RT5670_MIC1_BS_9AV (0x0 << 15)
1240#define RT5670_MIC1_BS_75AV (0x1 << 15)
1241#define RT5670_MIC2_BS_MASK (0x1 << 14)
1242#define RT5670_MIC2_BS_SFT 14
1243#define RT5670_MIC2_BS_9AV (0x0 << 14)
1244#define RT5670_MIC2_BS_75AV (0x1 << 14)
1245#define RT5670_MIC1_CLK_MASK (0x1 << 13)
1246#define RT5670_MIC1_CLK_SFT 13
1247#define RT5670_MIC1_CLK_DIS (0x0 << 13)
1248#define RT5670_MIC1_CLK_EN (0x1 << 13)
1249#define RT5670_MIC2_CLK_MASK (0x1 << 12)
1250#define RT5670_MIC2_CLK_SFT 12
1251#define RT5670_MIC2_CLK_DIS (0x0 << 12)
1252#define RT5670_MIC2_CLK_EN (0x1 << 12)
1253#define RT5670_MIC1_OVCD_MASK (0x1 << 11)
1254#define RT5670_MIC1_OVCD_SFT 11
1255#define RT5670_MIC1_OVCD_DIS (0x0 << 11)
1256#define RT5670_MIC1_OVCD_EN (0x1 << 11)
1257#define RT5670_MIC1_OVTH_MASK (0x3 << 9)
1258#define RT5670_MIC1_OVTH_SFT 9
1259#define RT5670_MIC1_OVTH_600UA (0x0 << 9)
1260#define RT5670_MIC1_OVTH_1500UA (0x1 << 9)
1261#define RT5670_MIC1_OVTH_2000UA (0x2 << 9)
1262#define RT5670_MIC2_OVCD_MASK (0x1 << 8)
1263#define RT5670_MIC2_OVCD_SFT 8
1264#define RT5670_MIC2_OVCD_DIS (0x0 << 8)
1265#define RT5670_MIC2_OVCD_EN (0x1 << 8)
1266#define RT5670_MIC2_OVTH_MASK (0x3 << 6)
1267#define RT5670_MIC2_OVTH_SFT 6
1268#define RT5670_MIC2_OVTH_600UA (0x0 << 6)
1269#define RT5670_MIC2_OVTH_1500UA (0x1 << 6)
1270#define RT5670_MIC2_OVTH_2000UA (0x2 << 6)
1271#define RT5670_PWR_MB_MASK (0x1 << 5)
1272#define RT5670_PWR_MB_SFT 5
1273#define RT5670_PWR_MB_PD (0x0 << 5)
1274#define RT5670_PWR_MB_PU (0x1 << 5)
1275#define RT5670_PWR_CLK25M_MASK (0x1 << 4)
1276#define RT5670_PWR_CLK25M_SFT 4
1277#define RT5670_PWR_CLK25M_PD (0x0 << 4)
1278#define RT5670_PWR_CLK25M_PU (0x1 << 4)
1279
1280/* Analog JD Control 1 (0x94) */
1281#define RT5670_JD1_MODE_MASK (0x3 << 0)
1282#define RT5670_JD1_MODE_0 (0x0 << 0)
1283#define RT5670_JD1_MODE_1 (0x1 << 0)
1284#define RT5670_JD1_MODE_2 (0x2 << 0)
1285
1286/* VAD Control 4 (0x9d) */
1287#define RT5670_VAD_SEL_MASK (0x3 << 8)
1288#define RT5670_VAD_SEL_SFT 8
1289
1290/* EQ Control 1 (0xb0) */
1291#define RT5670_EQ_SRC_MASK (0x1 << 15)
1292#define RT5670_EQ_SRC_SFT 15
1293#define RT5670_EQ_SRC_DAC (0x0 << 15)
1294#define RT5670_EQ_SRC_ADC (0x1 << 15)
1295#define RT5670_EQ_UPD (0x1 << 14)
1296#define RT5670_EQ_UPD_BIT 14
1297#define RT5670_EQ_CD_MASK (0x1 << 13)
1298#define RT5670_EQ_CD_SFT 13
1299#define RT5670_EQ_CD_DIS (0x0 << 13)
1300#define RT5670_EQ_CD_EN (0x1 << 13)
1301#define RT5670_EQ_DITH_MASK (0x3 << 8)
1302#define RT5670_EQ_DITH_SFT 8
1303#define RT5670_EQ_DITH_NOR (0x0 << 8)
1304#define RT5670_EQ_DITH_LSB (0x1 << 8)
1305#define RT5670_EQ_DITH_LSB_1 (0x2 << 8)
1306#define RT5670_EQ_DITH_LSB_2 (0x3 << 8)
1307
1308/* EQ Control 2 (0xb1) */
1309#define RT5670_EQ_HPF1_M_MASK (0x1 << 8)
1310#define RT5670_EQ_HPF1_M_SFT 8
1311#define RT5670_EQ_HPF1_M_HI (0x0 << 8)
1312#define RT5670_EQ_HPF1_M_1ST (0x1 << 8)
1313#define RT5670_EQ_LPF1_M_MASK (0x1 << 7)
1314#define RT5670_EQ_LPF1_M_SFT 7
1315#define RT5670_EQ_LPF1_M_LO (0x0 << 7)
1316#define RT5670_EQ_LPF1_M_1ST (0x1 << 7)
1317#define RT5670_EQ_HPF2_MASK (0x1 << 6)
1318#define RT5670_EQ_HPF2_SFT 6
1319#define RT5670_EQ_HPF2_DIS (0x0 << 6)
1320#define RT5670_EQ_HPF2_EN (0x1 << 6)
1321#define RT5670_EQ_HPF1_MASK (0x1 << 5)
1322#define RT5670_EQ_HPF1_SFT 5
1323#define RT5670_EQ_HPF1_DIS (0x0 << 5)
1324#define RT5670_EQ_HPF1_EN (0x1 << 5)
1325#define RT5670_EQ_BPF4_MASK (0x1 << 4)
1326#define RT5670_EQ_BPF4_SFT 4
1327#define RT5670_EQ_BPF4_DIS (0x0 << 4)
1328#define RT5670_EQ_BPF4_EN (0x1 << 4)
1329#define RT5670_EQ_BPF3_MASK (0x1 << 3)
1330#define RT5670_EQ_BPF3_SFT 3
1331#define RT5670_EQ_BPF3_DIS (0x0 << 3)
1332#define RT5670_EQ_BPF3_EN (0x1 << 3)
1333#define RT5670_EQ_BPF2_MASK (0x1 << 2)
1334#define RT5670_EQ_BPF2_SFT 2
1335#define RT5670_EQ_BPF2_DIS (0x0 << 2)
1336#define RT5670_EQ_BPF2_EN (0x1 << 2)
1337#define RT5670_EQ_BPF1_MASK (0x1 << 1)
1338#define RT5670_EQ_BPF1_SFT 1
1339#define RT5670_EQ_BPF1_DIS (0x0 << 1)
1340#define RT5670_EQ_BPF1_EN (0x1 << 1)
1341#define RT5670_EQ_LPF_MASK (0x1)
1342#define RT5670_EQ_LPF_SFT 0
1343#define RT5670_EQ_LPF_DIS (0x0)
1344#define RT5670_EQ_LPF_EN (0x1)
1345#define RT5670_EQ_CTRL_MASK (0x7f)
1346
1347/* Memory Test (0xb2) */
1348#define RT5670_MT_MASK (0x1 << 15)
1349#define RT5670_MT_SFT 15
1350#define RT5670_MT_DIS (0x0 << 15)
1351#define RT5670_MT_EN (0x1 << 15)
1352
1353/* DRC/AGC Control 1 (0xb4) */
1354#define RT5670_DRC_AGC_P_MASK (0x1 << 15)
1355#define RT5670_DRC_AGC_P_SFT 15
1356#define RT5670_DRC_AGC_P_DAC (0x0 << 15)
1357#define RT5670_DRC_AGC_P_ADC (0x1 << 15)
1358#define RT5670_DRC_AGC_MASK (0x1 << 14)
1359#define RT5670_DRC_AGC_SFT 14
1360#define RT5670_DRC_AGC_DIS (0x0 << 14)
1361#define RT5670_DRC_AGC_EN (0x1 << 14)
1362#define RT5670_DRC_AGC_UPD (0x1 << 13)
1363#define RT5670_DRC_AGC_UPD_BIT 13
1364#define RT5670_DRC_AGC_AR_MASK (0x1f << 8)
1365#define RT5670_DRC_AGC_AR_SFT 8
1366#define RT5670_DRC_AGC_R_MASK (0x7 << 5)
1367#define RT5670_DRC_AGC_R_SFT 5
1368#define RT5670_DRC_AGC_R_48K (0x1 << 5)
1369#define RT5670_DRC_AGC_R_96K (0x2 << 5)
1370#define RT5670_DRC_AGC_R_192K (0x3 << 5)
1371#define RT5670_DRC_AGC_R_441K (0x5 << 5)
1372#define RT5670_DRC_AGC_R_882K (0x6 << 5)
1373#define RT5670_DRC_AGC_R_1764K (0x7 << 5)
1374#define RT5670_DRC_AGC_RC_MASK (0x1f)
1375#define RT5670_DRC_AGC_RC_SFT 0
1376
1377/* DRC/AGC Control 2 (0xb5) */
1378#define RT5670_DRC_AGC_POB_MASK (0x3f << 8)
1379#define RT5670_DRC_AGC_POB_SFT 8
1380#define RT5670_DRC_AGC_CP_MASK (0x1 << 7)
1381#define RT5670_DRC_AGC_CP_SFT 7
1382#define RT5670_DRC_AGC_CP_DIS (0x0 << 7)
1383#define RT5670_DRC_AGC_CP_EN (0x1 << 7)
1384#define RT5670_DRC_AGC_CPR_MASK (0x3 << 5)
1385#define RT5670_DRC_AGC_CPR_SFT 5
1386#define RT5670_DRC_AGC_CPR_1_1 (0x0 << 5)
1387#define RT5670_DRC_AGC_CPR_1_2 (0x1 << 5)
1388#define RT5670_DRC_AGC_CPR_1_3 (0x2 << 5)
1389#define RT5670_DRC_AGC_CPR_1_4 (0x3 << 5)
1390#define RT5670_DRC_AGC_PRB_MASK (0x1f)
1391#define RT5670_DRC_AGC_PRB_SFT 0
1392
1393/* DRC/AGC Control 3 (0xb6) */
1394#define RT5670_DRC_AGC_NGB_MASK (0xf << 12)
1395#define RT5670_DRC_AGC_NGB_SFT 12
1396#define RT5670_DRC_AGC_TAR_MASK (0x1f << 7)
1397#define RT5670_DRC_AGC_TAR_SFT 7
1398#define RT5670_DRC_AGC_NG_MASK (0x1 << 6)
1399#define RT5670_DRC_AGC_NG_SFT 6
1400#define RT5670_DRC_AGC_NG_DIS (0x0 << 6)
1401#define RT5670_DRC_AGC_NG_EN (0x1 << 6)
1402#define RT5670_DRC_AGC_NGH_MASK (0x1 << 5)
1403#define RT5670_DRC_AGC_NGH_SFT 5
1404#define RT5670_DRC_AGC_NGH_DIS (0x0 << 5)
1405#define RT5670_DRC_AGC_NGH_EN (0x1 << 5)
1406#define RT5670_DRC_AGC_NGT_MASK (0x1f)
1407#define RT5670_DRC_AGC_NGT_SFT 0
1408
1409/* Jack Detect Control (0xbb) */
1410#define RT5670_JD_MASK (0x7 << 13)
1411#define RT5670_JD_SFT 13
1412#define RT5670_JD_DIS (0x0 << 13)
1413#define RT5670_JD_GPIO1 (0x1 << 13)
1414#define RT5670_JD_JD1_IN4P (0x2 << 13)
1415#define RT5670_JD_JD2_IN4N (0x3 << 13)
1416#define RT5670_JD_GPIO2 (0x4 << 13)
1417#define RT5670_JD_GPIO3 (0x5 << 13)
1418#define RT5670_JD_GPIO4 (0x6 << 13)
1419#define RT5670_JD_HP_MASK (0x1 << 11)
1420#define RT5670_JD_HP_SFT 11
1421#define RT5670_JD_HP_DIS (0x0 << 11)
1422#define RT5670_JD_HP_EN (0x1 << 11)
1423#define RT5670_JD_HP_TRG_MASK (0x1 << 10)
1424#define RT5670_JD_HP_TRG_SFT 10
1425#define RT5670_JD_HP_TRG_LO (0x0 << 10)
1426#define RT5670_JD_HP_TRG_HI (0x1 << 10)
1427#define RT5670_JD_SPL_MASK (0x1 << 9)
1428#define RT5670_JD_SPL_SFT 9
1429#define RT5670_JD_SPL_DIS (0x0 << 9)
1430#define RT5670_JD_SPL_EN (0x1 << 9)
1431#define RT5670_JD_SPL_TRG_MASK (0x1 << 8)
1432#define RT5670_JD_SPL_TRG_SFT 8
1433#define RT5670_JD_SPL_TRG_LO (0x0 << 8)
1434#define RT5670_JD_SPL_TRG_HI (0x1 << 8)
1435#define RT5670_JD_SPR_MASK (0x1 << 7)
1436#define RT5670_JD_SPR_SFT 7
1437#define RT5670_JD_SPR_DIS (0x0 << 7)
1438#define RT5670_JD_SPR_EN (0x1 << 7)
1439#define RT5670_JD_SPR_TRG_MASK (0x1 << 6)
1440#define RT5670_JD_SPR_TRG_SFT 6
1441#define RT5670_JD_SPR_TRG_LO (0x0 << 6)
1442#define RT5670_JD_SPR_TRG_HI (0x1 << 6)
1443#define RT5670_JD_MO_MASK (0x1 << 5)
1444#define RT5670_JD_MO_SFT 5
1445#define RT5670_JD_MO_DIS (0x0 << 5)
1446#define RT5670_JD_MO_EN (0x1 << 5)
1447#define RT5670_JD_MO_TRG_MASK (0x1 << 4)
1448#define RT5670_JD_MO_TRG_SFT 4
1449#define RT5670_JD_MO_TRG_LO (0x0 << 4)
1450#define RT5670_JD_MO_TRG_HI (0x1 << 4)
1451#define RT5670_JD_LO_MASK (0x1 << 3)
1452#define RT5670_JD_LO_SFT 3
1453#define RT5670_JD_LO_DIS (0x0 << 3)
1454#define RT5670_JD_LO_EN (0x1 << 3)
1455#define RT5670_JD_LO_TRG_MASK (0x1 << 2)
1456#define RT5670_JD_LO_TRG_SFT 2
1457#define RT5670_JD_LO_TRG_LO (0x0 << 2)
1458#define RT5670_JD_LO_TRG_HI (0x1 << 2)
1459#define RT5670_JD1_IN4P_MASK (0x1 << 1)
1460#define RT5670_JD1_IN4P_SFT 1
1461#define RT5670_JD1_IN4P_DIS (0x0 << 1)
1462#define RT5670_JD1_IN4P_EN (0x1 << 1)
1463#define RT5670_JD2_IN4N_MASK (0x1)
1464#define RT5670_JD2_IN4N_SFT 0
1465#define RT5670_JD2_IN4N_DIS (0x0)
1466#define RT5670_JD2_IN4N_EN (0x1)
1467
1468/* IRQ Control 1 (0xbd) */
1469#define RT5670_IRQ_JD_MASK (0x1 << 15)
1470#define RT5670_IRQ_JD_SFT 15
1471#define RT5670_IRQ_JD_BP (0x0 << 15)
1472#define RT5670_IRQ_JD_NOR (0x1 << 15)
1473#define RT5670_IRQ_OT_MASK (0x1 << 14)
1474#define RT5670_IRQ_OT_SFT 14
1475#define RT5670_IRQ_OT_BP (0x0 << 14)
1476#define RT5670_IRQ_OT_NOR (0x1 << 14)
1477#define RT5670_JD_STKY_MASK (0x1 << 13)
1478#define RT5670_JD_STKY_SFT 13
1479#define RT5670_JD_STKY_DIS (0x0 << 13)
1480#define RT5670_JD_STKY_EN (0x1 << 13)
1481#define RT5670_OT_STKY_MASK (0x1 << 12)
1482#define RT5670_OT_STKY_SFT 12
1483#define RT5670_OT_STKY_DIS (0x0 << 12)
1484#define RT5670_OT_STKY_EN (0x1 << 12)
1485#define RT5670_JD_P_MASK (0x1 << 11)
1486#define RT5670_JD_P_SFT 11
1487#define RT5670_JD_P_NOR (0x0 << 11)
1488#define RT5670_JD_P_INV (0x1 << 11)
1489#define RT5670_OT_P_MASK (0x1 << 10)
1490#define RT5670_OT_P_SFT 10
1491#define RT5670_OT_P_NOR (0x0 << 10)
1492#define RT5670_OT_P_INV (0x1 << 10)
1493#define RT5670_JD1_1_EN_MASK (0x1 << 9)
1494#define RT5670_JD1_1_EN_SFT 9
1495#define RT5670_JD1_1_DIS (0x0 << 9)
1496#define RT5670_JD1_1_EN (0x1 << 9)
1497
1498/* IRQ Control 2 (0xbe) */
1499#define RT5670_IRQ_MB1_OC_MASK (0x1 << 15)
1500#define RT5670_IRQ_MB1_OC_SFT 15
1501#define RT5670_IRQ_MB1_OC_BP (0x0 << 15)
1502#define RT5670_IRQ_MB1_OC_NOR (0x1 << 15)
1503#define RT5670_IRQ_MB2_OC_MASK (0x1 << 14)
1504#define RT5670_IRQ_MB2_OC_SFT 14
1505#define RT5670_IRQ_MB2_OC_BP (0x0 << 14)
1506#define RT5670_IRQ_MB2_OC_NOR (0x1 << 14)
1507#define RT5670_MB1_OC_STKY_MASK (0x1 << 11)
1508#define RT5670_MB1_OC_STKY_SFT 11
1509#define RT5670_MB1_OC_STKY_DIS (0x0 << 11)
1510#define RT5670_MB1_OC_STKY_EN (0x1 << 11)
1511#define RT5670_MB2_OC_STKY_MASK (0x1 << 10)
1512#define RT5670_MB2_OC_STKY_SFT 10
1513#define RT5670_MB2_OC_STKY_DIS (0x0 << 10)
1514#define RT5670_MB2_OC_STKY_EN (0x1 << 10)
1515#define RT5670_MB1_OC_P_MASK (0x1 << 7)
1516#define RT5670_MB1_OC_P_SFT 7
1517#define RT5670_MB1_OC_P_NOR (0x0 << 7)
1518#define RT5670_MB1_OC_P_INV (0x1 << 7)
1519#define RT5670_MB2_OC_P_MASK (0x1 << 6)
1520#define RT5670_MB2_OC_P_SFT 6
1521#define RT5670_MB2_OC_P_NOR (0x0 << 6)
1522#define RT5670_MB2_OC_P_INV (0x1 << 6)
1523#define RT5670_MB1_OC_CLR (0x1 << 3)
1524#define RT5670_MB1_OC_CLR_SFT 3
1525#define RT5670_MB2_OC_CLR (0x1 << 2)
1526#define RT5670_MB2_OC_CLR_SFT 2
1527
1528/* GPIO Control 1 (0xc0) */
1529#define RT5670_GP1_PIN_MASK (0x1 << 15)
1530#define RT5670_GP1_PIN_SFT 15
1531#define RT5670_GP1_PIN_GPIO1 (0x0 << 15)
1532#define RT5670_GP1_PIN_IRQ (0x1 << 15)
1533#define RT5670_GP2_PIN_MASK (0x1 << 14)
1534#define RT5670_GP2_PIN_SFT 14
1535#define RT5670_GP2_PIN_GPIO2 (0x0 << 14)
1536#define RT5670_GP2_PIN_DMIC1_SCL (0x1 << 14)
1537#define RT5670_GP3_PIN_MASK (0x3 << 12)
1538#define RT5670_GP3_PIN_SFT 12
1539#define RT5670_GP3_PIN_GPIO3 (0x0 << 12)
1540#define RT5670_GP3_PIN_DMIC1_SDA (0x1 << 12)
1541#define RT5670_GP3_PIN_IRQ (0x2 << 12)
1542#define RT5670_GP4_PIN_MASK (0x1 << 11)
1543#define RT5670_GP4_PIN_SFT 11
1544#define RT5670_GP4_PIN_GPIO4 (0x0 << 11)
1545#define RT5670_GP4_PIN_DMIC2_SDA (0x1 << 11)
1546#define RT5670_DP_SIG_MASK (0x1 << 10)
1547#define RT5670_DP_SIG_SFT 10
1548#define RT5670_DP_SIG_TEST (0x0 << 10)
1549#define RT5670_DP_SIG_AP (0x1 << 10)
1550#define RT5670_GPIO_M_MASK (0x1 << 9)
1551#define RT5670_GPIO_M_SFT 9
1552#define RT5670_GPIO_M_FLT (0x0 << 9)
1553#define RT5670_GPIO_M_PH (0x1 << 9)
1554#define RT5670_I2S2_PIN_MASK (0x1 << 8)
1555#define RT5670_I2S2_PIN_SFT 8
1556#define RT5670_I2S2_PIN_I2S (0x0 << 8)
1557#define RT5670_I2S2_PIN_GPIO (0x1 << 8)
1558#define RT5670_GP5_PIN_MASK (0x1 << 7)
1559#define RT5670_GP5_PIN_SFT 7
1560#define RT5670_GP5_PIN_GPIO5 (0x0 << 7)
1561#define RT5670_GP5_PIN_DMIC3_SDA (0x1 << 7)
1562#define RT5670_GP6_PIN_MASK (0x1 << 6)
1563#define RT5670_GP6_PIN_SFT 6
1564#define RT5670_GP6_PIN_GPIO6 (0x0 << 6)
1565#define RT5670_GP6_PIN_DMIC1_SDA (0x1 << 6)
1566#define RT5670_GP7_PIN_MASK (0x3 << 4)
1567#define RT5670_GP7_PIN_SFT 4
1568#define RT5670_GP7_PIN_GPIO7 (0x0 << 4)
1569#define RT5670_GP7_PIN_DMIC1_SDA (0x1 << 4)
1570#define RT5670_GP7_PIN_PDM_SCL2 (0x2 << 4)
1571#define RT5670_GP8_PIN_MASK (0x1 << 3)
1572#define RT5670_GP8_PIN_SFT 3
1573#define RT5670_GP8_PIN_GPIO8 (0x0 << 3)
1574#define RT5670_GP8_PIN_DMIC2_SDA (0x1 << 3)
1575#define RT5670_GP9_PIN_MASK (0x1 << 2)
1576#define RT5670_GP9_PIN_SFT 2
1577#define RT5670_GP9_PIN_GPIO9 (0x0 << 2)
1578#define RT5670_GP9_PIN_DMIC3_SDA (0x1 << 2)
1579#define RT5670_GP10_PIN_MASK (0x3)
1580#define RT5670_GP10_PIN_SFT 0
1581#define RT5670_GP10_PIN_GPIO9 (0x0)
1582#define RT5670_GP10_PIN_DMIC3_SDA (0x1)
1583#define RT5670_GP10_PIN_PDM_ADT2 (0x2)
1584
1585/* GPIO Control 2 (0xc1) */
1586#define RT5670_GP4_PF_MASK (0x1 << 11)
1587#define RT5670_GP4_PF_SFT 11
1588#define RT5670_GP4_PF_IN (0x0 << 11)
1589#define RT5670_GP4_PF_OUT (0x1 << 11)
1590#define RT5670_GP4_OUT_MASK (0x1 << 10)
1591#define RT5670_GP4_OUT_SFT 10
1592#define RT5670_GP4_OUT_LO (0x0 << 10)
1593#define RT5670_GP4_OUT_HI (0x1 << 10)
1594#define RT5670_GP4_P_MASK (0x1 << 9)
1595#define RT5670_GP4_P_SFT 9
1596#define RT5670_GP4_P_NOR (0x0 << 9)
1597#define RT5670_GP4_P_INV (0x1 << 9)
1598#define RT5670_GP3_PF_MASK (0x1 << 8)
1599#define RT5670_GP3_PF_SFT 8
1600#define RT5670_GP3_PF_IN (0x0 << 8)
1601#define RT5670_GP3_PF_OUT (0x1 << 8)
1602#define RT5670_GP3_OUT_MASK (0x1 << 7)
1603#define RT5670_GP3_OUT_SFT 7
1604#define RT5670_GP3_OUT_LO (0x0 << 7)
1605#define RT5670_GP3_OUT_HI (0x1 << 7)
1606#define RT5670_GP3_P_MASK (0x1 << 6)
1607#define RT5670_GP3_P_SFT 6
1608#define RT5670_GP3_P_NOR (0x0 << 6)
1609#define RT5670_GP3_P_INV (0x1 << 6)
1610#define RT5670_GP2_PF_MASK (0x1 << 5)
1611#define RT5670_GP2_PF_SFT 5
1612#define RT5670_GP2_PF_IN (0x0 << 5)
1613#define RT5670_GP2_PF_OUT (0x1 << 5)
1614#define RT5670_GP2_OUT_MASK (0x1 << 4)
1615#define RT5670_GP2_OUT_SFT 4
1616#define RT5670_GP2_OUT_LO (0x0 << 4)
1617#define RT5670_GP2_OUT_HI (0x1 << 4)
1618#define RT5670_GP2_P_MASK (0x1 << 3)
1619#define RT5670_GP2_P_SFT 3
1620#define RT5670_GP2_P_NOR (0x0 << 3)
1621#define RT5670_GP2_P_INV (0x1 << 3)
1622#define RT5670_GP1_PF_MASK (0x1 << 2)
1623#define RT5670_GP1_PF_SFT 2
1624#define RT5670_GP1_PF_IN (0x0 << 2)
1625#define RT5670_GP1_PF_OUT (0x1 << 2)
1626#define RT5670_GP1_OUT_MASK (0x1 << 1)
1627#define RT5670_GP1_OUT_SFT 1
1628#define RT5670_GP1_OUT_LO (0x0 << 1)
1629#define RT5670_GP1_OUT_HI (0x1 << 1)
1630#define RT5670_GP1_P_MASK (0x1)
1631#define RT5670_GP1_P_SFT 0
1632#define RT5670_GP1_P_NOR (0x0)
1633#define RT5670_GP1_P_INV (0x1)
1634
1635/* Scramble Function (0xcd) */
1636#define RT5670_SCB_KEY_MASK (0xff)
1637#define RT5670_SCB_KEY_SFT 0
1638
1639/* Scramble Control (0xce) */
1640#define RT5670_SCB_SWAP_MASK (0x1 << 15)
1641#define RT5670_SCB_SWAP_SFT 15
1642#define RT5670_SCB_SWAP_DIS (0x0 << 15)
1643#define RT5670_SCB_SWAP_EN (0x1 << 15)
1644#define RT5670_SCB_MASK (0x1 << 14)
1645#define RT5670_SCB_SFT 14
1646#define RT5670_SCB_DIS (0x0 << 14)
1647#define RT5670_SCB_EN (0x1 << 14)
1648
1649/* Baseback Control (0xcf) */
1650#define RT5670_BB_MASK (0x1 << 15)
1651#define RT5670_BB_SFT 15
1652#define RT5670_BB_DIS (0x0 << 15)
1653#define RT5670_BB_EN (0x1 << 15)
1654#define RT5670_BB_CT_MASK (0x7 << 12)
1655#define RT5670_BB_CT_SFT 12
1656#define RT5670_BB_CT_A (0x0 << 12)
1657#define RT5670_BB_CT_B (0x1 << 12)
1658#define RT5670_BB_CT_C (0x2 << 12)
1659#define RT5670_BB_CT_D (0x3 << 12)
1660#define RT5670_M_BB_L_MASK (0x1 << 9)
1661#define RT5670_M_BB_L_SFT 9
1662#define RT5670_M_BB_R_MASK (0x1 << 8)
1663#define RT5670_M_BB_R_SFT 8
1664#define RT5670_M_BB_HPF_L_MASK (0x1 << 7)
1665#define RT5670_M_BB_HPF_L_SFT 7
1666#define RT5670_M_BB_HPF_R_MASK (0x1 << 6)
1667#define RT5670_M_BB_HPF_R_SFT 6
1668#define RT5670_G_BB_BST_MASK (0x3f)
1669#define RT5670_G_BB_BST_SFT 0
1670
1671/* MP3 Plus Control 1 (0xd0) */
1672#define RT5670_M_MP3_L_MASK (0x1 << 15)
1673#define RT5670_M_MP3_L_SFT 15
1674#define RT5670_M_MP3_R_MASK (0x1 << 14)
1675#define RT5670_M_MP3_R_SFT 14
1676#define RT5670_M_MP3_MASK (0x1 << 13)
1677#define RT5670_M_MP3_SFT 13
1678#define RT5670_M_MP3_DIS (0x0 << 13)
1679#define RT5670_M_MP3_EN (0x1 << 13)
1680#define RT5670_EG_MP3_MASK (0x1f << 8)
1681#define RT5670_EG_MP3_SFT 8
1682#define RT5670_MP3_HLP_MASK (0x1 << 7)
1683#define RT5670_MP3_HLP_SFT 7
1684#define RT5670_MP3_HLP_DIS (0x0 << 7)
1685#define RT5670_MP3_HLP_EN (0x1 << 7)
1686#define RT5670_M_MP3_ORG_L_MASK (0x1 << 6)
1687#define RT5670_M_MP3_ORG_L_SFT 6
1688#define RT5670_M_MP3_ORG_R_MASK (0x1 << 5)
1689#define RT5670_M_MP3_ORG_R_SFT 5
1690
1691/* MP3 Plus Control 2 (0xd1) */
1692#define RT5670_MP3_WT_MASK (0x1 << 13)
1693#define RT5670_MP3_WT_SFT 13
1694#define RT5670_MP3_WT_1_4 (0x0 << 13)
1695#define RT5670_MP3_WT_1_2 (0x1 << 13)
1696#define RT5670_OG_MP3_MASK (0x1f << 8)
1697#define RT5670_OG_MP3_SFT 8
1698#define RT5670_HG_MP3_MASK (0x3f)
1699#define RT5670_HG_MP3_SFT 0
1700
1701/* 3D HP Control 1 (0xd2) */
1702#define RT5670_3D_CF_MASK (0x1 << 15)
1703#define RT5670_3D_CF_SFT 15
1704#define RT5670_3D_CF_DIS (0x0 << 15)
1705#define RT5670_3D_CF_EN (0x1 << 15)
1706#define RT5670_3D_HP_MASK (0x1 << 14)
1707#define RT5670_3D_HP_SFT 14
1708#define RT5670_3D_HP_DIS (0x0 << 14)
1709#define RT5670_3D_HP_EN (0x1 << 14)
1710#define RT5670_3D_BT_MASK (0x1 << 13)
1711#define RT5670_3D_BT_SFT 13
1712#define RT5670_3D_BT_DIS (0x0 << 13)
1713#define RT5670_3D_BT_EN (0x1 << 13)
1714#define RT5670_3D_1F_MIX_MASK (0x3 << 11)
1715#define RT5670_3D_1F_MIX_SFT 11
1716#define RT5670_3D_HP_M_MASK (0x1 << 10)
1717#define RT5670_3D_HP_M_SFT 10
1718#define RT5670_3D_HP_M_SUR (0x0 << 10)
1719#define RT5670_3D_HP_M_FRO (0x1 << 10)
1720#define RT5670_M_3D_HRTF_MASK (0x1 << 9)
1721#define RT5670_M_3D_HRTF_SFT 9
1722#define RT5670_M_3D_D2H_MASK (0x1 << 8)
1723#define RT5670_M_3D_D2H_SFT 8
1724#define RT5670_M_3D_D2R_MASK (0x1 << 7)
1725#define RT5670_M_3D_D2R_SFT 7
1726#define RT5670_M_3D_REVB_MASK (0x1 << 6)
1727#define RT5670_M_3D_REVB_SFT 6
1728
1729/* Adjustable high pass filter control 1 (0xd3) */
1730#define RT5670_2ND_HPF_MASK (0x1 << 15)
1731#define RT5670_2ND_HPF_SFT 15
1732#define RT5670_2ND_HPF_DIS (0x0 << 15)
1733#define RT5670_2ND_HPF_EN (0x1 << 15)
1734#define RT5670_HPF_CF_L_MASK (0x7 << 12)
1735#define RT5670_HPF_CF_L_SFT 12
1736#define RT5670_1ST_HPF_MASK (0x1 << 11)
1737#define RT5670_1ST_HPF_SFT 11
1738#define RT5670_1ST_HPF_DIS (0x0 << 11)
1739#define RT5670_1ST_HPF_EN (0x1 << 11)
1740#define RT5670_HPF_CF_R_MASK (0x7 << 8)
1741#define RT5670_HPF_CF_R_SFT 8
1742#define RT5670_ZD_T_MASK (0x3 << 6)
1743#define RT5670_ZD_T_SFT 6
1744#define RT5670_ZD_F_MASK (0x3 << 4)
1745#define RT5670_ZD_F_SFT 4
1746#define RT5670_ZD_F_IM (0x0 << 4)
1747#define RT5670_ZD_F_ZC_IM (0x1 << 4)
1748#define RT5670_ZD_F_ZC_IOD (0x2 << 4)
1749#define RT5670_ZD_F_UN (0x3 << 4)
1750
1751/* HP calibration control and Amp detection (0xd6) */
1752#define RT5670_SI_DAC_MASK (0x1 << 11)
1753#define RT5670_SI_DAC_SFT 11
1754#define RT5670_SI_DAC_AUTO (0x0 << 11)
1755#define RT5670_SI_DAC_TEST (0x1 << 11)
1756#define RT5670_DC_CAL_M_MASK (0x1 << 10)
1757#define RT5670_DC_CAL_M_SFT 10
1758#define RT5670_DC_CAL_M_CAL (0x0 << 10)
1759#define RT5670_DC_CAL_M_NOR (0x1 << 10)
1760#define RT5670_DC_CAL_MASK (0x1 << 9)
1761#define RT5670_DC_CAL_SFT 9
1762#define RT5670_DC_CAL_DIS (0x0 << 9)
1763#define RT5670_DC_CAL_EN (0x1 << 9)
1764#define RT5670_HPD_RCV_MASK (0x7 << 6)
1765#define RT5670_HPD_RCV_SFT 6
1766#define RT5670_HPD_PS_MASK (0x1 << 5)
1767#define RT5670_HPD_PS_SFT 5
1768#define RT5670_HPD_PS_DIS (0x0 << 5)
1769#define RT5670_HPD_PS_EN (0x1 << 5)
1770#define RT5670_CAL_M_MASK (0x1 << 4)
1771#define RT5670_CAL_M_SFT 4
1772#define RT5670_CAL_M_DEP (0x0 << 4)
1773#define RT5670_CAL_M_CAL (0x1 << 4)
1774#define RT5670_CAL_MASK (0x1 << 3)
1775#define RT5670_CAL_SFT 3
1776#define RT5670_CAL_DIS (0x0 << 3)
1777#define RT5670_CAL_EN (0x1 << 3)
1778#define RT5670_CAL_TEST_MASK (0x1 << 2)
1779#define RT5670_CAL_TEST_SFT 2
1780#define RT5670_CAL_TEST_DIS (0x0 << 2)
1781#define RT5670_CAL_TEST_EN (0x1 << 2)
1782#define RT5670_CAL_P_MASK (0x3)
1783#define RT5670_CAL_P_SFT 0
1784#define RT5670_CAL_P_NONE (0x0)
1785#define RT5670_CAL_P_CAL (0x1)
1786#define RT5670_CAL_P_DAC_CAL (0x2)
1787
1788/* Soft volume and zero cross control 1 (0xd9) */
1789#define RT5670_SV_MASK (0x1 << 15)
1790#define RT5670_SV_SFT 15
1791#define RT5670_SV_DIS (0x0 << 15)
1792#define RT5670_SV_EN (0x1 << 15)
1793#define RT5670_SPO_SV_MASK (0x1 << 14)
1794#define RT5670_SPO_SV_SFT 14
1795#define RT5670_SPO_SV_DIS (0x0 << 14)
1796#define RT5670_SPO_SV_EN (0x1 << 14)
1797#define RT5670_OUT_SV_MASK (0x1 << 13)
1798#define RT5670_OUT_SV_SFT 13
1799#define RT5670_OUT_SV_DIS (0x0 << 13)
1800#define RT5670_OUT_SV_EN (0x1 << 13)
1801#define RT5670_HP_SV_MASK (0x1 << 12)
1802#define RT5670_HP_SV_SFT 12
1803#define RT5670_HP_SV_DIS (0x0 << 12)
1804#define RT5670_HP_SV_EN (0x1 << 12)
1805#define RT5670_ZCD_DIG_MASK (0x1 << 11)
1806#define RT5670_ZCD_DIG_SFT 11
1807#define RT5670_ZCD_DIG_DIS (0x0 << 11)
1808#define RT5670_ZCD_DIG_EN (0x1 << 11)
1809#define RT5670_ZCD_MASK (0x1 << 10)
1810#define RT5670_ZCD_SFT 10
1811#define RT5670_ZCD_PD (0x0 << 10)
1812#define RT5670_ZCD_PU (0x1 << 10)
1813#define RT5670_M_ZCD_MASK (0x3f << 4)
1814#define RT5670_M_ZCD_SFT 4
1815#define RT5670_M_ZCD_RM_L (0x1 << 9)
1816#define RT5670_M_ZCD_RM_R (0x1 << 8)
1817#define RT5670_M_ZCD_SM_L (0x1 << 7)
1818#define RT5670_M_ZCD_SM_R (0x1 << 6)
1819#define RT5670_M_ZCD_OM_L (0x1 << 5)
1820#define RT5670_M_ZCD_OM_R (0x1 << 4)
1821#define RT5670_SV_DLY_MASK (0xf)
1822#define RT5670_SV_DLY_SFT 0
1823
1824/* Soft volume and zero cross control 2 (0xda) */
1825#define RT5670_ZCD_HP_MASK (0x1 << 15)
1826#define RT5670_ZCD_HP_SFT 15
1827#define RT5670_ZCD_HP_DIS (0x0 << 15)
1828#define RT5670_ZCD_HP_EN (0x1 << 15)
1829
1830
1831/* Codec Private Register definition */
1832/* 3D Speaker Control (0x63) */
1833#define RT5670_3D_SPK_MASK (0x1 << 15)
1834#define RT5670_3D_SPK_SFT 15
1835#define RT5670_3D_SPK_DIS (0x0 << 15)
1836#define RT5670_3D_SPK_EN (0x1 << 15)
1837#define RT5670_3D_SPK_M_MASK (0x3 << 13)
1838#define RT5670_3D_SPK_M_SFT 13
1839#define RT5670_3D_SPK_CG_MASK (0x1f << 8)
1840#define RT5670_3D_SPK_CG_SFT 8
1841#define RT5670_3D_SPK_SG_MASK (0x1f)
1842#define RT5670_3D_SPK_SG_SFT 0
1843
1844/* Wind Noise Detection Control 1 (0x6c) */
1845#define RT5670_WND_MASK (0x1 << 15)
1846#define RT5670_WND_SFT 15
1847#define RT5670_WND_DIS (0x0 << 15)
1848#define RT5670_WND_EN (0x1 << 15)
1849
1850/* Wind Noise Detection Control 2 (0x6d) */
1851#define RT5670_WND_FC_NW_MASK (0x3f << 10)
1852#define RT5670_WND_FC_NW_SFT 10
1853#define RT5670_WND_FC_WK_MASK (0x3f << 4)
1854#define RT5670_WND_FC_WK_SFT 4
1855
1856/* Wind Noise Detection Control 3 (0x6e) */
1857#define RT5670_HPF_FC_MASK (0x3f << 6)
1858#define RT5670_HPF_FC_SFT 6
1859#define RT5670_WND_FC_ST_MASK (0x3f)
1860#define RT5670_WND_FC_ST_SFT 0
1861
1862/* Wind Noise Detection Control 4 (0x6f) */
1863#define RT5670_WND_TH_LO_MASK (0x3ff)
1864#define RT5670_WND_TH_LO_SFT 0
1865
1866/* Wind Noise Detection Control 5 (0x70) */
1867#define RT5670_WND_TH_HI_MASK (0x3ff)
1868#define RT5670_WND_TH_HI_SFT 0
1869
1870/* Wind Noise Detection Control 8 (0x73) */
1871#define RT5670_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1872#define RT5670_WND_WIND_SFT 13
1873#define RT5670_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1874#define RT5670_WND_STRONG_SFT 12
1875enum {
1876 RT5670_NO_WIND,
1877 RT5670_BREEZE,
1878 RT5670_STORM,
1879};
1880
1881/* Dipole Speaker Interface (0x75) */
1882#define RT5670_DP_ATT_MASK (0x3 << 14)
1883#define RT5670_DP_ATT_SFT 14
1884#define RT5670_DP_SPK_MASK (0x1 << 10)
1885#define RT5670_DP_SPK_SFT 10
1886#define RT5670_DP_SPK_DIS (0x0 << 10)
1887#define RT5670_DP_SPK_EN (0x1 << 10)
1888
1889/* EQ Pre Volume Control (0xb3) */
1890#define RT5670_EQ_PRE_VOL_MASK (0xffff)
1891#define RT5670_EQ_PRE_VOL_SFT 0
1892
1893/* EQ Post Volume Control (0xb4) */
1894#define RT5670_EQ_PST_VOL_MASK (0xffff)
1895#define RT5670_EQ_PST_VOL_SFT 0
1896
1897/* Jack Detect Control 3 (0xf8) */
1898#define RT5670_CMP_MIC_IN_DET_MASK (0x7 << 12)
1899#define RT5670_JD_CBJ_EN (0x1 << 7)
1900#define RT5670_JD_CBJ_POL (0x1 << 6)
1901#define RT5670_JD_TRI_CBJ_SEL_MASK (0x7 << 3)
1902#define RT5670_JD_TRI_CBJ_SEL_SFT (3)
1903#define RT5670_JD_CBJ_GPIO_JD1 (0x0 << 3)
1904#define RT5670_JD_CBJ_JD1_1 (0x1 << 3)
1905#define RT5670_JD_CBJ_JD1_2 (0x2 << 3)
1906#define RT5670_JD_CBJ_JD2 (0x3 << 3)
1907#define RT5670_JD_CBJ_JD3 (0x4 << 3)
1908#define RT5670_JD_CBJ_GPIO_JD2 (0x5 << 3)
1909#define RT5670_JD_CBJ_MX0B_12 (0x6 << 3)
1910#define RT5670_JD_TRI_HPO_SEL_MASK (0x7 << 3)
1911#define RT5670_JD_TRI_HPO_SEL_SFT (0)
1912#define RT5670_JD_HPO_GPIO_JD1 (0x0)
1913#define RT5670_JD_HPO_JD1_1 (0x1)
1914#define RT5670_JD_HPO_JD1_2 (0x2)
1915#define RT5670_JD_HPO_JD2 (0x3)
1916#define RT5670_JD_HPO_JD3 (0x4)
1917#define RT5670_JD_HPO_GPIO_JD2 (0x5)
1918#define RT5670_JD_HPO_MX0B_12 (0x6)
1919
1920/* Digital Misc Control (0xfa) */
1921#define RT5670_RST_DSP (0x1 << 13)
1922#define RT5670_IF1_ADC1_IN1_SEL (0x1 << 12)
1923#define RT5670_IF1_ADC1_IN1_SFT 12
1924#define RT5670_IF1_ADC1_IN2_SEL (0x1 << 11)
1925#define RT5670_IF1_ADC1_IN2_SFT 11
1926#define RT5670_IF1_ADC2_IN1_SEL (0x1 << 10)
1927#define RT5670_IF1_ADC2_IN1_SFT 10
1928
1929/* General Control2 (0xfb) */
1930#define RT5670_RXDC_SRC_MASK (0x1 << 7)
1931#define RT5670_RXDC_SRC_STO (0x0 << 7)
1932#define RT5670_RXDC_SRC_MONO (0x1 << 7)
1933#define RT5670_RXDC_SRC_SFT (7)
1934#define RT5670_RXDP2_SEL_MASK (0x1 << 3)
1935#define RT5670_RXDP2_SEL_IF2 (0x0 << 3)
1936#define RT5670_RXDP2_SEL_ADC (0x1 << 3)
1937#define RT5670_RXDP2_SEL_SFT (3)
1938
1939/* System Clock Source */
1940enum {
1941 RT5670_SCLK_S_MCLK,
1942 RT5670_SCLK_S_PLL1,
1943 RT5670_SCLK_S_RCCLK,
1944};
1945
1946/* PLL1 Source */
1947enum {
1948 RT5670_PLL1_S_MCLK,
1949 RT5670_PLL1_S_BCLK1,
1950 RT5670_PLL1_S_BCLK2,
1951 RT5670_PLL1_S_BCLK3,
1952 RT5670_PLL1_S_BCLK4,
1953};
1954
1955enum {
1956 RT5670_AIF1,
1957 RT5670_AIF2,
1958 RT5670_AIF3,
1959 RT5670_AIF4,
1960 RT5670_AIFS,
1961};
1962
1963enum {
1964 RT5670_DMIC_DATA_GPIO6,
1965 RT5670_DMIC_DATA_IN2P,
1966 RT5670_DMIC_DATA_GPIO7,
1967};
1968
1969enum {
1970 RT5670_DMIC_DATA_GPIO8,
1971 RT5670_DMIC_DATA_IN3N,
1972};
1973
1974enum {
1975 RT5670_DMIC_DATA_GPIO9,
1976 RT5670_DMIC_DATA_GPIO10,
1977 RT5670_DMIC_DATA_GPIO5,
1978};
1979
1980struct rt5670_priv {
1981 struct snd_soc_codec *codec;
1982 struct rt5670_platform_data pdata;
1983 struct regmap *regmap;
1984
1985 int sysclk;
1986 int sysclk_src;
1987 int lrck[RT5670_AIFS];
1988 int bclk[RT5670_AIFS];
1989 int master[RT5670_AIFS];
1990
1991 int pll_src;
1992 int pll_in;
1993 int pll_out;
1994
1995 int dsp_sw; /* expected parameter setting */
1996 int dsp_rate;
1997 int jack_type;
1998};
1999
2000#endif /* __RT5670_H__ */
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c
index 833231e27340..67f14556462f 100644
--- a/sound/soc/codecs/rt5677.c
+++ b/sound/soc/codecs/rt5677.c
@@ -27,6 +27,7 @@
27#include <sound/initval.h> 27#include <sound/initval.h>
28#include <sound/tlv.h> 28#include <sound/tlv.h>
29 29
30#include "rl6231.h"
30#include "rt5677.h" 31#include "rt5677.h"
31 32
32#define RT5677_DEVICE_ID 0x6327 33#define RT5677_DEVICE_ID 0x6327
@@ -604,19 +605,19 @@ static const struct snd_kcontrol_new rt5677_snd_controls[] = {
604 adc_vol_tlv), 605 adc_vol_tlv),
605 606
606 /* ADC Boost Volume Control */ 607 /* ADC Boost Volume Control */
607 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5677_STO1_2_ADC_BST, 608 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
608 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0, 609 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
609 adc_bst_tlv), 610 adc_bst_tlv),
610 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5677_STO1_2_ADC_BST, 611 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
611 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0, 612 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
612 adc_bst_tlv), 613 adc_bst_tlv),
613 SOC_DOUBLE_TLV("STO3 ADC Boost Gain", RT5677_STO3_4_ADC_BST, 614 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
614 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0, 615 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
615 adc_bst_tlv), 616 adc_bst_tlv),
616 SOC_DOUBLE_TLV("STO4 ADC Boost Gain", RT5677_STO3_4_ADC_BST, 617 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
617 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0, 618 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
618 adc_bst_tlv), 619 adc_bst_tlv),
619 SOC_DOUBLE_TLV("Mono ADC Boost Gain", RT5677_ADC_BST_CTRL2, 620 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
620 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0, 621 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
621 adc_bst_tlv), 622 adc_bst_tlv),
622}; 623};
@@ -636,21 +637,7 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w,
636{ 637{
637 struct snd_soc_codec *codec = w->codec; 638 struct snd_soc_codec *codec = w->codec;
638 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 639 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
639 int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL, i; 640 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
640 int rate, red, bound, temp;
641
642 rate = rt5677->sysclk;
643 red = 3000000 * 12;
644 for (i = 0; i < ARRAY_SIZE(div); i++) {
645 bound = div[i] * 3000000;
646 if (rate > bound)
647 continue;
648 temp = bound - rate;
649 if (temp < red) {
650 red = temp;
651 idx = i;
652 }
653 }
654 641
655 if (idx < 0) 642 if (idx < 0)
656 dev_err(codec->dev, "Failed to set DMIC clock\n"); 643 dev_err(codec->dev, "Failed to set DMIC clock\n");
@@ -951,7 +938,7 @@ static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
951 938
952 939
953/* Mux */ 940/* Mux */
954/* DAC1 L/R source */ /* MX-29 [10:8] */ 941/* DAC1 L/R Source */ /* MX-29 [10:8] */
955static const char * const rt5677_dac1_src[] = { 942static const char * const rt5677_dac1_src[] = {
956 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01", 943 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
957 "OB 01" 944 "OB 01"
@@ -962,9 +949,9 @@ static SOC_ENUM_SINGLE_DECL(
962 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src); 949 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
963 950
964static const struct snd_kcontrol_new rt5677_dac1_mux = 951static const struct snd_kcontrol_new rt5677_dac1_mux =
965 SOC_DAPM_ENUM("DAC1 source", rt5677_dac1_enum); 952 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
966 953
967/* ADDA1 L/R source */ /* MX-29 [1:0] */ 954/* ADDA1 L/R Source */ /* MX-29 [1:0] */
968static const char * const rt5677_adda1_src[] = { 955static const char * const rt5677_adda1_src[] = {
969 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67", 956 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
970}; 957};
@@ -974,10 +961,10 @@ static SOC_ENUM_SINGLE_DECL(
974 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src); 961 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
975 962
976static const struct snd_kcontrol_new rt5677_adda1_mux = 963static const struct snd_kcontrol_new rt5677_adda1_mux =
977 SOC_DAPM_ENUM("ADDA1 source", rt5677_adda1_enum); 964 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
978 965
979 966
980/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */ 967/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
981static const char * const rt5677_dac2l_src[] = { 968static const char * const rt5677_dac2l_src[] = {
982 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2", 969 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
983 "OB 2", 970 "OB 2",
@@ -988,7 +975,7 @@ static SOC_ENUM_SINGLE_DECL(
988 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src); 975 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
989 976
990static const struct snd_kcontrol_new rt5677_dac2_l_mux = 977static const struct snd_kcontrol_new rt5677_dac2_l_mux =
991 SOC_DAPM_ENUM("DAC2 L source", rt5677_dac2l_enum); 978 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
992 979
993static const char * const rt5677_dac2r_src[] = { 980static const char * const rt5677_dac2r_src[] = {
994 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3", 981 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
@@ -1000,9 +987,9 @@ static SOC_ENUM_SINGLE_DECL(
1000 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src); 987 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1001 988
1002static const struct snd_kcontrol_new rt5677_dac2_r_mux = 989static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1003 SOC_DAPM_ENUM("DAC2 R source", rt5677_dac2r_enum); 990 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1004 991
1005/*DAC3 L/R source*/ /* MX-16 [6:4] [2:0] */ 992/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1006static const char * const rt5677_dac3l_src[] = { 993static const char * const rt5677_dac3l_src[] = {
1007 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L", 994 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1008 "SLB DAC 4", "OB 4" 995 "SLB DAC 4", "OB 4"
@@ -1013,7 +1000,7 @@ static SOC_ENUM_SINGLE_DECL(
1013 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src); 1000 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1014 1001
1015static const struct snd_kcontrol_new rt5677_dac3_l_mux = 1002static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1016 SOC_DAPM_ENUM("DAC3 L source", rt5677_dac3l_enum); 1003 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1017 1004
1018static const char * const rt5677_dac3r_src[] = { 1005static const char * const rt5677_dac3r_src[] = {
1019 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R", 1006 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
@@ -1025,9 +1012,9 @@ static SOC_ENUM_SINGLE_DECL(
1025 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src); 1012 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1026 1013
1027static const struct snd_kcontrol_new rt5677_dac3_r_mux = 1014static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1028 SOC_DAPM_ENUM("DAC3 R source", rt5677_dac3r_enum); 1015 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1029 1016
1030/*DAC4 L/R source*/ /* MX-16 [14:12] [10:8] */ 1017/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1031static const char * const rt5677_dac4l_src[] = { 1018static const char * const rt5677_dac4l_src[] = {
1032 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L", 1019 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1033 "SLB DAC 6", "OB 6" 1020 "SLB DAC 6", "OB 6"
@@ -1038,7 +1025,7 @@ static SOC_ENUM_SINGLE_DECL(
1038 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src); 1025 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1039 1026
1040static const struct snd_kcontrol_new rt5677_dac4_l_mux = 1027static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1041 SOC_DAPM_ENUM("DAC4 L source", rt5677_dac4l_enum); 1028 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1042 1029
1043static const char * const rt5677_dac4r_src[] = { 1030static const char * const rt5677_dac4r_src[] = {
1044 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R", 1031 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
@@ -1050,7 +1037,7 @@ static SOC_ENUM_SINGLE_DECL(
1050 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src); 1037 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1051 1038
1052static const struct snd_kcontrol_new rt5677_dac4_r_mux = 1039static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1053 SOC_DAPM_ENUM("DAC4 R source", rt5677_dac4r_enum); 1040 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1054 1041
1055/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */ 1042/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1056static const char * const rt5677_iob_bypass_src[] = { 1043static const char * const rt5677_iob_bypass_src[] = {
@@ -1062,35 +1049,35 @@ static SOC_ENUM_SINGLE_DECL(
1062 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src); 1049 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1063 1050
1064static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux = 1051static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1065 SOC_DAPM_ENUM("OB01 Bypass source", rt5677_ob01_bypass_src_enum); 1052 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1066 1053
1067static SOC_ENUM_SINGLE_DECL( 1054static SOC_ENUM_SINGLE_DECL(
1068 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1055 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1069 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src); 1056 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1070 1057
1071static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux = 1058static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1072 SOC_DAPM_ENUM("OB23 Bypass source", rt5677_ob23_bypass_src_enum); 1059 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1073 1060
1074static SOC_ENUM_SINGLE_DECL( 1061static SOC_ENUM_SINGLE_DECL(
1075 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1062 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1076 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src); 1063 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1077 1064
1078static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux = 1065static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1079 SOC_DAPM_ENUM("IB01 Bypass source", rt5677_ib01_bypass_src_enum); 1066 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1080 1067
1081static SOC_ENUM_SINGLE_DECL( 1068static SOC_ENUM_SINGLE_DECL(
1082 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1069 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1083 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src); 1070 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1084 1071
1085static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux = 1072static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1086 SOC_DAPM_ENUM("IB23 Bypass source", rt5677_ib23_bypass_src_enum); 1073 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1087 1074
1088static SOC_ENUM_SINGLE_DECL( 1075static SOC_ENUM_SINGLE_DECL(
1089 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, 1076 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1090 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src); 1077 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1091 1078
1092static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux = 1079static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1093 SOC_DAPM_ENUM("IB45 Bypass source", rt5677_ib45_bypass_src_enum); 1080 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1094 1081
1095/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */ 1082/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1096static const char * const rt5677_stereo_adc2_src[] = { 1083static const char * const rt5677_stereo_adc2_src[] = {
@@ -1102,21 +1089,21 @@ static SOC_ENUM_SINGLE_DECL(
1102 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src); 1089 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1103 1090
1104static const struct snd_kcontrol_new rt5677_sto1_adc2_mux = 1091static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1105 SOC_DAPM_ENUM("Stereo1 ADC2 source", rt5677_stereo1_adc2_enum); 1092 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1106 1093
1107static SOC_ENUM_SINGLE_DECL( 1094static SOC_ENUM_SINGLE_DECL(
1108 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER, 1095 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1109 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src); 1096 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1110 1097
1111static const struct snd_kcontrol_new rt5677_sto2_adc2_mux = 1098static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1112 SOC_DAPM_ENUM("Stereo2 ADC2 source", rt5677_stereo2_adc2_enum); 1099 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1113 1100
1114static SOC_ENUM_SINGLE_DECL( 1101static SOC_ENUM_SINGLE_DECL(
1115 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER, 1102 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1116 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src); 1103 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1117 1104
1118static const struct snd_kcontrol_new rt5677_sto3_adc2_mux = 1105static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1119 SOC_DAPM_ENUM("Stereo3 ADC2 source", rt5677_stereo3_adc2_enum); 1106 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1120 1107
1121/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */ 1108/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1122static const char * const rt5677_dmic_src[] = { 1109static const char * const rt5677_dmic_src[] = {
@@ -1128,44 +1115,44 @@ static SOC_ENUM_SINGLE_DECL(
1128 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src); 1115 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1129 1116
1130static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux = 1117static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1131 SOC_DAPM_ENUM("Mono DMIC L source", rt5677_mono_dmic_l_enum); 1118 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1132 1119
1133static SOC_ENUM_SINGLE_DECL( 1120static SOC_ENUM_SINGLE_DECL(
1134 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER, 1121 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1135 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src); 1122 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1136 1123
1137static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux = 1124static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1138 SOC_DAPM_ENUM("Mono DMIC R source", rt5677_mono_dmic_r_enum); 1125 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1139 1126
1140static SOC_ENUM_SINGLE_DECL( 1127static SOC_ENUM_SINGLE_DECL(
1141 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER, 1128 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1142 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src); 1129 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1143 1130
1144static const struct snd_kcontrol_new rt5677_sto1_dmic_mux = 1131static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1145 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5677_stereo1_dmic_enum); 1132 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1146 1133
1147static SOC_ENUM_SINGLE_DECL( 1134static SOC_ENUM_SINGLE_DECL(
1148 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER, 1135 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1149 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src); 1136 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1150 1137
1151static const struct snd_kcontrol_new rt5677_sto2_dmic_mux = 1138static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1152 SOC_DAPM_ENUM("Stereo2 DMIC source", rt5677_stereo2_dmic_enum); 1139 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1153 1140
1154static SOC_ENUM_SINGLE_DECL( 1141static SOC_ENUM_SINGLE_DECL(
1155 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER, 1142 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1156 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src); 1143 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1157 1144
1158static const struct snd_kcontrol_new rt5677_sto3_dmic_mux = 1145static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1159 SOC_DAPM_ENUM("Stereo3 DMIC source", rt5677_stereo3_dmic_enum); 1146 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1160 1147
1161static SOC_ENUM_SINGLE_DECL( 1148static SOC_ENUM_SINGLE_DECL(
1162 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER, 1149 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1163 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src); 1150 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1164 1151
1165static const struct snd_kcontrol_new rt5677_sto4_dmic_mux = 1152static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1166 SOC_DAPM_ENUM("Stereo4 DMIC source", rt5677_stereo4_dmic_enum); 1153 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1167 1154
1168/* Stereo2 ADC source */ /* MX-26 [0] */ 1155/* Stereo2 ADC Source */ /* MX-26 [0] */
1169static const char * const rt5677_stereo2_adc_lr_src[] = { 1156static const char * const rt5677_stereo2_adc_lr_src[] = {
1170 "L", "LR" 1157 "L", "LR"
1171}; 1158};
@@ -1175,7 +1162,7 @@ static SOC_ENUM_SINGLE_DECL(
1175 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src); 1162 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1176 1163
1177static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux = 1164static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1178 SOC_DAPM_ENUM("Stereo2 ADC LR source", rt5677_stereo2_adc_lr_enum); 1165 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1179 1166
1180/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */ 1167/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1181static const char * const rt5677_stereo_adc1_src[] = { 1168static const char * const rt5677_stereo_adc1_src[] = {
@@ -1187,23 +1174,23 @@ static SOC_ENUM_SINGLE_DECL(
1187 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src); 1174 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1188 1175
1189static const struct snd_kcontrol_new rt5677_sto1_adc1_mux = 1176static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1190 SOC_DAPM_ENUM("Stereo1 ADC1 source", rt5677_stereo1_adc1_enum); 1177 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1191 1178
1192static SOC_ENUM_SINGLE_DECL( 1179static SOC_ENUM_SINGLE_DECL(
1193 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER, 1180 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1194 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src); 1181 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1195 1182
1196static const struct snd_kcontrol_new rt5677_sto2_adc1_mux = 1183static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1197 SOC_DAPM_ENUM("Stereo2 ADC1 source", rt5677_stereo2_adc1_enum); 1184 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1198 1185
1199static SOC_ENUM_SINGLE_DECL( 1186static SOC_ENUM_SINGLE_DECL(
1200 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER, 1187 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1201 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src); 1188 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1202 1189
1203static const struct snd_kcontrol_new rt5677_sto3_adc1_mux = 1190static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1204 SOC_DAPM_ENUM("Stereo3 ADC1 source", rt5677_stereo3_adc1_enum); 1191 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1205 1192
1206/* Mono ADC Left source 2 */ /* MX-28 [11:10] */ 1193/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1207static const char * const rt5677_mono_adc2_l_src[] = { 1194static const char * const rt5677_mono_adc2_l_src[] = {
1208 "DD MIX1L", "DMIC", "MONO DAC MIXL" 1195 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1209}; 1196};
@@ -1213,9 +1200,9 @@ static SOC_ENUM_SINGLE_DECL(
1213 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src); 1200 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1214 1201
1215static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux = 1202static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1216 SOC_DAPM_ENUM("Mono ADC2 L source", rt5677_mono_adc2_l_enum); 1203 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1217 1204
1218/* Mono ADC Left source 1 */ /* MX-28 [13:12] */ 1205/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1219static const char * const rt5677_mono_adc1_l_src[] = { 1206static const char * const rt5677_mono_adc1_l_src[] = {
1220 "DD MIX1L", "ADC1", "MONO DAC MIXL" 1207 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1221}; 1208};
@@ -1225,9 +1212,9 @@ static SOC_ENUM_SINGLE_DECL(
1225 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src); 1212 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1226 1213
1227static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux = 1214static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1228 SOC_DAPM_ENUM("Mono ADC1 L source", rt5677_mono_adc1_l_enum); 1215 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1229 1216
1230/* Mono ADC Right source 2 */ /* MX-28 [3:2] */ 1217/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1231static const char * const rt5677_mono_adc2_r_src[] = { 1218static const char * const rt5677_mono_adc2_r_src[] = {
1232 "DD MIX1R", "DMIC", "MONO DAC MIXR" 1219 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1233}; 1220};
@@ -1237,9 +1224,9 @@ static SOC_ENUM_SINGLE_DECL(
1237 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src); 1224 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1238 1225
1239static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux = 1226static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1240 SOC_DAPM_ENUM("Mono ADC2 R source", rt5677_mono_adc2_r_enum); 1227 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1241 1228
1242/* Mono ADC Right source 1 */ /* MX-28 [5:4] */ 1229/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1243static const char * const rt5677_mono_adc1_r_src[] = { 1230static const char * const rt5677_mono_adc1_r_src[] = {
1244 "DD MIX1R", "ADC2", "MONO DAC MIXR" 1231 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1245}; 1232};
@@ -1249,7 +1236,7 @@ static SOC_ENUM_SINGLE_DECL(
1249 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src); 1236 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1250 1237
1251static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux = 1238static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1252 SOC_DAPM_ENUM("Mono ADC1 R source", rt5677_mono_adc1_r_enum); 1239 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1253 1240
1254/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */ 1241/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1255static const char * const rt5677_stereo4_adc2_src[] = { 1242static const char * const rt5677_stereo4_adc2_src[] = {
@@ -1261,7 +1248,7 @@ static SOC_ENUM_SINGLE_DECL(
1261 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src); 1248 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1262 1249
1263static const struct snd_kcontrol_new rt5677_sto4_adc2_mux = 1250static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1264 SOC_DAPM_ENUM("Stereo4 ADC2 source", rt5677_stereo4_adc2_enum); 1251 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1265 1252
1266 1253
1267/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */ 1254/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
@@ -1274,7 +1261,7 @@ static SOC_ENUM_SINGLE_DECL(
1274 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src); 1261 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1275 1262
1276static const struct snd_kcontrol_new rt5677_sto4_adc1_mux = 1263static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1277 SOC_DAPM_ENUM("Stereo4 ADC1 source", rt5677_stereo4_adc1_enum); 1264 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1278 1265
1279/* InBound0/1 Source */ /* MX-A3 [14:12] */ 1266/* InBound0/1 Source */ /* MX-A3 [14:12] */
1280static const char * const rt5677_inbound01_src[] = { 1267static const char * const rt5677_inbound01_src[] = {
@@ -1416,7 +1403,7 @@ static SOC_ENUM_SINGLE_DECL(
1416static const struct snd_kcontrol_new rt5677_dac3_mux = 1403static const struct snd_kcontrol_new rt5677_dac3_mux =
1417 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum); 1404 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1418 1405
1419/* PDM channel source */ /* MX-31 [13:12][9:8][5:4][1:0] */ 1406/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
1420static const char * const rt5677_pdm_src[] = { 1407static const char * const rt5677_pdm_src[] = {
1421 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" 1408 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1422}; 1409};
@@ -1426,28 +1413,28 @@ static SOC_ENUM_SINGLE_DECL(
1426 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src); 1413 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1427 1414
1428static const struct snd_kcontrol_new rt5677_pdm1_l_mux = 1415static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1429 SOC_DAPM_ENUM("PDM1 source", rt5677_pdm1_l_enum); 1416 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
1430 1417
1431static SOC_ENUM_SINGLE_DECL( 1418static SOC_ENUM_SINGLE_DECL(
1432 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL, 1419 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1433 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src); 1420 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1434 1421
1435static const struct snd_kcontrol_new rt5677_pdm2_l_mux = 1422static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1436 SOC_DAPM_ENUM("PDM2 source", rt5677_pdm2_l_enum); 1423 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
1437 1424
1438static SOC_ENUM_SINGLE_DECL( 1425static SOC_ENUM_SINGLE_DECL(
1439 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL, 1426 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1440 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src); 1427 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1441 1428
1442static const struct snd_kcontrol_new rt5677_pdm1_r_mux = 1429static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1443 SOC_DAPM_ENUM("PDM1 source", rt5677_pdm1_r_enum); 1430 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
1444 1431
1445static SOC_ENUM_SINGLE_DECL( 1432static SOC_ENUM_SINGLE_DECL(
1446 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL, 1433 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1447 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src); 1434 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1448 1435
1449static const struct snd_kcontrol_new rt5677_pdm2_r_mux = 1436static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1450 SOC_DAPM_ENUM("PDM2 source", rt5677_pdm2_r_enum); 1437 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
1451 1438
1452/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0]*/ 1439/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0]*/
1453static const char * const rt5677_if12_adc1_src[] = { 1440static const char * const rt5677_if12_adc1_src[] = {
@@ -1459,21 +1446,21 @@ static SOC_ENUM_SINGLE_DECL(
1459 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src); 1446 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1460 1447
1461static const struct snd_kcontrol_new rt5677_if1_adc1_mux = 1448static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1462 SOC_DAPM_ENUM("IF1 ADC1 source", rt5677_if1_adc1_enum); 1449 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
1463 1450
1464static SOC_ENUM_SINGLE_DECL( 1451static SOC_ENUM_SINGLE_DECL(
1465 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2, 1452 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1466 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src); 1453 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1467 1454
1468static const struct snd_kcontrol_new rt5677_if2_adc1_mux = 1455static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1469 SOC_DAPM_ENUM("IF2 ADC1 source", rt5677_if2_adc1_enum); 1456 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
1470 1457
1471static SOC_ENUM_SINGLE_DECL( 1458static SOC_ENUM_SINGLE_DECL(
1472 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX, 1459 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1473 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src); 1460 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1474 1461
1475static const struct snd_kcontrol_new rt5677_slb_adc1_mux = 1462static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1476 SOC_DAPM_ENUM("SLB ADC1 source", rt5677_slb_adc1_enum); 1463 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
1477 1464
1478/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */ 1465/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1479static const char * const rt5677_if12_adc2_src[] = { 1466static const char * const rt5677_if12_adc2_src[] = {
@@ -1485,21 +1472,21 @@ static SOC_ENUM_SINGLE_DECL(
1485 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src); 1472 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1486 1473
1487static const struct snd_kcontrol_new rt5677_if1_adc2_mux = 1474static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1488 SOC_DAPM_ENUM("IF1 ADC2 source", rt5677_if1_adc2_enum); 1475 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
1489 1476
1490static SOC_ENUM_SINGLE_DECL( 1477static SOC_ENUM_SINGLE_DECL(
1491 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2, 1478 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1492 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src); 1479 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1493 1480
1494static const struct snd_kcontrol_new rt5677_if2_adc2_mux = 1481static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1495 SOC_DAPM_ENUM("IF2 ADC2 source", rt5677_if2_adc2_enum); 1482 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
1496 1483
1497static SOC_ENUM_SINGLE_DECL( 1484static SOC_ENUM_SINGLE_DECL(
1498 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX, 1485 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1499 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src); 1486 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1500 1487
1501static const struct snd_kcontrol_new rt5677_slb_adc2_mux = 1488static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1502 SOC_DAPM_ENUM("SLB ADC2 source", rt5677_slb_adc2_enum); 1489 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
1503 1490
1504/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */ 1491/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1505static const char * const rt5677_if12_adc3_src[] = { 1492static const char * const rt5677_if12_adc3_src[] = {
@@ -1511,21 +1498,21 @@ static SOC_ENUM_SINGLE_DECL(
1511 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src); 1498 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1512 1499
1513static const struct snd_kcontrol_new rt5677_if1_adc3_mux = 1500static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1514 SOC_DAPM_ENUM("IF1 ADC3 source", rt5677_if1_adc3_enum); 1501 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
1515 1502
1516static SOC_ENUM_SINGLE_DECL( 1503static SOC_ENUM_SINGLE_DECL(
1517 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2, 1504 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1518 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src); 1505 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1519 1506
1520static const struct snd_kcontrol_new rt5677_if2_adc3_mux = 1507static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1521 SOC_DAPM_ENUM("IF2 ADC3 source", rt5677_if2_adc3_enum); 1508 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
1522 1509
1523static SOC_ENUM_SINGLE_DECL( 1510static SOC_ENUM_SINGLE_DECL(
1524 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX, 1511 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1525 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src); 1512 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1526 1513
1527static const struct snd_kcontrol_new rt5677_slb_adc3_mux = 1514static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1528 SOC_DAPM_ENUM("SLB ADC3 source", rt5677_slb_adc3_enum); 1515 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
1529 1516
1530/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */ 1517/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1531static const char * const rt5677_if12_adc4_src[] = { 1518static const char * const rt5677_if12_adc4_src[] = {
@@ -1537,21 +1524,21 @@ static SOC_ENUM_SINGLE_DECL(
1537 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src); 1524 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1538 1525
1539static const struct snd_kcontrol_new rt5677_if1_adc4_mux = 1526static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1540 SOC_DAPM_ENUM("IF1 ADC4 source", rt5677_if1_adc4_enum); 1527 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
1541 1528
1542static SOC_ENUM_SINGLE_DECL( 1529static SOC_ENUM_SINGLE_DECL(
1543 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2, 1530 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1544 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src); 1531 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1545 1532
1546static const struct snd_kcontrol_new rt5677_if2_adc4_mux = 1533static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1547 SOC_DAPM_ENUM("IF2 ADC4 source", rt5677_if2_adc4_enum); 1534 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
1548 1535
1549static SOC_ENUM_SINGLE_DECL( 1536static SOC_ENUM_SINGLE_DECL(
1550 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX, 1537 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1551 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src); 1538 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1552 1539
1553static const struct snd_kcontrol_new rt5677_slb_adc4_mux = 1540static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1554 SOC_DAPM_ENUM("SLB ADC4 source", rt5677_slb_adc4_enum); 1541 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
1555 1542
1556/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4]*/ 1543/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4]*/
1557static const char * const rt5677_if34_adc_src[] = { 1544static const char * const rt5677_if34_adc_src[] = {
@@ -1564,14 +1551,14 @@ static SOC_ENUM_SINGLE_DECL(
1564 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src); 1551 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1565 1552
1566static const struct snd_kcontrol_new rt5677_if3_adc_mux = 1553static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1567 SOC_DAPM_ENUM("IF3 ADC source", rt5677_if3_adc_enum); 1554 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
1568 1555
1569static SOC_ENUM_SINGLE_DECL( 1556static SOC_ENUM_SINGLE_DECL(
1570 rt5677_if4_adc_enum, RT5677_IF4_DATA, 1557 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1571 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src); 1558 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1572 1559
1573static const struct snd_kcontrol_new rt5677_if4_adc_mux = 1560static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1574 SOC_DAPM_ENUM("IF4 ADC source", rt5677_if4_adc_enum); 1561 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
1575 1562
1576static int rt5677_bst1_event(struct snd_soc_dapm_widget *w, 1563static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
1577 struct snd_kcontrol *kcontrol, int event) 1564 struct snd_kcontrol *kcontrol, int event)
@@ -1670,6 +1657,13 @@ static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
1670 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 | 1657 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
1671 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB); 1658 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
1672 break; 1659 break;
1660
1661 case SND_SOC_DAPM_PRE_PMD:
1662 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1663 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
1664 RT5677_PWR_CLK_MB, 0);
1665 break;
1666
1673 default: 1667 default:
1674 return 0; 1668 return 0;
1675 } 1669 }
@@ -1685,8 +1679,9 @@ static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
1685 1679
1686 /* Input Side */ 1680 /* Input Side */
1687 /* micbias */ 1681 /* micbias */
1688 SND_SOC_DAPM_SUPPLY("micbias1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT, 1682 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
1689 0, rt5677_set_micbias1_event, SND_SOC_DAPM_POST_PMU), 1683 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
1684 SND_SOC_DAPM_POST_PMU),
1690 1685
1691 /* Input Lines */ 1686 /* Input Lines */
1692 SND_SOC_DAPM_INPUT("DMIC L1"), 1687 SND_SOC_DAPM_INPUT("DMIC L1"),
@@ -2798,21 +2793,6 @@ static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2798 { "PDM2R", NULL, "PDM2 R Mux" }, 2793 { "PDM2R", NULL, "PDM2 R Mux" },
2799}; 2794};
2800 2795
2801static int get_clk_info(int sclk, int rate)
2802{
2803 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
2804
2805 if (sclk <= 0 || rate <= 0)
2806 return -EINVAL;
2807
2808 rate = rate << 8;
2809 for (i = 0; i < ARRAY_SIZE(pd); i++)
2810 if (sclk == rate * pd[i])
2811 return i;
2812
2813 return -EINVAL;
2814}
2815
2816static int rt5677_hw_params(struct snd_pcm_substream *substream, 2796static int rt5677_hw_params(struct snd_pcm_substream *substream,
2817 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2797 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2818{ 2798{
@@ -2822,7 +2802,7 @@ static int rt5677_hw_params(struct snd_pcm_substream *substream,
2822 int pre_div, bclk_ms, frame_size; 2802 int pre_div, bclk_ms, frame_size;
2823 2803
2824 rt5677->lrck[dai->id] = params_rate(params); 2804 rt5677->lrck[dai->id] = params_rate(params);
2825 pre_div = get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); 2805 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
2826 if (pre_div < 0) { 2806 if (pre_div < 0) {
2827 dev_err(codec->dev, "Unsupported clock setting\n"); 2807 dev_err(codec->dev, "Unsupported clock setting\n");
2828 return -EINVAL; 2808 return -EINVAL;
@@ -3016,62 +2996,12 @@ static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
3016 * Returns 0 for success or negative error code. 2996 * Returns 0 for success or negative error code.
3017 */ 2997 */
3018static int rt5677_pll_calc(const unsigned int freq_in, 2998static int rt5677_pll_calc(const unsigned int freq_in,
3019 const unsigned int freq_out, struct rt5677_pll_code *pll_code) 2999 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
3020{ 3000{
3021 int max_n = RT5677_PLL_N_MAX, max_m = RT5677_PLL_M_MAX; 3001 if (RT5677_PLL_INP_MIN > freq_in)
3022 int k, red, n_t, pll_out, in_t;
3023 int n = 0, m = 0, m_t = 0;
3024 int out_t, red_t = abs(freq_out - freq_in);
3025 bool m_bp = false, k_bp = false;
3026
3027 if (RT5677_PLL_INP_MAX < freq_in || RT5677_PLL_INP_MIN > freq_in)
3028 return -EINVAL; 3002 return -EINVAL;
3029 3003
3030 k = 100000000 / freq_out - 2; 3004 return rl6231_pll_calc(freq_in, freq_out, pll_code);
3031 if (k > RT5677_PLL_K_MAX)
3032 k = RT5677_PLL_K_MAX;
3033 for (n_t = 0; n_t <= max_n; n_t++) {
3034 in_t = freq_in / (k + 2);
3035 pll_out = freq_out / (n_t + 2);
3036 if (in_t < 0)
3037 continue;
3038 if (in_t == pll_out) {
3039 m_bp = true;
3040 n = n_t;
3041 goto code_find;
3042 }
3043 red = abs(in_t - pll_out);
3044 if (red < red_t) {
3045 m_bp = true;
3046 n = n_t;
3047 m = m_t;
3048 if (red == 0)
3049 goto code_find;
3050 red_t = red;
3051 }
3052 for (m_t = 0; m_t <= max_m; m_t++) {
3053 out_t = in_t / (m_t + 2);
3054 red = abs(out_t - pll_out);
3055 if (red < red_t) {
3056 m_bp = false;
3057 n = n_t;
3058 m = m_t;
3059 if (red == 0)
3060 goto code_find;
3061 red_t = red;
3062 }
3063 }
3064 }
3065 pr_debug("Only get approximation about PLL\n");
3066
3067code_find:
3068
3069 pll_code->m_bp = m_bp;
3070 pll_code->k_bp = k_bp;
3071 pll_code->m_code = m;
3072 pll_code->n_code = n;
3073 pll_code->k_code = k;
3074 return 0;
3075} 3005}
3076 3006
3077static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 3007static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
@@ -3079,7 +3009,7 @@ static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3079{ 3009{
3080 struct snd_soc_codec *codec = dai->codec; 3010 struct snd_soc_codec *codec = dai->codec;
3081 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 3011 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3082 struct rt5677_pll_code pll_code; 3012 struct rl6231_pll_code pll_code;
3083 int ret; 3013 int ret;
3084 3014
3085 if (source == rt5677->pll_src && freq_in == rt5677->pll_in && 3015 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
@@ -3137,15 +3067,12 @@ static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3137 return ret; 3067 return ret;
3138 } 3068 }
3139 3069
3140 dev_dbg(codec->dev, "m_bypass=%d k_bypass=%d m=%d n=%d k=%d\n", 3070 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
3141 pll_code.m_bp, pll_code.k_bp, 3071 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
3142 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code, 3072 pll_code.n_code, pll_code.k_code);
3143 (pll_code.k_bp ? 0 : pll_code.k_code));
3144 3073
3145 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, 3074 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
3146 pll_code.n_code << RT5677_PLL_N_SFT | 3075 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
3147 pll_code.k_bp << RT5677_PLL_K_BP_SFT |
3148 (pll_code.k_bp ? 0 : pll_code.k_code));
3149 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, 3076 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
3150 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT | 3077 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
3151 pll_code.m_bp << RT5677_PLL_M_BP_SFT); 3078 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
@@ -3197,7 +3124,7 @@ static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3197 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); 3124 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
3198 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); 3125 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
3199 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000); 3126 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
3200 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0000); 3127 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
3201 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000); 3128 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
3202 regmap_update_bits(rt5677->regmap, 3129 regmap_update_bits(rt5677->regmap,
3203 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000); 3130 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
@@ -3454,14 +3381,8 @@ static int rt5677_i2c_probe(struct i2c_client *i2c,
3454 regmap_update_bits(rt5677->regmap, RT5677_IN1, 3381 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3455 RT5677_IN_DF2, RT5677_IN_DF2); 3382 RT5677_IN_DF2, RT5677_IN_DF2);
3456 3383
3457 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677, 3384 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
3458 rt5677_dai, ARRAY_SIZE(rt5677_dai)); 3385 rt5677_dai, ARRAY_SIZE(rt5677_dai));
3459 if (ret < 0)
3460 goto err;
3461
3462 return 0;
3463err:
3464 return ret;
3465} 3386}
3466 3387
3467static int rt5677_i2c_remove(struct i2c_client *i2c) 3388static int rt5677_i2c_remove(struct i2c_client *i2c)
@@ -3480,18 +3401,7 @@ static struct i2c_driver rt5677_i2c_driver = {
3480 .remove = rt5677_i2c_remove, 3401 .remove = rt5677_i2c_remove,
3481 .id_table = rt5677_i2c_id, 3402 .id_table = rt5677_i2c_id,
3482}; 3403};
3483 3404module_i2c_driver(rt5677_i2c_driver);
3484static int __init rt5677_modinit(void)
3485{
3486 return i2c_add_driver(&rt5677_i2c_driver);
3487}
3488module_init(rt5677_modinit);
3489
3490static void __exit rt5677_modexit(void)
3491{
3492 i2c_del_driver(&rt5677_i2c_driver);
3493}
3494module_exit(rt5677_modexit);
3495 3405
3496MODULE_DESCRIPTION("ASoC RT5677 driver"); 3406MODULE_DESCRIPTION("ASoC RT5677 driver");
3497MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); 3407MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
diff --git a/sound/soc/codecs/rt5677.h b/sound/soc/codecs/rt5677.h
index af4e9c797408..863393e62096 100644
--- a/sound/soc/codecs/rt5677.h
+++ b/sound/soc/codecs/rt5677.h
@@ -1393,13 +1393,6 @@
1393#define RT5677_DSP_IB_9_L (0x1 << 1) 1393#define RT5677_DSP_IB_9_L (0x1 << 1)
1394#define RT5677_DSP_IB_9_L_SFT 1 1394#define RT5677_DSP_IB_9_L_SFT 1
1395 1395
1396/* Debug String Length */
1397#define RT5677_REG_DISP_LEN 23
1398
1399#define RT5677_NO_JACK BIT(0)
1400#define RT5677_HEADSET_DET BIT(1)
1401#define RT5677_HEADPHO_DET BIT(2)
1402
1403/* System Clock Source */ 1396/* System Clock Source */
1404enum { 1397enum {
1405 RT5677_SCLK_S_MCLK, 1398 RT5677_SCLK_S_MCLK,
@@ -1425,14 +1418,6 @@ enum {
1425 RT5677_AIFS, 1418 RT5677_AIFS,
1426}; 1419};
1427 1420
1428struct rt5677_pll_code {
1429 bool m_bp; /* Indicates bypass m code or not. */
1430 bool k_bp; /* Indicates bypass k code or not. */
1431 int m_code;
1432 int n_code;
1433 int k_code;
1434};
1435
1436struct rt5677_priv { 1421struct rt5677_priv {
1437 struct snd_soc_codec *codec; 1422 struct snd_soc_codec *codec;
1438 struct rt5677_platform_data pdata; 1423 struct rt5677_platform_data pdata;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 06:06:13 -0500