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-rw-r--r--sound/soc/codecs/ak4642.c33
-rw-r--r--sound/soc/codecs/arizona.c247
-rw-r--r--sound/soc/codecs/arizona.h8
-rw-r--r--sound/soc/codecs/cs4271.c34
-rw-r--r--sound/soc/codecs/cs42l52.c4
-rwxr-xr-x[-rw-r--r--]sound/soc/codecs/max98090.c2685
-rwxr-xr-xsound/soc/codecs/max98090.h1549
-rw-r--r--sound/soc/codecs/tlv320aic3x.c87
-rw-r--r--sound/soc/codecs/tlv320aic3x.h4
-rw-r--r--sound/soc/codecs/tlv320dac33.c16
-rw-r--r--sound/soc/codecs/twl4030.c85
-rw-r--r--sound/soc/codecs/twl6040.c62
-rw-r--r--sound/soc/codecs/wm2000.c66
-rw-r--r--sound/soc/codecs/wm2000.h3
-rw-r--r--sound/soc/codecs/wm2200.c62
-rw-r--r--sound/soc/codecs/wm5100.c13
-rw-r--r--sound/soc/codecs/wm5102.c172
-rw-r--r--sound/soc/codecs/wm5110.c111
-rw-r--r--sound/soc/codecs/wm8350.c10
-rw-r--r--sound/soc/codecs/wm8804.c3
-rw-r--r--sound/soc/codecs/wm8962.c37
-rw-r--r--sound/soc/codecs/wm8983.c41
-rw-r--r--sound/soc/codecs/wm8985.c43
-rw-r--r--sound/soc/codecs/wm_adsp.c525
-rw-r--r--sound/soc/codecs/wm_adsp.h18
-rw-r--r--sound/soc/codecs/wmfw.h15
26 files changed, 5152 insertions, 781 deletions
diff --git a/sound/soc/codecs/ak4642.c b/sound/soc/codecs/ak4642.c
index 1f0cdab03294..2d0378709702 100644
--- a/sound/soc/codecs/ak4642.c
+++ b/sound/soc/codecs/ak4642.c
@@ -26,6 +26,7 @@
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/i2c.h> 27#include <linux/i2c.h>
28#include <linux/slab.h> 28#include <linux/slab.h>
29#include <linux/of_device.h>
29#include <linux/module.h> 30#include <linux/module.h>
30#include <sound/soc.h> 31#include <sound/soc.h>
31#include <sound/initval.h> 32#include <sound/initval.h>
@@ -513,12 +514,31 @@ static struct snd_soc_codec_driver soc_codec_dev_ak4648 = {
513}; 514};
514 515
515#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 516#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
517static struct of_device_id ak4642_of_match[];
516static int ak4642_i2c_probe(struct i2c_client *i2c, 518static int ak4642_i2c_probe(struct i2c_client *i2c,
517 const struct i2c_device_id *id) 519 const struct i2c_device_id *id)
518{ 520{
521 struct device_node *np = i2c->dev.of_node;
522 const struct snd_soc_codec_driver *driver;
523
524 driver = NULL;
525 if (np) {
526 const struct of_device_id *of_id;
527
528 of_id = of_match_device(ak4642_of_match, &i2c->dev);
529 if (of_id)
530 driver = of_id->data;
531 } else {
532 driver = (struct snd_soc_codec_driver *)id->driver_data;
533 }
534
535 if (!driver) {
536 dev_err(&i2c->dev, "no driver\n");
537 return -EINVAL;
538 }
539
519 return snd_soc_register_codec(&i2c->dev, 540 return snd_soc_register_codec(&i2c->dev,
520 (struct snd_soc_codec_driver *)id->driver_data, 541 driver, &ak4642_dai, 1);
521 &ak4642_dai, 1);
522} 542}
523 543
524static int ak4642_i2c_remove(struct i2c_client *client) 544static int ak4642_i2c_remove(struct i2c_client *client)
@@ -527,6 +547,14 @@ static int ak4642_i2c_remove(struct i2c_client *client)
527 return 0; 547 return 0;
528} 548}
529 549
550static struct of_device_id ak4642_of_match[] = {
551 { .compatible = "asahi-kasei,ak4642", .data = &soc_codec_dev_ak4642},
552 { .compatible = "asahi-kasei,ak4643", .data = &soc_codec_dev_ak4642},
553 { .compatible = "asahi-kasei,ak4648", .data = &soc_codec_dev_ak4648},
554 {},
555};
556MODULE_DEVICE_TABLE(of, ak4642_of_match);
557
530static const struct i2c_device_id ak4642_i2c_id[] = { 558static const struct i2c_device_id ak4642_i2c_id[] = {
531 { "ak4642", (kernel_ulong_t)&soc_codec_dev_ak4642 }, 559 { "ak4642", (kernel_ulong_t)&soc_codec_dev_ak4642 },
532 { "ak4643", (kernel_ulong_t)&soc_codec_dev_ak4642 }, 560 { "ak4643", (kernel_ulong_t)&soc_codec_dev_ak4642 },
@@ -539,6 +567,7 @@ static struct i2c_driver ak4642_i2c_driver = {
539 .driver = { 567 .driver = {
540 .name = "ak4642-codec", 568 .name = "ak4642-codec",
541 .owner = THIS_MODULE, 569 .owner = THIS_MODULE,
570 .of_match_table = ak4642_of_match,
542 }, 571 },
543 .probe = ak4642_i2c_probe, 572 .probe = ak4642_i2c_probe,
544 .remove = ak4642_i2c_remove, 573 .remove = ak4642_i2c_remove,
diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c
index ef62c435848e..d824c984c8a4 100644
--- a/sound/soc/codecs/arizona.c
+++ b/sound/soc/codecs/arizona.c
@@ -56,14 +56,14 @@
56#define arizona_fll_warn(_fll, fmt, ...) \ 56#define arizona_fll_warn(_fll, fmt, ...) \
57 dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) 57 dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
58#define arizona_fll_dbg(_fll, fmt, ...) \ 58#define arizona_fll_dbg(_fll, fmt, ...) \
59 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__) 59 dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
60 60
61#define arizona_aif_err(_dai, fmt, ...) \ 61#define arizona_aif_err(_dai, fmt, ...) \
62 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__) 62 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
63#define arizona_aif_warn(_dai, fmt, ...) \ 63#define arizona_aif_warn(_dai, fmt, ...) \
64 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__) 64 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
65#define arizona_aif_dbg(_dai, fmt, ...) \ 65#define arizona_aif_dbg(_dai, fmt, ...) \
66 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__) 66 dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
67 67
68const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = { 68const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = {
69 "None", 69 "None",
@@ -141,6 +141,30 @@ const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = {
141 "ASRC1R", 141 "ASRC1R",
142 "ASRC2L", 142 "ASRC2L",
143 "ASRC2R", 143 "ASRC2R",
144 "ISRC1INT1",
145 "ISRC1INT2",
146 "ISRC1INT3",
147 "ISRC1INT4",
148 "ISRC1DEC1",
149 "ISRC1DEC2",
150 "ISRC1DEC3",
151 "ISRC1DEC4",
152 "ISRC2INT1",
153 "ISRC2INT2",
154 "ISRC2INT3",
155 "ISRC2INT4",
156 "ISRC2DEC1",
157 "ISRC2DEC2",
158 "ISRC2DEC3",
159 "ISRC2DEC4",
160 "ISRC3INT1",
161 "ISRC3INT2",
162 "ISRC3INT3",
163 "ISRC3INT4",
164 "ISRC3DEC1",
165 "ISRC3DEC2",
166 "ISRC3DEC3",
167 "ISRC3DEC4",
144}; 168};
145EXPORT_SYMBOL_GPL(arizona_mixer_texts); 169EXPORT_SYMBOL_GPL(arizona_mixer_texts);
146 170
@@ -220,6 +244,30 @@ int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = {
220 0x91, 244 0x91,
221 0x92, 245 0x92,
222 0x93, 246 0x93,
247 0xa0, /* ISRC1INT1 */
248 0xa1,
249 0xa2,
250 0xa3,
251 0xa4, /* ISRC1DEC1 */
252 0xa5,
253 0xa6,
254 0xa7,
255 0xa8, /* ISRC2DEC1 */
256 0xa9,
257 0xaa,
258 0xab,
259 0xac, /* ISRC2INT1 */
260 0xad,
261 0xae,
262 0xaf,
263 0xb0, /* ISRC3DEC1 */
264 0xb1,
265 0xb2,
266 0xb3,
267 0xb4, /* ISRC3INT1 */
268 0xb5,
269 0xb6,
270 0xb7,
223}; 271};
224EXPORT_SYMBOL_GPL(arizona_mixer_values); 272EXPORT_SYMBOL_GPL(arizona_mixer_values);
225 273
@@ -275,6 +323,15 @@ const struct soc_enum arizona_lhpf4_mode =
275 arizona_lhpf_mode_text); 323 arizona_lhpf_mode_text);
276EXPORT_SYMBOL_GPL(arizona_lhpf4_mode); 324EXPORT_SYMBOL_GPL(arizona_lhpf4_mode);
277 325
326static const char *arizona_ng_hold_text[] = {
327 "30ms", "120ms", "250ms", "500ms",
328};
329
330const struct soc_enum arizona_ng_hold =
331 SOC_ENUM_SINGLE(ARIZONA_NOISE_GATE_CONTROL, ARIZONA_NGATE_HOLD_SHIFT,
332 4, arizona_ng_hold_text);
333EXPORT_SYMBOL_GPL(arizona_ng_hold);
334
278int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, 335int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
279 int event) 336 int event)
280{ 337{
@@ -417,6 +474,10 @@ int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
417 case 147456000: 474 case 147456000:
418 val |= 6 << ARIZONA_SYSCLK_FREQ_SHIFT; 475 val |= 6 << ARIZONA_SYSCLK_FREQ_SHIFT;
419 break; 476 break;
477 case 0:
478 dev_dbg(arizona->dev, "%s cleared\n", name);
479 *clk = freq;
480 return 0;
420 default: 481 default:
421 return -EINVAL; 482 return -EINVAL;
422 } 483 }
@@ -635,6 +696,9 @@ static int arizona_startup(struct snd_pcm_substream *substream,
635 return 0; 696 return 0;
636 } 697 }
637 698
699 if (base_rate == 0)
700 return 0;
701
638 if (base_rate % 8000) 702 if (base_rate % 8000)
639 constraint = &arizona_44k1_constraint; 703 constraint = &arizona_44k1_constraint;
640 else 704 else
@@ -645,25 +709,81 @@ static int arizona_startup(struct snd_pcm_substream *substream,
645 constraint); 709 constraint);
646} 710}
647 711
712static int arizona_hw_params_rate(struct snd_pcm_substream *substream,
713 struct snd_pcm_hw_params *params,
714 struct snd_soc_dai *dai)
715{
716 struct snd_soc_codec *codec = dai->codec;
717 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
718 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
719 int base = dai->driver->base;
720 int i, sr_val;
721
722 /*
723 * We will need to be more flexible than this in future,
724 * currently we use a single sample rate for SYSCLK.
725 */
726 for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
727 if (arizona_sr_vals[i] == params_rate(params))
728 break;
729 if (i == ARRAY_SIZE(arizona_sr_vals)) {
730 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
731 params_rate(params));
732 return -EINVAL;
733 }
734 sr_val = i;
735
736 switch (dai_priv->clk) {
737 case ARIZONA_CLK_SYSCLK:
738 snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1,
739 ARIZONA_SAMPLE_RATE_1_MASK, sr_val);
740 if (base)
741 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
742 ARIZONA_AIF1_RATE_MASK, 0);
743 break;
744 case ARIZONA_CLK_ASYNCCLK:
745 snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
746 ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val);
747 if (base)
748 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
749 ARIZONA_AIF1_RATE_MASK,
750 8 << ARIZONA_AIF1_RATE_SHIFT);
751 break;
752 default:
753 arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
754 return -EINVAL;
755 }
756
757 return 0;
758}
759
648static int arizona_hw_params(struct snd_pcm_substream *substream, 760static int arizona_hw_params(struct snd_pcm_substream *substream,
649 struct snd_pcm_hw_params *params, 761 struct snd_pcm_hw_params *params,
650 struct snd_soc_dai *dai) 762 struct snd_soc_dai *dai)
651{ 763{
652 struct snd_soc_codec *codec = dai->codec; 764 struct snd_soc_codec *codec = dai->codec;
653 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec); 765 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
654 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1]; 766 struct arizona *arizona = priv->arizona;
655 int base = dai->driver->base; 767 int base = dai->driver->base;
656 const int *rates; 768 const int *rates;
657 int i; 769 int i, ret;
658 int bclk, lrclk, wl, frame, sr_val; 770 int chan_limit = arizona->pdata.max_channels_clocked[dai->id - 1];
771 int bclk, lrclk, wl, frame, bclk_target;
659 772
660 if (params_rate(params) % 8000) 773 if (params_rate(params) % 8000)
661 rates = &arizona_44k1_bclk_rates[0]; 774 rates = &arizona_44k1_bclk_rates[0];
662 else 775 else
663 rates = &arizona_48k_bclk_rates[0]; 776 rates = &arizona_48k_bclk_rates[0];
664 777
778 bclk_target = snd_soc_params_to_bclk(params);
779 if (chan_limit && chan_limit < params_channels(params)) {
780 arizona_aif_dbg(dai, "Limiting to %d channels\n", chan_limit);
781 bclk_target /= params_channels(params);
782 bclk_target *= chan_limit;
783 }
784
665 for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) { 785 for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) {
666 if (rates[i] >= snd_soc_params_to_bclk(params) && 786 if (rates[i] >= bclk_target &&
667 rates[i] % params_rate(params) == 0) { 787 rates[i] % params_rate(params) == 0) {
668 bclk = i; 788 bclk = i;
669 break; 789 break;
@@ -675,16 +795,6 @@ static int arizona_hw_params(struct snd_pcm_substream *substream,
675 return -EINVAL; 795 return -EINVAL;
676 } 796 }
677 797
678 for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
679 if (arizona_sr_vals[i] == params_rate(params))
680 break;
681 if (i == ARRAY_SIZE(arizona_sr_vals)) {
682 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
683 params_rate(params));
684 return -EINVAL;
685 }
686 sr_val = i;
687
688 lrclk = rates[bclk] / params_rate(params); 798 lrclk = rates[bclk] / params_rate(params);
689 799
690 arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n", 800 arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
@@ -693,28 +803,9 @@ static int arizona_hw_params(struct snd_pcm_substream *substream,
693 wl = snd_pcm_format_width(params_format(params)); 803 wl = snd_pcm_format_width(params_format(params));
694 frame = wl << ARIZONA_AIF1TX_WL_SHIFT | wl; 804 frame = wl << ARIZONA_AIF1TX_WL_SHIFT | wl;
695 805
696 /* 806 ret = arizona_hw_params_rate(substream, params, dai);
697 * We will need to be more flexible than this in future, 807 if (ret != 0)
698 * currently we use a single sample rate for SYSCLK. 808 return ret;
699 */
700 switch (dai_priv->clk) {
701 case ARIZONA_CLK_SYSCLK:
702 snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1,
703 ARIZONA_SAMPLE_RATE_1_MASK, sr_val);
704 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
705 ARIZONA_AIF1_RATE_MASK, 0);
706 break;
707 case ARIZONA_CLK_ASYNCCLK:
708 snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
709 ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val);
710 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
711 ARIZONA_AIF1_RATE_MASK,
712 8 << ARIZONA_AIF1_RATE_SHIFT);
713 break;
714 default:
715 arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
716 return -EINVAL;
717 }
718 809
719 snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL, 810 snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL,
720 ARIZONA_AIF1_BCLK_FREQ_MASK, bclk); 811 ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
@@ -789,11 +880,27 @@ static int arizona_dai_set_sysclk(struct snd_soc_dai *dai,
789 return snd_soc_dapm_sync(&codec->dapm); 880 return snd_soc_dapm_sync(&codec->dapm);
790} 881}
791 882
883static int arizona_set_tristate(struct snd_soc_dai *dai, int tristate)
884{
885 struct snd_soc_codec *codec = dai->codec;
886 int base = dai->driver->base;
887 unsigned int reg;
888
889 if (tristate)
890 reg = ARIZONA_AIF1_TRI;
891 else
892 reg = 0;
893
894 return snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
895 ARIZONA_AIF1_TRI, reg);
896}
897
792const struct snd_soc_dai_ops arizona_dai_ops = { 898const struct snd_soc_dai_ops arizona_dai_ops = {
793 .startup = arizona_startup, 899 .startup = arizona_startup,
794 .set_fmt = arizona_set_fmt, 900 .set_fmt = arizona_set_fmt,
795 .hw_params = arizona_hw_params, 901 .hw_params = arizona_hw_params,
796 .set_sysclk = arizona_dai_set_sysclk, 902 .set_sysclk = arizona_dai_set_sysclk,
903 .set_tristate = arizona_set_tristate,
797}; 904};
798EXPORT_SYMBOL_GPL(arizona_dai_ops); 905EXPORT_SYMBOL_GPL(arizona_dai_ops);
799 906
@@ -807,17 +914,6 @@ int arizona_init_dai(struct arizona_priv *priv, int id)
807} 914}
808EXPORT_SYMBOL_GPL(arizona_init_dai); 915EXPORT_SYMBOL_GPL(arizona_init_dai);
809 916
810static irqreturn_t arizona_fll_lock(int irq, void *data)
811{
812 struct arizona_fll *fll = data;
813
814 arizona_fll_dbg(fll, "Lock status changed\n");
815
816 complete(&fll->lock);
817
818 return IRQ_HANDLED;
819}
820
821static irqreturn_t arizona_fll_clock_ok(int irq, void *data) 917static irqreturn_t arizona_fll_clock_ok(int irq, void *data)
822{ 918{
823 struct arizona_fll *fll = data; 919 struct arizona_fll *fll = data;
@@ -910,7 +1006,7 @@ static int arizona_calc_fll(struct arizona_fll *fll,
910 1006
911 cfg->n = target / (ratio * Fref); 1007 cfg->n = target / (ratio * Fref);
912 1008
913 if (target % Fref) { 1009 if (target % (ratio * Fref)) {
914 gcd_fll = gcd(target, ratio * Fref); 1010 gcd_fll = gcd(target, ratio * Fref);
915 arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll); 1011 arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll);
916 1012
@@ -922,6 +1018,15 @@ static int arizona_calc_fll(struct arizona_fll *fll,
922 cfg->lambda = 0; 1018 cfg->lambda = 0;
923 } 1019 }
924 1020
1021 /* Round down to 16bit range with cost of accuracy lost.
1022 * Denominator must be bigger than numerator so we only
1023 * take care of it.
1024 */
1025 while (cfg->lambda >= (1 << 16)) {
1026 cfg->theta >>= 1;
1027 cfg->lambda >>= 1;
1028 }
1029
925 arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n", 1030 arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n",
926 cfg->n, cfg->theta, cfg->lambda); 1031 cfg->n, cfg->theta, cfg->lambda);
927 arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n", 1032 arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
@@ -1057,7 +1162,6 @@ int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
1057{ 1162{
1058 int ret; 1163 int ret;
1059 1164
1060 init_completion(&fll->lock);
1061 init_completion(&fll->ok); 1165 init_completion(&fll->ok);
1062 1166
1063 fll->id = id; 1167 fll->id = id;
@@ -1068,13 +1172,6 @@ int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
1068 snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name), 1172 snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name),
1069 "FLL%d clock OK", id); 1173 "FLL%d clock OK", id);
1070 1174
1071 ret = arizona_request_irq(arizona, lock_irq, fll->lock_name,
1072 arizona_fll_lock, fll);
1073 if (ret != 0) {
1074 dev_err(arizona->dev, "Failed to get FLL%d lock IRQ: %d\n",
1075 id, ret);
1076 }
1077
1078 ret = arizona_request_irq(arizona, ok_irq, fll->clock_ok_name, 1175 ret = arizona_request_irq(arizona, ok_irq, fll->clock_ok_name,
1079 arizona_fll_clock_ok, fll); 1176 arizona_fll_clock_ok, fll);
1080 if (ret != 0) { 1177 if (ret != 0) {
@@ -1089,6 +1186,40 @@ int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
1089} 1186}
1090EXPORT_SYMBOL_GPL(arizona_init_fll); 1187EXPORT_SYMBOL_GPL(arizona_init_fll);
1091 1188
1189/**
1190 * arizona_set_output_mode - Set the mode of the specified output
1191 *
1192 * @codec: Device to configure
1193 * @output: Output number
1194 * @diff: True to set the output to differential mode
1195 *
1196 * Some systems use external analogue switches to connect more
1197 * analogue devices to the CODEC than are supported by the device. In
1198 * some systems this requires changing the switched output from single
1199 * ended to differential mode dynamically at runtime, an operation
1200 * supported using this function.
1201 *
1202 * Most systems have a single static configuration and should use
1203 * platform data instead.
1204 */
1205int arizona_set_output_mode(struct snd_soc_codec *codec, int output, bool diff)
1206{
1207 unsigned int reg, val;
1208
1209 if (output < 1 || output > 6)
1210 return -EINVAL;
1211
1212 reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8;
1213
1214 if (diff)
1215 val = ARIZONA_OUT1_MONO;
1216 else
1217 val = 0;
1218
1219 return snd_soc_update_bits(codec, reg, ARIZONA_OUT1_MONO, val);
1220}
1221EXPORT_SYMBOL_GPL(arizona_set_output_mode);
1222
1092MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support"); 1223MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
1093MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 1224MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1094MODULE_LICENSE("GPL"); 1225MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/arizona.h b/sound/soc/codecs/arizona.h
index 4deebeb07177..116372c91f5d 100644
--- a/sound/soc/codecs/arizona.h
+++ b/sound/soc/codecs/arizona.h
@@ -66,7 +66,7 @@ struct arizona_priv {
66 struct arizona_dai_priv dai[ARIZONA_MAX_DAI]; 66 struct arizona_dai_priv dai[ARIZONA_MAX_DAI];
67}; 67};
68 68
69#define ARIZONA_NUM_MIXER_INPUTS 75 69#define ARIZONA_NUM_MIXER_INPUTS 99
70 70
71extern const unsigned int arizona_mixer_tlv[]; 71extern const unsigned int arizona_mixer_tlv[];
72extern const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS]; 72extern const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS];
@@ -176,6 +176,8 @@ extern const struct soc_enum arizona_lhpf2_mode;
176extern const struct soc_enum arizona_lhpf3_mode; 176extern const struct soc_enum arizona_lhpf3_mode;
177extern const struct soc_enum arizona_lhpf4_mode; 177extern const struct soc_enum arizona_lhpf4_mode;
178 178
179extern const struct soc_enum arizona_ng_hold;
180
179extern int arizona_in_ev(struct snd_soc_dapm_widget *w, 181extern int arizona_in_ev(struct snd_soc_dapm_widget *w,
180 struct snd_kcontrol *kcontrol, 182 struct snd_kcontrol *kcontrol,
181 int event); 183 int event);
@@ -195,7 +197,6 @@ struct arizona_fll {
195 int id; 197 int id;
196 unsigned int base; 198 unsigned int base;
197 unsigned int vco_mult; 199 unsigned int vco_mult;
198 struct completion lock;
199 struct completion ok; 200 struct completion ok;
200 unsigned int fref; 201 unsigned int fref;
201 unsigned int fout; 202 unsigned int fout;
@@ -211,4 +212,7 @@ extern int arizona_set_fll(struct arizona_fll *fll, int source,
211 212
212extern int arizona_init_dai(struct arizona_priv *priv, int dai); 213extern int arizona_init_dai(struct arizona_priv *priv, int dai);
213 214
215int arizona_set_output_mode(struct snd_soc_codec *codec, int output,
216 bool diff);
217
214#endif 218#endif
diff --git a/sound/soc/codecs/cs4271.c b/sound/soc/codecs/cs4271.c
index ac8742a1f25a..2415a4118dbd 100644
--- a/sound/soc/codecs/cs4271.c
+++ b/sound/soc/codecs/cs4271.c
@@ -167,6 +167,8 @@ struct cs4271_private {
167 int gpio_nreset; 167 int gpio_nreset;
168 /* GPIO that disable serial bus, if any */ 168 /* GPIO that disable serial bus, if any */
169 int gpio_disable; 169 int gpio_disable;
170 /* enable soft reset workaround */
171 bool enable_soft_reset;
170}; 172};
171 173
172/* 174/*
@@ -325,6 +327,33 @@ static int cs4271_hw_params(struct snd_pcm_substream *substream,
325 int i, ret; 327 int i, ret;
326 unsigned int ratio, val; 328 unsigned int ratio, val;
327 329
330 if (cs4271->enable_soft_reset) {
331 /*
332 * Put the codec in soft reset and back again in case it's not
333 * currently streaming data. This way of bringing the codec in
334 * sync to the current clocks is not explicitly documented in
335 * the data sheet, but it seems to work fine, and in contrast
336 * to a read hardware reset, we don't have to sync back all
337 * registers every time.
338 */
339
340 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
341 !dai->capture_active) ||
342 (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
343 !dai->playback_active)) {
344 ret = snd_soc_update_bits(codec, CS4271_MODE2,
345 CS4271_MODE2_PDN,
346 CS4271_MODE2_PDN);
347 if (ret < 0)
348 return ret;
349
350 ret = snd_soc_update_bits(codec, CS4271_MODE2,
351 CS4271_MODE2_PDN, 0);
352 if (ret < 0)
353 return ret;
354 }
355 }
356
328 cs4271->rate = params_rate(params); 357 cs4271->rate = params_rate(params);
329 358
330 /* Configure DAC */ 359 /* Configure DAC */
@@ -484,6 +513,10 @@ static int cs4271_probe(struct snd_soc_codec *codec)
484 if (of_get_property(codec->dev->of_node, 513 if (of_get_property(codec->dev->of_node,
485 "cirrus,amutec-eq-bmutec", NULL)) 514 "cirrus,amutec-eq-bmutec", NULL))
486 amutec_eq_bmutec = true; 515 amutec_eq_bmutec = true;
516
517 if (of_get_property(codec->dev->of_node,
518 "cirrus,enable-soft-reset", NULL))
519 cs4271->enable_soft_reset = true;
487 } 520 }
488#endif 521#endif
489 522
@@ -492,6 +525,7 @@ static int cs4271_probe(struct snd_soc_codec *codec)
492 gpio_nreset = cs4271plat->gpio_nreset; 525 gpio_nreset = cs4271plat->gpio_nreset;
493 526
494 amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec; 527 amutec_eq_bmutec = cs4271plat->amutec_eq_bmutec;
528 cs4271->enable_soft_reset = cs4271plat->enable_soft_reset;
495 } 529 }
496 530
497 if (gpio_nreset >= 0) 531 if (gpio_nreset >= 0)
diff --git a/sound/soc/codecs/cs42l52.c b/sound/soc/codecs/cs42l52.c
index 9811a5478c87..0f6f481cec09 100644
--- a/sound/soc/codecs/cs42l52.c
+++ b/sound/soc/codecs/cs42l52.c
@@ -1038,7 +1038,7 @@ static void cs42l52_init_beep(struct snd_soc_codec *codec)
1038 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec); 1038 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1039 int ret; 1039 int ret;
1040 1040
1041 cs42l52->beep = input_allocate_device(); 1041 cs42l52->beep = devm_input_allocate_device(codec->dev);
1042 if (!cs42l52->beep) { 1042 if (!cs42l52->beep) {
1043 dev_err(codec->dev, "Failed to allocate beep device\n"); 1043 dev_err(codec->dev, "Failed to allocate beep device\n");
1044 return; 1044 return;
@@ -1059,7 +1059,6 @@ static void cs42l52_init_beep(struct snd_soc_codec *codec)
1059 1059
1060 ret = input_register_device(cs42l52->beep); 1060 ret = input_register_device(cs42l52->beep);
1061 if (ret != 0) { 1061 if (ret != 0) {
1062 input_free_device(cs42l52->beep);
1063 cs42l52->beep = NULL; 1062 cs42l52->beep = NULL;
1064 dev_err(codec->dev, "Failed to register beep device\n"); 1063 dev_err(codec->dev, "Failed to register beep device\n");
1065 } 1064 }
@@ -1076,7 +1075,6 @@ static void cs42l52_free_beep(struct snd_soc_codec *codec)
1076 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec); 1075 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1077 1076
1078 device_remove_file(codec->dev, &dev_attr_beep); 1077 device_remove_file(codec->dev, &dev_attr_beep);
1079 input_unregister_device(cs42l52->beep);
1080 cancel_work_sync(&cs42l52->beep_work); 1078 cancel_work_sync(&cs42l52->beep_work);
1081 cs42l52->beep = NULL; 1079 cs42l52->beep = NULL;
1082 1080
diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c
index c9772ca3da4f..fc176044994d 100644..100755
--- a/sound/soc/codecs/max98090.c
+++ b/sound/soc/codecs/max98090.c
@@ -1,562 +1,2381 @@
1/* 1/*
2 * max98090.c -- MAX98090 ALSA SoC Audio driver 2 * max98090.c -- MAX98090 ALSA SoC Audio driver
3 * based on Rev0p8 datasheet
4 * 3 *
5 * Copyright (C) 2012 Renesas Solutions Corp. 4 * Copyright 2011-2012 Maxim Integrated Products
6 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 *
8 * Based on
9 *
10 * max98095.c
11 * Copyright 2011 Maxim Integrated Products
12 *
13 * https://github.com/hardkernel/linux/commit/\
14 * 3417d7166b17113b3b33b0a337c74d1c7cc313df#sound/soc/codecs/max98090.c
15 * Copyright 2011 Maxim Integrated Products
16 * 5 *
17 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
20 */ 9 */
21 10
11#include <linux/delay.h>
22#include <linux/i2c.h> 12#include <linux/i2c.h>
23#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/pm.h>
15#include <linux/pm_runtime.h>
24#include <linux/regmap.h> 16#include <linux/regmap.h>
17#include <linux/slab.h>
18#include <sound/jack.h>
19#include <sound/pcm.h>
20#include <sound/pcm_params.h>
25#include <sound/soc.h> 21#include <sound/soc.h>
26#include <sound/tlv.h> 22#include <sound/tlv.h>
23#include <sound/max98090.h>
24#include "max98090.h"
25
26#include <linux/version.h>
27
28#define DEBUG
29#define EXTMIC_METHOD
30#define EXTMIC_METHOD_TEST
31
32/* Allows for sparsely populated register maps */
33static struct reg_default max98090_reg[] = {
34 { 0x00, 0x00 }, /* 00 Software Reset */
35 { 0x03, 0x04 }, /* 03 Interrupt Masks */
36 { 0x04, 0x00 }, /* 04 System Clock Quick */
37 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
38 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
39 { 0x07, 0x00 }, /* 07 DAC Path Quick */
40 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
41 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
42 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
43 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
44 { 0x0C, 0x00 }, /* 0C Reserved */
45 { 0x0D, 0x00 }, /* 0D Input Config */
46 { 0x0E, 0x1B }, /* 0E Line Input Level */
47 { 0x0F, 0x00 }, /* 0F Line Config */
48
49 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
50 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
51 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
52 { 0x13, 0x00 }, /* 13 Digital Mic Config */
53 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
54 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
55 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
56 { 0x17, 0x03 }, /* 17 Left ADC Level */
57 { 0x18, 0x03 }, /* 18 Right ADC Level */
58 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
59 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
60 { 0x1B, 0x00 }, /* 1B System Clock */
61 { 0x1C, 0x00 }, /* 1C Clock Mode */
62 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
63 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
64 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
65
66 { 0x20, 0x00 }, /* 20 Any Clock 4 */
67 { 0x21, 0x00 }, /* 21 Master Mode */
68 { 0x22, 0x00 }, /* 22 Interface Format */
69 { 0x23, 0x00 }, /* 23 TDM Format 1*/
70 { 0x24, 0x00 }, /* 24 TDM Format 2*/
71 { 0x25, 0x00 }, /* 25 I/O Configuration */
72 { 0x26, 0x80 }, /* 26 Filter Config */
73 { 0x27, 0x00 }, /* 27 DAI Playback Level */
74 { 0x28, 0x00 }, /* 28 EQ Playback Level */
75 { 0x29, 0x00 }, /* 29 Left HP Mixer */
76 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
77 { 0x2B, 0x00 }, /* 2B HP Control */
78 { 0x2C, 0x1A }, /* 2C Left HP Volume */
79 { 0x2D, 0x1A }, /* 2D Right HP Volume */
80 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
81 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
82
83 { 0x30, 0x00 }, /* 30 Spk Control */
84 { 0x31, 0x2C }, /* 31 Left Spk Volume */
85 { 0x32, 0x2C }, /* 32 Right Spk Volume */
86 { 0x33, 0x00 }, /* 33 ALC Timing */
87 { 0x34, 0x00 }, /* 34 ALC Compressor */
88 { 0x35, 0x00 }, /* 35 ALC Expander */
89 { 0x36, 0x00 }, /* 36 ALC Gain */
90 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
91 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
92 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
93 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
94 { 0x3B, 0x00 }, /* 3B Line OutR Control */
95 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
96 { 0x3D, 0x00 }, /* 3D Jack Detect */
97 { 0x3E, 0x00 }, /* 3E Input Enable */
98 { 0x3F, 0x00 }, /* 3F Output Enable */
99
100 { 0x40, 0x00 }, /* 40 Level Control */
101 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
102 { 0x42, 0x00 }, /* 42 Bias Control */
103 { 0x43, 0x00 }, /* 43 DAC Control */
104 { 0x44, 0x06 }, /* 44 ADC Control */
105 { 0x45, 0x00 }, /* 45 Device Shutdown */
106 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
107 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
108 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
109 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
110 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
111 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
112 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
113 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
114 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
115 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
116
117 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
118 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
119 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
120 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
121 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
122 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
123 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
124 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
125 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
126 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
127 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
128 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
129 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
130 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
131 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
132 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
133
134 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
135 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
136 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
137 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
138 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
139 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
140 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
141 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
142 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
143 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
144 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
145 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
146 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
147 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
148 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
149 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
150
151 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
152 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
153 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
154 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
155 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
156 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
157 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
158 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
159 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
160 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
161 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
162 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
163 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
164 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
165 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
166 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
167
168 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
169 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
170 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
171 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
172 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
173 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
174 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
175 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
176 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
177 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
178 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
179 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
180 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
181 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
182 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
183 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
184
185 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
186 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
187 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
188 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
189 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
190 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
191 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
192 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
193 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
194 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
195 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
196 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
197 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
198 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
199 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
200 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
201
202 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
203 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
204 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
205 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
206 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
207 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
208 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
209 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
210 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
211 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
212 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
213 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
214 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
215 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
216 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
217 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
218
219 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
220 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
221 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
222 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
223 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
224 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
225 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
226 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
227 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
228 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
229 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
230 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
231 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
232 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
233 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
234 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
235
236 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
237 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
238 { 0xC2, 0x00 }, /* C2 Sample Rate */
239 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
240 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
241 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
242 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
243 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
244 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
245 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
246 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
247 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
248 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
249 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
250 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
251 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
252
253 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
254 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
255};
27 256
28/* 257static bool max98090_volatile_register(struct device *dev, unsigned int reg)
29 * 258{
30 * MAX98090 Registers Definition 259 switch (reg) {
31 * 260 case M98090_REG_DEVICE_STATUS:
32 */ 261 case M98090_REG_JACK_STATUS:
262 case M98090_REG_REVISION_ID:
263 return true;
264 default:
265 return false;
266 }
267}
33 268
34/* RESET / STATUS / INTERRUPT REGISTERS */ 269static bool max98090_readable_register(struct device *dev, unsigned int reg)
35#define MAX98090_0x00_SW_RESET 0x00 270{
36#define MAX98090_0x01_INT_STS 0x01 271 switch (reg) {
37#define MAX98090_0x02_JACK_STS 0x02 272 case M98090_REG_DEVICE_STATUS:
38#define MAX98090_0x03_INT_MASK 0x03 273 case M98090_REG_JACK_STATUS:
39 274 case M98090_REG_INTERRUPT_S:
40/* QUICK SETUP REGISTERS */ 275 case M98090_REG_RESERVED:
41#define MAX98090_0x04_SYS_CLK 0x04 276 case M98090_REG_LINE_INPUT_CONFIG:
42#define MAX98090_0x05_SAMPLE_RATE 0x05 277 case M98090_REG_LINE_INPUT_LEVEL:
43#define MAX98090_0x06_DAI_IF 0x06 278 case M98090_REG_INPUT_MODE:
44#define MAX98090_0x07_DAC_PATH 0x07 279 case M98090_REG_MIC1_INPUT_LEVEL:
45#define MAX98090_0x08_MIC_TO_ADC 0x08 280 case M98090_REG_MIC2_INPUT_LEVEL:
46#define MAX98090_0x09_LINE_TO_ADC 0x09 281 case M98090_REG_MIC_BIAS_VOLTAGE:
47#define MAX98090_0x0A_ANALOG_MIC_LOOP 0x0A 282 case M98090_REG_DIGITAL_MIC_ENABLE:
48#define MAX98090_0x0B_ANALOG_LINE_LOOP 0x0B 283 case M98090_REG_DIGITAL_MIC_CONFIG:
49 284 case M98090_REG_LEFT_ADC_MIXER:
50/* ANALOG INPUT CONFIGURATION REGISTERS */ 285 case M98090_REG_RIGHT_ADC_MIXER:
51#define MAX98090_0x0D_INPUT_CONFIG 0x0D 286 case M98090_REG_LEFT_ADC_LEVEL:
52#define MAX98090_0x0E_LINE_IN_LVL 0x0E 287 case M98090_REG_RIGHT_ADC_LEVEL:
53#define MAX98090_0x0F_LINI_IN_CFG 0x0F 288 case M98090_REG_ADC_BIQUAD_LEVEL:
54#define MAX98090_0x10_MIC1_IN_LVL 0x10 289 case M98090_REG_ADC_SIDETONE:
55#define MAX98090_0x11_MIC2_IN_LVL 0x11 290 case M98090_REG_SYSTEM_CLOCK:
56 291 case M98090_REG_CLOCK_MODE:
57/* MICROPHONE CONFIGURATION REGISTERS */ 292 case M98090_REG_CLOCK_RATIO_NI_MSB:
58#define MAX98090_0x12_MIC_BIAS_VOL 0x12 293 case M98090_REG_CLOCK_RATIO_NI_LSB:
59#define MAX98090_0x13_DIGITAL_MIC_CFG 0x13 294 case M98090_REG_CLOCK_RATIO_MI_MSB:
60#define MAX98090_0x14_DIGITAL_MIC_MODE 0x14 295 case M98090_REG_CLOCK_RATIO_MI_LSB:
61 296 case M98090_REG_MASTER_MODE:
62/* ADC PATH AND CONFIGURATION REGISTERS */ 297 case M98090_REG_INTERFACE_FORMAT:
63#define MAX98090_0x15_L_ADC_MIX 0x15 298 case M98090_REG_TDM_CONTROL:
64#define MAX98090_0x16_R_ADC_MIX 0x16 299 case M98090_REG_TDM_FORMAT:
65#define MAX98090_0x17_L_ADC_LVL 0x17 300 case M98090_REG_IO_CONFIGURATION:
66#define MAX98090_0x18_R_ADC_LVL 0x18 301 case M98090_REG_FILTER_CONFIG:
67#define MAX98090_0x19_ADC_BIQUAD_LVL 0x19 302 case M98090_REG_DAI_PLAYBACK_LEVEL:
68#define MAX98090_0x1A_ADC_SIDETONE 0x1A 303 case M98090_REG_DAI_PLAYBACK_LEVEL_EQ:
69 304 case M98090_REG_LEFT_HP_MIXER:
70/* CLOCK CONFIGURATION REGISTERS */ 305 case M98090_REG_RIGHT_HP_MIXER:
71#define MAX98090_0x1B_SYS_CLK 0x1B 306 case M98090_REG_HP_CONTROL:
72#define MAX98090_0x1C_CLK_MODE 0x1C 307 case M98090_REG_LEFT_HP_VOLUME:
73#define MAX98090_0x1D_ANY_CLK1 0x1D 308 case M98090_REG_RIGHT_HP_VOLUME:
74#define MAX98090_0x1E_ANY_CLK2 0x1E 309 case M98090_REG_LEFT_SPK_MIXER:
75#define MAX98090_0x1F_ANY_CLK3 0x1F 310 case M98090_REG_RIGHT_SPK_MIXER:
76#define MAX98090_0x20_ANY_CLK4 0x20 311 case M98090_REG_SPK_CONTROL:
77#define MAX98090_0x21_MASTER_MODE 0x21 312 case M98090_REG_LEFT_SPK_VOLUME:
78 313 case M98090_REG_RIGHT_SPK_VOLUME:
79/* INTERFACE CONTROL REGISTERS */ 314 case M98090_REG_DRC_TIMING:
80#define MAX98090_0x22_DAI_IF_FMT 0x22 315 case M98090_REG_DRC_COMPRESSOR:
81#define MAX98090_0x23_DAI_TDM_FMT1 0x23 316 case M98090_REG_DRC_EXPANDER:
82#define MAX98090_0x24_DAI_TDM_FMT2 0x24 317 case M98090_REG_DRC_GAIN:
83#define MAX98090_0x25_DAI_IO_CFG 0x25 318 case M98090_REG_RCV_LOUTL_MIXER:
84#define MAX98090_0x26_FILTER_CFG 0x26 319 case M98090_REG_RCV_LOUTL_CONTROL:
85#define MAX98090_0x27_DAI_PLAYBACK_LVL 0x27 320 case M98090_REG_RCV_LOUTL_VOLUME:
86#define MAX98090_0x28_EQ_PLAYBACK_LVL 0x28 321 case M98090_REG_LOUTR_MIXER:
87 322 case M98090_REG_LOUTR_CONTROL:
88/* HEADPHONE CONTROL REGISTERS */ 323 case M98090_REG_LOUTR_VOLUME:
89#define MAX98090_0x29_L_HP_MIX 0x29 324 case M98090_REG_JACK_DETECT:
90#define MAX98090_0x2A_R_HP_MIX 0x2A 325 case M98090_REG_INPUT_ENABLE:
91#define MAX98090_0x2B_HP_CTR 0x2B 326 case M98090_REG_OUTPUT_ENABLE:
92#define MAX98090_0x2C_L_HP_VOL 0x2C 327 case M98090_REG_LEVEL_CONTROL:
93#define MAX98090_0x2D_R_HP_VOL 0x2D 328 case M98090_REG_DSP_FILTER_ENABLE:
94 329 case M98090_REG_BIAS_CONTROL:
95/* SPEAKER CONFIGURATION REGISTERS */ 330 case M98090_REG_DAC_CONTROL:
96#define MAX98090_0x2E_L_SPK_MIX 0x2E 331 case M98090_REG_ADC_CONTROL:
97#define MAX98090_0x2F_R_SPK_MIX 0x2F 332 case M98090_REG_DEVICE_SHUTDOWN:
98#define MAX98090_0x30_SPK_CTR 0x30 333 case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68:
99#define MAX98090_0x31_L_SPK_VOL 0x31 334 case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E:
100#define MAX98090_0x32_R_SPK_VOL 0x32 335 case M98090_REG_DMIC3_VOLUME:
101 336 case M98090_REG_DMIC4_VOLUME:
102/* ALC CONFIGURATION REGISTERS */ 337 case M98090_REG_DMIC34_BQ_PREATTEN:
103#define MAX98090_0x33_ALC_TIMING 0x33 338 case M98090_REG_RECORD_TDM_SLOT:
104#define MAX98090_0x34_ALC_COMPRESSOR 0x34 339 case M98090_REG_SAMPLE_RATE:
105#define MAX98090_0x35_ALC_EXPANDER 0x35 340 case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E:
106#define MAX98090_0x36_ALC_GAIN 0x36 341 return true;
107 342 default:
108/* RECEIVER AND LINE_OUTPUT REGISTERS */ 343 return false;
109#define MAX98090_0x37_RCV_LOUT_L_MIX 0x37 344 }
110#define MAX98090_0x38_RCV_LOUT_L_CNTL 0x38 345}
111#define MAX98090_0x39_RCV_LOUT_L_VOL 0x39
112#define MAX98090_0x3A_LOUT_R_MIX 0x3A
113#define MAX98090_0x3B_LOUT_R_CNTL 0x3B
114#define MAX98090_0x3C_LOUT_R_VOL 0x3C
115
116/* JACK DETECT AND ENABLE REGISTERS */
117#define MAX98090_0x3D_JACK_DETECT 0x3D
118#define MAX98090_0x3E_IN_ENABLE 0x3E
119#define MAX98090_0x3F_OUT_ENABLE 0x3F
120#define MAX98090_0x40_LVL_CTR 0x40
121#define MAX98090_0x41_DSP_FILTER_ENABLE 0x41
122
123/* BIAS AND POWER MODE CONFIGURATION REGISTERS */
124#define MAX98090_0x42_BIAS_CTR 0x42
125#define MAX98090_0x43_DAC_CTR 0x43
126#define MAX98090_0x44_ADC_CTR 0x44
127#define MAX98090_0x45_DEV_SHUTDOWN 0x45
128
129/* REVISION ID REGISTER */
130#define MAX98090_0xFF_REV_ID 0xFF
131
132#define MAX98090_REG_MAX_CACHED 0x45
133#define MAX98090_REG_END 0xFF
134 346
135/* 347static int max98090_reset(struct max98090_priv *max98090)
136 * 348{
137 * MAX98090 Registers Bit Fields 349 int ret;
138 *
139 */
140 350
141/* MAX98090_0x06_DAI_IF */ 351 /* Reset the codec by writing to this write-only reset register */
142#define MAX98090_DAI_IF_MASK 0x3F 352 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
143#define MAX98090_RJ_M (1 << 5) 353 M98090_SWRESET_MASK);
144#define MAX98090_RJ_S (1 << 4) 354 if (ret < 0) {
145#define MAX98090_LJ_M (1 << 3) 355 dev_err(max98090->codec->dev,
146#define MAX98090_LJ_S (1 << 2) 356 "Failed to reset codec: %d\n", ret);
147#define MAX98090_I2S_M (1 << 1) 357 return ret;
148#define MAX98090_I2S_S (1 << 0) 358 }
149 359
150/* MAX98090_0x45_DEV_SHUTDOWN */ 360 msleep(20);
151#define MAX98090_SHDNRUN (1 << 7) 361 return ret;
152 362}
153/* codec private data */ 363
154struct max98090_priv { 364static const unsigned int max98090_micboost_tlv[] = {
155 struct regmap *regmap; 365 TLV_DB_RANGE_HEAD(2),
156}; 366 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
157 367 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
158static const struct reg_default max98090_reg_defaults[] = { 368};
159 /* RESET / STATUS / INTERRUPT REGISTERS */ 369
160 {MAX98090_0x00_SW_RESET, 0x00}, 370static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
161 {MAX98090_0x01_INT_STS, 0x00}, 371
162 {MAX98090_0x02_JACK_STS, 0x00}, 372static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
163 {MAX98090_0x03_INT_MASK, 0x04}, 373 -600, 600, 0);
164 374
165 /* QUICK SETUP REGISTERS */ 375static const unsigned int max98090_line_tlv[] = {
166 {MAX98090_0x04_SYS_CLK, 0x00}, 376 TLV_DB_RANGE_HEAD(2),
167 {MAX98090_0x05_SAMPLE_RATE, 0x00}, 377 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
168 {MAX98090_0x06_DAI_IF, 0x00}, 378 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
169 {MAX98090_0x07_DAC_PATH, 0x00}, 379};
170 {MAX98090_0x08_MIC_TO_ADC, 0x00}, 380
171 {MAX98090_0x09_LINE_TO_ADC, 0x00}, 381static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
172 {MAX98090_0x0A_ANALOG_MIC_LOOP, 0x00}, 382static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
173 {MAX98090_0x0B_ANALOG_LINE_LOOP, 0x00}, 383
174 384static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
175 /* ANALOG INPUT CONFIGURATION REGISTERS */ 385static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
176 {MAX98090_0x0D_INPUT_CONFIG, 0x00}, 386
177 {MAX98090_0x0E_LINE_IN_LVL, 0x1B}, 387static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0);
178 {MAX98090_0x0F_LINI_IN_CFG, 0x00}, 388
179 {MAX98090_0x10_MIC1_IN_LVL, 0x11}, 389static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
180 {MAX98090_0x11_MIC2_IN_LVL, 0x11}, 390static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
181 391static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
182 /* MICROPHONE CONFIGURATION REGISTERS */ 392static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
183 {MAX98090_0x12_MIC_BIAS_VOL, 0x00}, 393
184 {MAX98090_0x13_DIGITAL_MIC_CFG, 0x00}, 394static const unsigned int max98090_mixout_tlv[] = {
185 {MAX98090_0x14_DIGITAL_MIC_MODE, 0x00}, 395 TLV_DB_RANGE_HEAD(2),
186 396 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
187 /* ADC PATH AND CONFIGURATION REGISTERS */ 397 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0),
188 {MAX98090_0x15_L_ADC_MIX, 0x00},
189 {MAX98090_0x16_R_ADC_MIX, 0x00},
190 {MAX98090_0x17_L_ADC_LVL, 0x03},
191 {MAX98090_0x18_R_ADC_LVL, 0x03},
192 {MAX98090_0x19_ADC_BIQUAD_LVL, 0x00},
193 {MAX98090_0x1A_ADC_SIDETONE, 0x00},
194
195 /* CLOCK CONFIGURATION REGISTERS */
196 {MAX98090_0x1B_SYS_CLK, 0x00},
197 {MAX98090_0x1C_CLK_MODE, 0x00},
198 {MAX98090_0x1D_ANY_CLK1, 0x00},
199 {MAX98090_0x1E_ANY_CLK2, 0x00},
200 {MAX98090_0x1F_ANY_CLK3, 0x00},
201 {MAX98090_0x20_ANY_CLK4, 0x00},
202 {MAX98090_0x21_MASTER_MODE, 0x00},
203
204 /* INTERFACE CONTROL REGISTERS */
205 {MAX98090_0x22_DAI_IF_FMT, 0x00},
206 {MAX98090_0x23_DAI_TDM_FMT1, 0x00},
207 {MAX98090_0x24_DAI_TDM_FMT2, 0x00},
208 {MAX98090_0x25_DAI_IO_CFG, 0x00},
209 {MAX98090_0x26_FILTER_CFG, 0x80},
210 {MAX98090_0x27_DAI_PLAYBACK_LVL, 0x00},
211 {MAX98090_0x28_EQ_PLAYBACK_LVL, 0x00},
212
213 /* HEADPHONE CONTROL REGISTERS */
214 {MAX98090_0x29_L_HP_MIX, 0x00},
215 {MAX98090_0x2A_R_HP_MIX, 0x00},
216 {MAX98090_0x2B_HP_CTR, 0x00},
217 {MAX98090_0x2C_L_HP_VOL, 0x1A},
218 {MAX98090_0x2D_R_HP_VOL, 0x1A},
219
220 /* SPEAKER CONFIGURATION REGISTERS */
221 {MAX98090_0x2E_L_SPK_MIX, 0x00},
222 {MAX98090_0x2F_R_SPK_MIX, 0x00},
223 {MAX98090_0x30_SPK_CTR, 0x00},
224 {MAX98090_0x31_L_SPK_VOL, 0x2C},
225 {MAX98090_0x32_R_SPK_VOL, 0x2C},
226
227 /* ALC CONFIGURATION REGISTERS */
228 {MAX98090_0x33_ALC_TIMING, 0x00},
229 {MAX98090_0x34_ALC_COMPRESSOR, 0x00},
230 {MAX98090_0x35_ALC_EXPANDER, 0x00},
231 {MAX98090_0x36_ALC_GAIN, 0x00},
232
233 /* RECEIVER AND LINE_OUTPUT REGISTERS */
234 {MAX98090_0x37_RCV_LOUT_L_MIX, 0x00},
235 {MAX98090_0x38_RCV_LOUT_L_CNTL, 0x00},
236 {MAX98090_0x39_RCV_LOUT_L_VOL, 0x15},
237 {MAX98090_0x3A_LOUT_R_MIX, 0x00},
238 {MAX98090_0x3B_LOUT_R_CNTL, 0x00},
239 {MAX98090_0x3C_LOUT_R_VOL, 0x15},
240
241 /* JACK DETECT AND ENABLE REGISTERS */
242 {MAX98090_0x3D_JACK_DETECT, 0x00},
243 {MAX98090_0x3E_IN_ENABLE, 0x00},
244 {MAX98090_0x3F_OUT_ENABLE, 0x00},
245 {MAX98090_0x40_LVL_CTR, 0x00},
246 {MAX98090_0x41_DSP_FILTER_ENABLE, 0x00},
247
248 /* BIAS AND POWER MODE CONFIGURATION REGISTERS */
249 {MAX98090_0x42_BIAS_CTR, 0x00},
250 {MAX98090_0x43_DAC_CTR, 0x00},
251 {MAX98090_0x44_ADC_CTR, 0x06},
252 {MAX98090_0x45_DEV_SHUTDOWN, 0x00},
253}; 398};
254 399
255static const unsigned int max98090_hp_tlv[] = { 400static const unsigned int max98090_hp_tlv[] = {
256 TLV_DB_RANGE_HEAD(5), 401 TLV_DB_RANGE_HEAD(5),
257 0x0, 0x6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 402 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
258 0x7, 0xE, TLV_DB_SCALE_ITEM(-4000, 300, 0), 403 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
259 0xF, 0x15, TLV_DB_SCALE_ITEM(-1700, 200, 0), 404 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
260 0x16, 0x1B, TLV_DB_SCALE_ITEM(-400, 100, 0), 405 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
261 0x1C, 0x1F, TLV_DB_SCALE_ITEM(150, 50, 0), 406 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
262}; 407};
263 408
264static struct snd_kcontrol_new max98090_snd_controls[] = { 409static const unsigned int max98090_spk_tlv[] = {
265 SOC_DOUBLE_R_TLV("Headphone Volume", MAX98090_0x2C_L_HP_VOL, 410 TLV_DB_RANGE_HEAD(5),
266 MAX98090_0x2D_R_HP_VOL, 0, 31, 0, max98090_hp_tlv), 411 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
412 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
413 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
414 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
415 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0),
267}; 416};
268 417
269/* Left HeadPhone Mixer Switch */ 418static const unsigned int max98090_rcv_lout_tlv[] = {
270static struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { 419 TLV_DB_RANGE_HEAD(5),
271 SOC_DAPM_SINGLE("DACR Switch", MAX98090_0x29_L_HP_MIX, 1, 1, 0), 420 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
272 SOC_DAPM_SINGLE("DACL Switch", MAX98090_0x29_L_HP_MIX, 0, 1, 0), 421 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
422 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
423 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
424 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
273}; 425};
274 426
275/* Right HeadPhone Mixer Switch */ 427static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
276static struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { 428 struct snd_ctl_elem_value *ucontrol)
277 SOC_DAPM_SINGLE("DACR Switch", MAX98090_0x2A_R_HP_MIX, 1, 1, 0), 429{
278 SOC_DAPM_SINGLE("DACL Switch", MAX98090_0x2A_R_HP_MIX, 0, 1, 0), 430 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
431 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
432 struct soc_mixer_control *mc =
433 (struct soc_mixer_control *)kcontrol->private_value;
434 unsigned int mask = (1 << fls(mc->max)) - 1;
435 unsigned int val = snd_soc_read(codec, mc->reg);
436 unsigned int *select;
437
438 switch (mc->reg) {
439 case M98090_REG_MIC1_INPUT_LEVEL:
440 select = &(max98090->pa1en);
441 break;
442 case M98090_REG_MIC2_INPUT_LEVEL:
443 select = &(max98090->pa2en);
444 break;
445 case M98090_REG_ADC_SIDETONE:
446 select = &(max98090->sidetone);
447 break;
448 default:
449 return -EINVAL;
450 }
451
452 val = (val >> mc->shift) & mask;
453
454 if (val >= 1) {
455 /* If on, return the volume */
456 val = val - 1;
457 *select = val;
458 } else {
459 /* If off, return last stored value */
460 val = *select;
461 }
462
463 ucontrol->value.integer.value[0] = val;
464 return 0;
465}
466
467static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
468 struct snd_ctl_elem_value *ucontrol)
469{
470 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
471 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
472 struct soc_mixer_control *mc =
473 (struct soc_mixer_control *)kcontrol->private_value;
474 unsigned int mask = (1 << fls(mc->max)) - 1;
475 unsigned int sel = ucontrol->value.integer.value[0];
476 unsigned int val = snd_soc_read(codec, mc->reg);
477 unsigned int *select;
478
479 switch (mc->reg) {
480 case M98090_REG_MIC1_INPUT_LEVEL:
481 select = &(max98090->pa1en);
482 break;
483 case M98090_REG_MIC2_INPUT_LEVEL:
484 select = &(max98090->pa2en);
485 break;
486 case M98090_REG_ADC_SIDETONE:
487 select = &(max98090->sidetone);
488 break;
489 default:
490 return -EINVAL;
491 }
492
493 val = (val >> mc->shift) & mask;
494
495 *select = sel;
496
497 /* Setting a volume is only valid if it is already On */
498 if (val >= 1) {
499 sel = sel + 1;
500 } else {
501 /* Write what was already there */
502 sel = val;
503 }
504
505 snd_soc_update_bits(codec, mc->reg,
506 mask << mc->shift,
507 sel << mc->shift);
508
509 return 0;
510}
511
512static const char * max98090_perf_pwr_text[] =
513 { "High Performance", "Low Power" };
514static const char * max98090_pwr_perf_text[] =
515 { "Low Power", "High Performance" };
516
517static const struct soc_enum max98090_vcmbandgap_enum =
518 SOC_ENUM_SINGLE(M98090_REG_BIAS_CONTROL, M98090_VCM_MODE_SHIFT,
519 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
520
521static const char * max98090_osr128_text[] = { "64*fs", "128*fs" };
522
523static const struct soc_enum max98090_osr128_enum =
524 SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL, M98090_OSR128_SHIFT,
525 ARRAY_SIZE(max98090_osr128_text), max98090_osr128_text);
526
527static const char *max98090_mode_text[] = { "Voice", "Music" };
528
529static const struct soc_enum max98090_mode_enum =
530 SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG, M98090_MODE_SHIFT,
531 ARRAY_SIZE(max98090_mode_text), max98090_mode_text);
532
533static const struct soc_enum max98090_filter_dmic34mode_enum =
534 SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG,
535 M98090_FLT_DMIC34MODE_SHIFT,
536 ARRAY_SIZE(max98090_mode_text), max98090_mode_text);
537
538static const char * max98090_drcatk_text[] =
539 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
540
541static const struct soc_enum max98090_drcatk_enum =
542 SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING, M98090_DRCATK_SHIFT,
543 ARRAY_SIZE(max98090_drcatk_text), max98090_drcatk_text);
544
545static const char * max98090_drcrls_text[] =
546 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
547
548static const struct soc_enum max98090_drcrls_enum =
549 SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING, M98090_DRCRLS_SHIFT,
550 ARRAY_SIZE(max98090_drcrls_text), max98090_drcrls_text);
551
552static const char * max98090_alccmp_text[] =
553 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
554
555static const struct soc_enum max98090_alccmp_enum =
556 SOC_ENUM_SINGLE(M98090_REG_DRC_COMPRESSOR, M98090_DRCCMP_SHIFT,
557 ARRAY_SIZE(max98090_alccmp_text), max98090_alccmp_text);
558
559static const char * max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
560
561static const struct soc_enum max98090_drcexp_enum =
562 SOC_ENUM_SINGLE(M98090_REG_DRC_EXPANDER, M98090_DRCEXP_SHIFT,
563 ARRAY_SIZE(max98090_drcexp_text), max98090_drcexp_text);
564
565static const struct soc_enum max98090_dac_perfmode_enum =
566 SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL, M98090_PERFMODE_SHIFT,
567 ARRAY_SIZE(max98090_perf_pwr_text), max98090_perf_pwr_text);
568
569static const struct soc_enum max98090_dachp_enum =
570 SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL, M98090_DACHP_SHIFT,
571 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
572
573static const struct soc_enum max98090_adchp_enum =
574 SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL, M98090_ADCHP_SHIFT,
575 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
576
577static const struct snd_kcontrol_new max98090_snd_controls[] = {
578 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
579
580 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
581 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
582
583 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
584 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
585 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
586 max98090_put_enab_tlv, max98090_micboost_tlv),
587
588 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
589 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
590 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
591 max98090_put_enab_tlv, max98090_micboost_tlv),
592
593 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
594 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
595 max98090_mic_tlv),
596
597 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
598 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
599 max98090_mic_tlv),
600
601 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
602 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
603 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
604
605 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
606 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
607 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
608
609 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
610 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
611 max98090_line_tlv),
612
613 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
614 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
615 max98090_line_tlv),
616
617 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
618 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
619 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
620 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
621
622 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
623 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
624 max98090_avg_tlv),
625 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
626 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
627 max98090_avg_tlv),
628
629 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
630 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
631 max98090_av_tlv),
632 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
633 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
634 max98090_av_tlv),
635
636 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
637 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
638 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
639 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
640
641 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
642 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
643 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
644 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
645 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
646 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
647 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
648 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
649 SOC_ENUM("Filter Mode", max98090_mode_enum),
650 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
651 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
652 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
653 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
654 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
655 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
656 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
657 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
658 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
659 max98090_put_enab_tlv, max98090_micboost_tlv),
660 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
661 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
662 max98090_dvg_tlv),
663 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
664 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
665 max98090_dv_tlv),
666 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
667 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
668 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
669 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
670 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
671 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
672 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
673 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
674 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
675 1),
676 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
677 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
678 max98090_dv_tlv),
679
680 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
681 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
682 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
683 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
684 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
685 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
686 max98090_alcmakeup_tlv),
687 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
688 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
689 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
690 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
691 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
692 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
693 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
694 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
695
696 SOC_ENUM("DAC HP Playback Performance Mode",
697 max98090_dac_perfmode_enum),
698 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
699
700 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
701 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
702 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
703 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
704 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
705 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
706
707 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
708 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
709 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
710 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
711 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
712 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
713
714 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
715 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
716 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
717 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
718 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
719 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
720
721 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
722 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
723 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
724
725 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
726 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
727 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
728 0, max98090_spk_tlv),
729
730 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
731 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
732 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
733
734 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
735 M98090_HPLM_SHIFT, 1, 1),
736 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
737 M98090_HPRM_SHIFT, 1, 1),
738
739 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
740 M98090_SPLM_SHIFT, 1, 1),
741 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
742 M98090_SPRM_SHIFT, 1, 1),
743
744 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
745 M98090_RCVLM_SHIFT, 1, 1),
746 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
747 M98090_RCVRM_SHIFT, 1, 1),
748
749 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
750 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
751 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
752 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
753 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
754 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
755
756 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
757 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
758 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
279}; 759};
280 760
281static struct snd_soc_dapm_widget max98090_dapm_widgets[] = { 761static const struct snd_kcontrol_new max98091_snd_controls[] = {
282 /* Output */ 762
763 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
764 M98090_DMIC34_ZEROPAD_SHIFT,
765 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
766
767 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
768 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
769 M98090_FLT_DMIC34HPF_SHIFT,
770 M98090_FLT_DMIC34HPF_NUM - 1, 0),
771
772 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
773 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
774 max98090_avg_tlv),
775 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
776 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
777 max98090_avg_tlv),
778
779 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
780 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
781 max98090_av_tlv),
782 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
783 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
784 max98090_av_tlv),
785
786 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
787 M98090_REG_DMIC34_BIQUAD_BASE, 15),
788 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
789 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
790
791 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
792 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
793 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
794};
795
796static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
797 struct snd_kcontrol *kcontrol, int event)
798{
799 struct snd_soc_codec *codec = w->codec;
800 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
801
802 unsigned int val = snd_soc_read(codec, w->reg);
803
804 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
805 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
806 else
807 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
808
809
810 if (val >= 1) {
811 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
812 max98090->pa1en = val - 1; /* Update for volatile */
813 } else {
814 max98090->pa2en = val - 1; /* Update for volatile */
815 }
816 }
817
818 switch (event) {
819 case SND_SOC_DAPM_POST_PMU:
820 /* If turning on, set to most recently selected volume */
821 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
822 val = max98090->pa1en + 1;
823 else
824 val = max98090->pa2en + 1;
825 break;
826 case SND_SOC_DAPM_POST_PMD:
827 /* If turning off, turn off */
828 val = 0;
829 break;
830 default:
831 return -EINVAL;
832 }
833
834 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
835 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK,
836 val << M98090_MIC_PA1EN_SHIFT);
837 else
838 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK,
839 val << M98090_MIC_PA2EN_SHIFT);
840
841 return 0;
842}
843
844static const char *mic1_mux_text[] = { "IN12", "IN56" };
845
846static const struct soc_enum mic1_mux_enum =
847 SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE, M98090_EXTMIC1_SHIFT,
848 ARRAY_SIZE(mic1_mux_text), mic1_mux_text);
849
850static const struct snd_kcontrol_new max98090_mic1_mux =
851 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
852
853static const char *mic2_mux_text[] = { "IN34", "IN56" };
854
855static const struct soc_enum mic2_mux_enum =
856 SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE, M98090_EXTMIC2_SHIFT,
857 ARRAY_SIZE(mic2_mux_text), mic2_mux_text);
858
859static const struct snd_kcontrol_new max98090_mic2_mux =
860 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
861
862static const char * max98090_micpre_text[] = { "Off", "On" };
863
864static const struct soc_enum max98090_pa1en_enum =
865 SOC_ENUM_SINGLE(M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
866 ARRAY_SIZE(max98090_micpre_text), max98090_micpre_text);
867
868static const struct soc_enum max98090_pa2en_enum =
869 SOC_ENUM_SINGLE(M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
870 ARRAY_SIZE(max98090_micpre_text), max98090_micpre_text);
871
872/* LINEA mixer switch */
873static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
874 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
875 M98090_IN1SEEN_SHIFT, 1, 0),
876 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
877 M98090_IN3SEEN_SHIFT, 1, 0),
878 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
879 M98090_IN5SEEN_SHIFT, 1, 0),
880 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
881 M98090_IN34DIFF_SHIFT, 1, 0),
882};
883
884/* LINEB mixer switch */
885static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
886 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
887 M98090_IN2SEEN_SHIFT, 1, 0),
888 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
889 M98090_IN4SEEN_SHIFT, 1, 0),
890 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
891 M98090_IN6SEEN_SHIFT, 1, 0),
892 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
893 M98090_IN56DIFF_SHIFT, 1, 0),
894};
895
896/* Left ADC mixer switch */
897static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
898 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
899 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
900 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
901 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
902 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
903 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
904 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
905 M98090_MIXADL_LINEA_SHIFT, 1, 0),
906 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
907 M98090_MIXADL_LINEB_SHIFT, 1, 0),
908 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
909 M98090_MIXADL_MIC1_SHIFT, 1, 0),
910 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
911 M98090_MIXADL_MIC2_SHIFT, 1, 0),
912};
913
914/* Right ADC mixer switch */
915static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
916 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
917 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
918 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
919 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
920 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
921 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
922 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
923 M98090_MIXADR_LINEA_SHIFT, 1, 0),
924 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
925 M98090_MIXADR_LINEB_SHIFT, 1, 0),
926 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
927 M98090_MIXADR_MIC1_SHIFT, 1, 0),
928 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
929 M98090_MIXADR_MIC2_SHIFT, 1, 0),
930};
931
932static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
933
934static const struct soc_enum ltenl_mux_enum =
935 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LTEN_SHIFT,
936 ARRAY_SIZE(lten_mux_text), lten_mux_text);
937
938static const struct soc_enum ltenr_mux_enum =
939 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LTEN_SHIFT,
940 ARRAY_SIZE(lten_mux_text), lten_mux_text);
941
942static const struct snd_kcontrol_new max98090_ltenl_mux =
943 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
944
945static const struct snd_kcontrol_new max98090_ltenr_mux =
946 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
947
948static const char *lben_mux_text[] = { "Normal", "Loopback" };
949
950static const struct soc_enum lbenl_mux_enum =
951 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LBEN_SHIFT,
952 ARRAY_SIZE(lben_mux_text), lben_mux_text);
953
954static const struct soc_enum lbenr_mux_enum =
955 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LBEN_SHIFT,
956 ARRAY_SIZE(lben_mux_text), lben_mux_text);
957
958static const struct snd_kcontrol_new max98090_lbenl_mux =
959 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
960
961static const struct snd_kcontrol_new max98090_lbenr_mux =
962 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
963
964static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
965
966static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
967
968static const struct soc_enum stenl_mux_enum =
969 SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE, M98090_DSTSL_SHIFT,
970 ARRAY_SIZE(stenl_mux_text), stenl_mux_text);
971
972static const struct soc_enum stenr_mux_enum =
973 SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE, M98090_DSTSR_SHIFT,
974 ARRAY_SIZE(stenr_mux_text), stenr_mux_text);
975
976static const struct snd_kcontrol_new max98090_stenl_mux =
977 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
978
979static const struct snd_kcontrol_new max98090_stenr_mux =
980 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
981
982/* Left speaker mixer switch */
983static const struct
984 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
985 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
986 M98090_MIXSPL_DACL_SHIFT, 1, 0),
987 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
988 M98090_MIXSPL_DACR_SHIFT, 1, 0),
989 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
990 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
991 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
992 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
993 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
994 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
995 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
996 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
997};
998
999/* Right speaker mixer switch */
1000static const struct
1001 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
1002 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1003 M98090_MIXSPR_DACL_SHIFT, 1, 0),
1004 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1005 M98090_MIXSPR_DACR_SHIFT, 1, 0),
1006 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
1007 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
1008 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
1009 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
1010 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
1011 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
1012 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
1013 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
1014};
1015
1016/* Left headphone mixer switch */
1017static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
1018 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
1019 M98090_MIXHPL_DACL_SHIFT, 1, 0),
1020 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
1021 M98090_MIXHPL_DACR_SHIFT, 1, 0),
1022 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
1023 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
1024 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
1025 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
1026 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
1027 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
1028 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
1029 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
1030};
1031
1032/* Right headphone mixer switch */
1033static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
1034 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1035 M98090_MIXHPR_DACL_SHIFT, 1, 0),
1036 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1037 M98090_MIXHPR_DACR_SHIFT, 1, 0),
1038 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1039 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
1040 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1041 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
1042 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1043 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
1044 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1045 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1046};
1047
1048/* Left receiver mixer switch */
1049static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1050 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1051 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1052 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1053 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1054 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1055 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1056 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1057 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1058 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1059 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1060 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1061 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1062};
1063
1064/* Right receiver mixer switch */
1065static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1066 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1067 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1068 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1069 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1070 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1071 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1072 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1073 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1074 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1075 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1076 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1077 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1078};
1079
1080static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1081
1082static const struct soc_enum linmod_mux_enum =
1083 SOC_ENUM_SINGLE(M98090_REG_LOUTR_MIXER, M98090_LINMOD_SHIFT,
1084 ARRAY_SIZE(linmod_mux_text), linmod_mux_text);
1085
1086static const struct snd_kcontrol_new max98090_linmod_mux =
1087 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1088
1089static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1090
1091/*
1092 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1093 */
1094static const struct soc_enum mixhplsel_mux_enum =
1095 SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL, M98090_MIXHPLSEL_SHIFT,
1096 ARRAY_SIZE(mixhpsel_mux_text), mixhpsel_mux_text);
1097
1098static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1099 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1100
1101static const struct soc_enum mixhprsel_mux_enum =
1102 SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL, M98090_MIXHPRSEL_SHIFT,
1103 ARRAY_SIZE(mixhpsel_mux_text), mixhpsel_mux_text);
1104
1105static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1106 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1107
1108static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1109
1110 SND_SOC_DAPM_INPUT("MIC1"),
1111 SND_SOC_DAPM_INPUT("MIC2"),
1112 SND_SOC_DAPM_INPUT("DMICL"),
1113 SND_SOC_DAPM_INPUT("DMICR"),
1114 SND_SOC_DAPM_INPUT("IN1"),
1115 SND_SOC_DAPM_INPUT("IN2"),
1116 SND_SOC_DAPM_INPUT("IN3"),
1117 SND_SOC_DAPM_INPUT("IN4"),
1118 SND_SOC_DAPM_INPUT("IN5"),
1119 SND_SOC_DAPM_INPUT("IN6"),
1120 SND_SOC_DAPM_INPUT("IN12"),
1121 SND_SOC_DAPM_INPUT("IN34"),
1122 SND_SOC_DAPM_INPUT("IN56"),
1123
1124 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1125 M98090_MBEN_SHIFT, 0, NULL, 0),
1126 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1127 M98090_SHDNN_SHIFT, 0, NULL, 0),
1128 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1129 M98090_SDIEN_SHIFT, 0, NULL, 0),
1130 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1131 M98090_SDOEN_SHIFT, 0, NULL, 0),
1132 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1133 M98090_DIGMICL_SHIFT, 0, NULL, 0),
1134 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1135 M98090_DIGMICR_SHIFT, 0, NULL, 0),
1136 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1137 M98090_AHPF_SHIFT, 0, NULL, 0),
1138
1139/*
1140 * Note: Sysclk and misc power supplies are taken care of by SHDN
1141 */
1142
1143 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1144 0, 0, &max98090_mic1_mux),
1145
1146 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1147 0, 0, &max98090_mic2_mux),
1148
1149 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1150 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1151 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1152
1153 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1154 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1155 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1156
1157 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1158 &max98090_linea_mixer_controls[0],
1159 ARRAY_SIZE(max98090_linea_mixer_controls)),
1160
1161 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1162 &max98090_lineb_mixer_controls[0],
1163 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1164
1165 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1166 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1167 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1168 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1169
1170 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1171 &max98090_left_adc_mixer_controls[0],
1172 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1173
1174 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1175 &max98090_right_adc_mixer_controls[0],
1176 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1177
1178 SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1179 M98090_ADLEN_SHIFT, 0),
1180 SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1181 M98090_ADREN_SHIFT, 0),
1182
1183 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1184 SND_SOC_NOPM, 0, 0),
1185 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1186 SND_SOC_NOPM, 0, 0),
1187
1188 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1189 0, 0, &max98090_lbenl_mux),
1190
1191 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1192 0, 0, &max98090_lbenr_mux),
1193
1194 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1195 0, 0, &max98090_ltenl_mux),
1196
1197 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1198 0, 0, &max98090_ltenr_mux),
1199
1200 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1201 0, 0, &max98090_stenl_mux),
1202
1203 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1204 0, 0, &max98090_stenr_mux),
1205
1206 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1207 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1208
1209 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1210 M98090_DALEN_SHIFT, 0),
1211 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1212 M98090_DAREN_SHIFT, 0),
1213
1214 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1215 &max98090_left_hp_mixer_controls[0],
1216 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1217
1218 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1219 &max98090_right_hp_mixer_controls[0],
1220 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1221
1222 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1223 &max98090_left_speaker_mixer_controls[0],
1224 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1225
1226 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1227 &max98090_right_speaker_mixer_controls[0],
1228 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1229
1230 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1231 &max98090_left_rcv_mixer_controls[0],
1232 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1233
1234 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1235 &max98090_right_rcv_mixer_controls[0],
1236 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1237
1238 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER,
1239 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux),
1240
1241 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL,
1242 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux),
1243
1244 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL,
1245 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux),
1246
1247 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1248 M98090_HPLEN_SHIFT, 0, NULL, 0),
1249 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1250 M98090_HPREN_SHIFT, 0, NULL, 0),
1251
1252 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1253 M98090_SPLEN_SHIFT, 0, NULL, 0),
1254 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1255 M98090_SPREN_SHIFT, 0, NULL, 0),
1256
1257 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1258 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1259 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1260 M98090_RCVREN_SHIFT, 0, NULL, 0),
1261
283 SND_SOC_DAPM_OUTPUT("HPL"), 1262 SND_SOC_DAPM_OUTPUT("HPL"),
284 SND_SOC_DAPM_OUTPUT("HPR"), 1263 SND_SOC_DAPM_OUTPUT("HPR"),
1264 SND_SOC_DAPM_OUTPUT("SPKL"),
1265 SND_SOC_DAPM_OUTPUT("SPKR"),
1266 SND_SOC_DAPM_OUTPUT("RCVL"),
1267 SND_SOC_DAPM_OUTPUT("RCVR"),
1268};
1269
1270static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
285 1271
286 /* PGA */ 1272 SND_SOC_DAPM_INPUT("DMIC3"),
287 SND_SOC_DAPM_PGA("HPL Out", MAX98090_0x3F_OUT_ENABLE, 7, 0, NULL, 0), 1273 SND_SOC_DAPM_INPUT("DMIC4"),
288 SND_SOC_DAPM_PGA("HPR Out", MAX98090_0x3F_OUT_ENABLE, 6, 0, NULL, 0),
289 1274
290 /* Mixer */ 1275 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
291 SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0, 1276 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
292 max98090_left_hp_mixer_controls, 1277 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
293 ARRAY_SIZE(max98090_left_hp_mixer_controls)), 1278 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1279};
294 1280
295 SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0, 1281static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
296 max98090_right_hp_mixer_controls, 1282
297 ARRAY_SIZE(max98090_right_hp_mixer_controls)), 1283 {"MIC1 Input", NULL, "MIC1"},
1284 {"MIC2 Input", NULL, "MIC2"},
1285
1286 {"DMICL", NULL, "DMICL_ENA"},
1287 {"DMICR", NULL, "DMICR_ENA"},
1288 {"DMICL", NULL, "AHPF"},
1289 {"DMICR", NULL, "AHPF"},
1290
1291 /* MIC1 input mux */
1292 {"MIC1 Mux", "IN12", "IN12"},
1293 {"MIC1 Mux", "IN56", "IN56"},
1294
1295 /* MIC2 input mux */
1296 {"MIC2 Mux", "IN34", "IN34"},
1297 {"MIC2 Mux", "IN56", "IN56"},
1298
1299 {"MIC1 Input", NULL, "MIC1 Mux"},
1300 {"MIC2 Input", NULL, "MIC2 Mux"},
1301
1302 /* Left ADC input mixer */
1303 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1304 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1305 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1306 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1307 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1308 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1309 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1310
1311 /* Right ADC input mixer */
1312 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1313 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1314 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1315 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1316 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1317 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1318 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1319
1320 /* Line A input mixer */
1321 {"LINEA Mixer", "IN1 Switch", "IN1"},
1322 {"LINEA Mixer", "IN3 Switch", "IN3"},
1323 {"LINEA Mixer", "IN5 Switch", "IN5"},
1324 {"LINEA Mixer", "IN34 Switch", "IN34"},
1325
1326 /* Line B input mixer */
1327 {"LINEB Mixer", "IN2 Switch", "IN2"},
1328 {"LINEB Mixer", "IN4 Switch", "IN4"},
1329 {"LINEB Mixer", "IN6 Switch", "IN6"},
1330 {"LINEB Mixer", "IN56 Switch", "IN56"},
1331
1332 {"LINEA Input", NULL, "LINEA Mixer"},
1333 {"LINEB Input", NULL, "LINEB Mixer"},
1334
1335 /* Inputs */
1336 {"ADCL", NULL, "Left ADC Mixer"},
1337 {"ADCR", NULL, "Right ADC Mixer"},
1338 {"ADCL", NULL, "SHDN"},
1339 {"ADCR", NULL, "SHDN"},
1340
1341 {"LBENL Mux", "Normal", "ADCL"},
1342 {"LBENL Mux", "Normal", "DMICL"},
1343 {"LBENL Mux", "Loopback", "LTENL Mux"},
1344 {"LBENR Mux", "Normal", "ADCR"},
1345 {"LBENR Mux", "Normal", "DMICR"},
1346 {"LBENR Mux", "Loopback", "LTENR Mux"},
1347
1348 {"AIFOUTL", NULL, "LBENL Mux"},
1349 {"AIFOUTR", NULL, "LBENR Mux"},
1350 {"AIFOUTL", NULL, "SHDN"},
1351 {"AIFOUTR", NULL, "SHDN"},
1352 {"AIFOUTL", NULL, "SDOEN"},
1353 {"AIFOUTR", NULL, "SDOEN"},
1354
1355 {"LTENL Mux", "Normal", "AIFINL"},
1356 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1357 {"LTENR Mux", "Normal", "AIFINR"},
1358 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1359
1360 {"DACL", NULL, "LTENL Mux"},
1361 {"DACR", NULL, "LTENR Mux"},
1362
1363 {"STENL Mux", "Sidetone Left", "ADCL"},
1364 {"STENL Mux", "Sidetone Left", "DMICL"},
1365 {"STENR Mux", "Sidetone Right", "ADCR"},
1366 {"STENR Mux", "Sidetone Right", "DMICR"},
1367 {"DACL", "NULL", "STENL Mux"},
1368 {"DACR", "NULL", "STENL Mux"},
1369
1370 {"AIFINL", NULL, "SHDN"},
1371 {"AIFINR", NULL, "SHDN"},
1372 {"AIFINL", NULL, "SDIEN"},
1373 {"AIFINR", NULL, "SDIEN"},
1374 {"DACL", NULL, "SHDN"},
1375 {"DACR", NULL, "SHDN"},
1376
1377 /* Left headphone output mixer */
1378 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1379 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1380 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1381 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1382 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1383 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1384
1385 /* Right headphone output mixer */
1386 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1387 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1388 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1389 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1390 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1391 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1392
1393 /* Left speaker output mixer */
1394 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1395 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1396 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1397 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1398 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1399 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1400
1401 /* Right speaker output mixer */
1402 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1403 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1404 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1405 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1406 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1407 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1408
1409 /* Left Receiver output mixer */
1410 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1411 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1412 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1413 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1414 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1415 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1416
1417 /* Right Receiver output mixer */
1418 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1419 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1420 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1421 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1422 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1423 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1424
1425 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1426
1427 /*
1428 * Disable this for lowest power if bypassing
1429 * the DAC with an analog signal
1430 */
1431 {"HP Left Out", NULL, "DACL"},
1432 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1433
1434 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1435
1436 /*
1437 * Disable this for lowest power if bypassing
1438 * the DAC with an analog signal
1439 */
1440 {"HP Right Out", NULL, "DACR"},
1441 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1442
1443 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1444 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1445 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1446
1447 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1448 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1449 {"RCV Right Out", NULL, "LINMOD Mux"},
1450
1451 {"HPL", NULL, "HP Left Out"},
1452 {"HPR", NULL, "HP Right Out"},
1453 {"SPKL", NULL, "SPK Left Out"},
1454 {"SPKR", NULL, "SPK Right Out"},
1455 {"RCVL", NULL, "RCV Left Out"},
1456 {"RCVR", NULL, "RCV Right Out"},
298 1457
299 /* DAC */
300 SND_SOC_DAPM_DAC("DACL", "Hifi Playback", MAX98090_0x3F_OUT_ENABLE, 0, 0),
301 SND_SOC_DAPM_DAC("DACR", "Hifi Playback", MAX98090_0x3F_OUT_ENABLE, 1, 0),
302}; 1458};
303 1459
304static struct snd_soc_dapm_route max98090_audio_map[] = { 1460static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
305 /* Output */ 1461
306 {"HPL", NULL, "HPL Out"}, 1462 /* DMIC inputs */
307 {"HPR", NULL, "HPR Out"}, 1463 {"DMIC3", NULL, "DMIC3_ENA"},
1464 {"DMIC4", NULL, "DMIC4_ENA"},
1465 {"DMIC3", NULL, "AHPF"},
1466 {"DMIC4", NULL, "AHPF"},
1467
1468};
1469
1470static int max98090_add_widgets(struct snd_soc_codec *codec)
1471{
1472 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1473 struct snd_soc_dapm_context *dapm = &codec->dapm;
1474
1475 snd_soc_add_codec_controls(codec, max98090_snd_controls,
1476 ARRAY_SIZE(max98090_snd_controls));
308 1477
309 /* PGA */ 1478 if (max98090->devtype == MAX98091) {
310 {"HPL Out", NULL, "HPL Mixer"}, 1479 snd_soc_add_codec_controls(codec, max98091_snd_controls,
311 {"HPR Out", NULL, "HPR Mixer"}, 1480 ARRAY_SIZE(max98091_snd_controls));
1481 }
1482
1483 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1484 ARRAY_SIZE(max98090_dapm_widgets));
1485
1486 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1487 ARRAY_SIZE(max98090_dapm_routes));
1488
1489 if (max98090->devtype == MAX98091) {
1490 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1491 ARRAY_SIZE(max98091_dapm_widgets));
1492
1493 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1494 ARRAY_SIZE(max98091_dapm_routes));
1495
1496 }
312 1497
313 /* Mixer*/ 1498 return 0;
314 {"HPL Mixer", "DACR Switch", "DACR"}, 1499}
315 {"HPL Mixer", "DACL Switch", "DACL"}, 1500
1501static const int pclk_rates[] = {
1502 12000000, 12000000, 13000000, 13000000,
1503 16000000, 16000000, 19200000, 19200000
1504};
1505
1506static const int lrclk_rates[] = {
1507 8000, 16000, 8000, 16000,
1508 8000, 16000, 8000, 16000
1509};
316 1510
317 {"HPR Mixer", "DACR Switch", "DACR"}, 1511static const int user_pclk_rates[] = {
318 {"HPR Mixer", "DACL Switch", "DACL"}, 1512 13000000, 13000000
319}; 1513};
320 1514
321static bool max98090_volatile(struct device *dev, unsigned int reg) 1515static const int user_lrclk_rates[] = {
1516 44100, 48000
1517};
1518
1519static const unsigned long long ni_value[] = {
1520 3528, 768
1521};
1522
1523static const unsigned long long mi_value[] = {
1524 8125, 1625
1525};
1526
1527static void max98090_configure_bclk(struct snd_soc_codec *codec)
322{ 1528{
323 if ((reg == MAX98090_0x01_INT_STS) || 1529 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
324 (reg == MAX98090_0x02_JACK_STS) || 1530 unsigned long long ni;
325 (reg > MAX98090_REG_MAX_CACHED)) 1531 int i;
326 return true; 1532
1533 if (!max98090->sysclk) {
1534 dev_err(codec->dev, "No SYSCLK configured\n");
1535 return;
1536 }
1537
1538 if (!max98090->bclk || !max98090->lrclk) {
1539 dev_err(codec->dev, "No audio clocks configured\n");
1540 return;
1541 }
1542
1543 /* Skip configuration when operating as slave */
1544 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) &
1545 M98090_MAS_MASK)) {
1546 return;
1547 }
327 1548
328 return false; 1549 /* Check for supported PCLK to LRCLK ratios */
1550 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1551 if ((pclk_rates[i] == max98090->sysclk) &&
1552 (lrclk_rates[i] == max98090->lrclk)) {
1553 dev_dbg(codec->dev,
1554 "Found supported PCLK to LRCLK rates 0x%x\n",
1555 i + 0x8);
1556
1557 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1558 M98090_FREQ_MASK,
1559 (i + 0x8) << M98090_FREQ_SHIFT);
1560 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1561 M98090_USE_M1_MASK, 0);
1562 return;
1563 }
1564 }
1565
1566 /* Check for user calculated MI and NI ratios */
1567 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1568 if ((user_pclk_rates[i] == max98090->sysclk) &&
1569 (user_lrclk_rates[i] == max98090->lrclk)) {
1570 dev_dbg(codec->dev,
1571 "Found user supported PCLK to LRCLK rates\n");
1572 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n",
1573 i, ni_value[i], mi_value[i]);
1574
1575 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1576 M98090_FREQ_MASK, 0);
1577 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1578 M98090_USE_M1_MASK,
1579 1 << M98090_USE_M1_SHIFT);
1580
1581 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1582 (ni_value[i] >> 8) & 0x7F);
1583 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB,
1584 ni_value[i] & 0xFF);
1585 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB,
1586 (mi_value[i] >> 8) & 0x7F);
1587 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB,
1588 mi_value[i] & 0xFF);
1589
1590 return;
1591 }
1592 }
1593
1594 /*
1595 * Calculate based on MI = 65536 (not as good as either method above)
1596 */
1597 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1598 M98090_FREQ_MASK, 0);
1599 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1600 M98090_USE_M1_MASK, 0);
1601
1602 /*
1603 * Configure NI when operating as master
1604 * Note: There is a small, but significant audio quality improvement
1605 * by calculating ni and mi.
1606 */
1607 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1608 * (unsigned long long int)max98090->lrclk;
1609 do_div(ni, (unsigned long long int)max98090->sysclk);
1610 dev_info(codec->dev, "No better method found\n");
1611 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni);
1612 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1613 (ni >> 8) & 0x7F);
1614 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
329} 1615}
330 1616
331static int max98090_dai_hw_params(struct snd_pcm_substream *substream, 1617static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
332 struct snd_pcm_hw_params *params, 1618 unsigned int fmt)
333 struct snd_soc_dai *dai)
334{ 1619{
335 struct snd_soc_codec *codec = dai->codec; 1620 struct snd_soc_codec *codec = codec_dai->codec;
336 unsigned int val; 1621 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1622 struct max98090_cdata *cdata;
1623 u8 regval;
1624
1625 max98090->dai_fmt = fmt;
1626 cdata = &max98090->dai[0];
1627
1628 if (fmt != cdata->fmt) {
1629 cdata->fmt = fmt;
1630
1631 regval = 0;
1632 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1633 case SND_SOC_DAIFMT_CBS_CFS:
1634 /* Set to slave mode PLL - MAS mode off */
1635 snd_soc_write(codec,
1636 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1637 snd_soc_write(codec,
1638 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1639 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1640 M98090_USE_M1_MASK, 0);
1641 break;
1642 case SND_SOC_DAIFMT_CBM_CFM:
1643 /* Set to master mode */
1644 if (max98090->tdm_slots == 4) {
1645 /* TDM */
1646 regval |= M98090_MAS_MASK |
1647 M98090_BSEL_64;
1648 } else if (max98090->tdm_slots == 3) {
1649 /* TDM */
1650 regval |= M98090_MAS_MASK |
1651 M98090_BSEL_48;
1652 } else {
1653 /* Few TDM slots, or No TDM */
1654 regval |= M98090_MAS_MASK |
1655 M98090_BSEL_32;
1656 }
1657 break;
1658 case SND_SOC_DAIFMT_CBS_CFM:
1659 case SND_SOC_DAIFMT_CBM_CFS:
1660 default:
1661 dev_err(codec->dev, "DAI clock mode unsupported");
1662 return -EINVAL;
1663 }
1664 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval);
1665
1666 regval = 0;
1667 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1668 case SND_SOC_DAIFMT_I2S:
1669 regval |= M98090_DLY_MASK;
1670 break;
1671 case SND_SOC_DAIFMT_LEFT_J:
1672 break;
1673 case SND_SOC_DAIFMT_RIGHT_J:
1674 regval |= M98090_RJ_MASK;
1675 break;
1676 case SND_SOC_DAIFMT_DSP_A:
1677 /* Not supported mode */
1678 default:
1679 dev_err(codec->dev, "DAI format unsupported");
1680 return -EINVAL;
1681 }
1682
1683 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1684 case SND_SOC_DAIFMT_NB_NF:
1685 break;
1686 case SND_SOC_DAIFMT_NB_IF:
1687 regval |= M98090_WCI_MASK;
1688 break;
1689 case SND_SOC_DAIFMT_IB_NF:
1690 regval |= M98090_BCI_MASK;
1691 break;
1692 case SND_SOC_DAIFMT_IB_IF:
1693 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1694 break;
1695 default:
1696 dev_err(codec->dev, "DAI invert mode unsupported");
1697 return -EINVAL;
1698 }
1699
1700 /*
1701 * This accommodates an inverted logic in the MAX98090 chip
1702 * for Bit Clock Invert (BCI). The inverted logic is only
1703 * seen for the case of TDM mode. The remaining cases have
1704 * normal logic.
1705 */
1706 if (max98090->tdm_slots > 1) {
1707 regval ^= M98090_BCI_MASK;
1708 }
1709
1710 snd_soc_write(codec,
1711 M98090_REG_INTERFACE_FORMAT, regval);
1712 }
337 1713
338 switch (params_rate(params)) { 1714 return 0;
339 case 96000: 1715}
340 val = 1 << 5; 1716
341 break; 1717static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
342 case 32000: 1718 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
343 val = 1 << 4; 1719{
344 break; 1720 struct snd_soc_codec *codec = codec_dai->codec;
345 case 48000: 1721 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
346 val = 1 << 3; 1722 struct max98090_cdata *cdata;
1723 cdata = &max98090->dai[0];
1724
1725 if (slots < 0 || slots > 4)
1726 return -EINVAL;
1727
1728 max98090->tdm_slots = slots;
1729 max98090->tdm_width = slot_width;
1730
1731 if (max98090->tdm_slots > 1) {
1732 /* SLOTL SLOTR SLOTDLY */
1733 snd_soc_write(codec, M98090_REG_TDM_FORMAT,
1734 0 << M98090_TDM_SLOTL_SHIFT |
1735 1 << M98090_TDM_SLOTR_SHIFT |
1736 0 << M98090_TDM_SLOTDLY_SHIFT);
1737
1738 /* FSW TDM */
1739 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL,
1740 M98090_TDM_MASK,
1741 M98090_TDM_MASK);
1742 }
1743
1744 /*
1745 * Normally advisable to set TDM first, but this permits either order
1746 */
1747 cdata->fmt = 0;
1748 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1749
1750 return 0;
1751}
1752
1753static int max98090_set_bias_level(struct snd_soc_codec *codec,
1754 enum snd_soc_bias_level level)
1755{
1756 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1757 int ret;
1758
1759 switch (level) {
1760 case SND_SOC_BIAS_ON:
1761 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1762 ret = regcache_sync(max98090->regmap);
1763
1764 if (ret != 0) {
1765 dev_err(codec->dev,
1766 "Failed to sync cache: %d\n", ret);
1767 return ret;
1768 }
1769 }
1770
1771 if (max98090->jack_state == M98090_JACK_STATE_HEADSET) {
1772 /*
1773 * Set to normal bias level.
1774 */
1775 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
1776 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8);
1777 }
347 break; 1778 break;
348 case 44100: 1779
349 val = 1 << 2; 1780 case SND_SOC_BIAS_PREPARE:
350 break; 1781 break;
351 case 16000: 1782
352 val = 1 << 1; 1783 case SND_SOC_BIAS_STANDBY:
1784 case SND_SOC_BIAS_OFF:
1785 /* Set internal pull-up to lowest power mode */
1786 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1787 M98090_JDWK_MASK, M98090_JDWK_MASK);
1788 regcache_mark_dirty(max98090->regmap);
353 break; 1789 break;
354 case 8000: 1790 }
355 val = 1 << 0; 1791 codec->dapm.bias_level = level;
1792 return 0;
1793}
1794
1795static const int comp_pclk_rates[] = {
1796 11289600, 12288000, 12000000, 13000000, 19200000
1797};
1798
1799static const int dmic_micclk[] = {
1800 2, 2, 2, 2, 4, 2
1801};
1802
1803static const int comp_lrclk_rates[] = {
1804 8000, 16000, 32000, 44100, 48000, 96000
1805};
1806
1807static const int dmic_comp[6][6] = {
1808 {7, 8, 3, 3, 3, 3},
1809 {7, 8, 3, 3, 3, 3},
1810 {7, 8, 3, 3, 3, 3},
1811 {7, 8, 3, 1, 1, 1},
1812 {7, 8, 3, 1, 2, 2},
1813 {7, 8, 3, 3, 3, 3}
1814};
1815
1816static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1817 struct snd_pcm_hw_params *params,
1818 struct snd_soc_dai *dai)
1819{
1820 struct snd_soc_codec *codec = dai->codec;
1821 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1822 struct max98090_cdata *cdata;
1823 int i, j;
1824
1825 cdata = &max98090->dai[0];
1826 max98090->bclk = snd_soc_params_to_bclk(params);
1827 if (params_channels(params) == 1)
1828 max98090->bclk *= 2;
1829
1830 max98090->lrclk = params_rate(params);
1831
1832 switch (params_format(params)) {
1833 case SNDRV_PCM_FORMAT_S16_LE:
1834 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT,
1835 M98090_WS_MASK, 0);
356 break; 1836 break;
357 default: 1837 default:
358 dev_err(codec->dev, "unsupported rate\n");
359 return -EINVAL; 1838 return -EINVAL;
360 } 1839 }
361 snd_soc_update_bits(codec, MAX98090_0x05_SAMPLE_RATE, 0x03F, val); 1840
1841 max98090_configure_bclk(codec);
1842
1843 cdata->rate = max98090->lrclk;
1844
1845 /* Update filter mode */
1846 if (max98090->lrclk < 24000)
1847 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1848 M98090_MODE_MASK, 0);
1849 else
1850 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1851 M98090_MODE_MASK, M98090_MODE_MASK);
1852
1853 /* Update sample rate mode */
1854 if (max98090->lrclk < 50000)
1855 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1856 M98090_DHF_MASK, 0);
1857 else
1858 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1859 M98090_DHF_MASK, M98090_DHF_MASK);
1860
1861 /* Check for supported PCLK to LRCLK ratios */
1862 for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) {
1863 if (comp_pclk_rates[j] == max98090->sysclk) {
1864 break;
1865 }
1866 }
1867
1868 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1869 if (max98090->lrclk <= (comp_lrclk_rates[i] +
1870 comp_lrclk_rates[i + 1]) / 2) {
1871 break;
1872 }
1873 }
1874
1875 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE,
1876 M98090_MICCLK_MASK,
1877 dmic_micclk[j] << M98090_MICCLK_SHIFT);
1878
1879 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG,
1880 M98090_DMIC_COMP_MASK,
1881 dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT);
362 1882
363 return 0; 1883 return 0;
364} 1884}
365 1885
1886/*
1887 * PLL / Sysclk
1888 */
366static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, 1889static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
367 int clk_id, unsigned int freq, int dir) 1890 int clk_id, unsigned int freq, int dir)
368{ 1891{
369 struct snd_soc_codec *codec = dai->codec; 1892 struct snd_soc_codec *codec = dai->codec;
370 unsigned int val; 1893 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
371 1894
372 snd_soc_update_bits(codec, MAX98090_0x45_DEV_SHUTDOWN, 1895 /* Requested clock frequency is already setup */
373 MAX98090_SHDNRUN, 0); 1896 if (freq == max98090->sysclk)
374 1897 return 0;
375 switch (freq) { 1898
376 case 26000000: 1899 /* Setup clocks for slave mode, and using the PLL
377 val = 1 << 7; 1900 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
378 break; 1901 * 0x02 (when master clk is 20MHz to 40MHz)..
379 case 19200000: 1902 * 0x03 (when master clk is 40MHz to 60MHz)..
380 val = 1 << 6; 1903 */
381 break; 1904 if ((freq >= 10000000) && (freq < 20000000)) {
382 case 13000000: 1905 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
383 val = 1 << 5; 1906 M98090_PSCLK_DIV1);
384 break; 1907 } else if ((freq >= 20000000) && (freq < 40000000)) {
385 case 12288000: 1908 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
386 val = 1 << 4; 1909 M98090_PSCLK_DIV2);
387 break; 1910 } else if ((freq >= 40000000) && (freq < 60000000)) {
388 case 12000000: 1911 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
389 val = 1 << 3; 1912 M98090_PSCLK_DIV4);
390 break; 1913 } else {
391 case 11289600:
392 val = 1 << 2;
393 break;
394 default:
395 dev_err(codec->dev, "Invalid master clock frequency\n"); 1914 dev_err(codec->dev, "Invalid master clock frequency\n");
396 return -EINVAL; 1915 return -EINVAL;
397 } 1916 }
398 snd_soc_update_bits(codec, MAX98090_0x04_SYS_CLK, 0xFD, val);
399 1917
400 snd_soc_update_bits(codec, MAX98090_0x45_DEV_SHUTDOWN, 1918 max98090->sysclk = freq;
401 MAX98090_SHDNRUN, MAX98090_SHDNRUN);
402 1919
403 dev_dbg(dai->dev, "sysclk is %uHz\n", freq); 1920 max98090_configure_bclk(codec);
404 1921
405 return 0; 1922 return 0;
406} 1923}
407 1924
408static int max98090_dai_set_fmt(struct snd_soc_dai *dai, 1925static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
409 unsigned int fmt)
410{ 1926{
411 struct snd_soc_codec *codec = dai->codec; 1927 struct snd_soc_codec *codec = codec_dai->codec;
412 int is_master; 1928 int regval;
413 u8 val;
414 1929
415 /* master/slave mode */ 1930 regval = mute ? M98090_DVM_MASK : 0;
416 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1931 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL,
417 case SND_SOC_DAIFMT_CBM_CFM: 1932 M98090_DVM_MASK, regval);
418 is_master = 1; 1933
419 break; 1934 return 0;
420 case SND_SOC_DAIFMT_CBS_CFS: 1935}
421 is_master = 0; 1936
422 break; 1937static void max98090_jack_work(struct work_struct *work)
423 default: 1938{
424 dev_err(codec->dev, "unsupported clock\n"); 1939 struct max98090_priv *max98090 = container_of(work,
425 return -EINVAL; 1940 struct max98090_priv,
1941 jack_work.work);
1942 struct snd_soc_codec *codec = max98090->codec;
1943 struct snd_soc_dapm_context *dapm = &codec->dapm;
1944 int status = 0;
1945 int reg;
1946
1947 /* Read a second time */
1948 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
1949
1950 /* Strong pull up allows mic detection */
1951 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1952 M98090_JDWK_MASK, 0);
1953
1954 msleep(50);
1955
1956 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1957
1958 /* Weak pull up allows only insertion detection */
1959 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1960 M98090_JDWK_MASK, M98090_JDWK_MASK);
1961 } else {
1962 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
426 } 1963 }
427 1964
428 /* format */ 1965 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
429 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1966
430 case SND_SOC_DAIFMT_I2S: 1967 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
431 val = (is_master) ? MAX98090_I2S_M : MAX98090_I2S_S; 1968 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
432 break; 1969 dev_dbg(codec->dev, "No Headset Detected\n");
433 case SND_SOC_DAIFMT_RIGHT_J: 1970
434 val = (is_master) ? MAX98090_RJ_M : MAX98090_RJ_S; 1971 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
435 break; 1972
436 case SND_SOC_DAIFMT_LEFT_J: 1973 status |= 0;
437 val = (is_master) ? MAX98090_LJ_M : MAX98090_LJ_S; 1974
438 break; 1975 break;
439 default: 1976
440 dev_err(codec->dev, "unsupported format\n"); 1977 case 0:
441 return -EINVAL; 1978 if (max98090->jack_state ==
1979 M98090_JACK_STATE_HEADSET) {
1980
1981 dev_dbg(codec->dev,
1982 "Headset Button Down Detected\n");
1983
1984 /*
1985 * max98090_headset_button_event(codec)
1986 * could be defined, then called here.
1987 */
1988
1989 status |= SND_JACK_HEADSET;
1990 status |= SND_JACK_BTN_0;
1991
1992 break;
1993 }
1994
1995 /* Line is reported as Headphone */
1996 /* Nokia Headset is reported as Headphone */
1997 /* Mono Headphone is reported as Headphone */
1998 dev_dbg(codec->dev, "Headphone Detected\n");
1999
2000 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2001
2002 status |= SND_JACK_HEADPHONE;
2003
2004 break;
2005
2006 case M98090_JKSNS_MASK:
2007 dev_dbg(codec->dev, "Headset Detected\n");
2008
2009 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2010
2011 status |= SND_JACK_HEADSET;
2012
2013 break;
2014
2015 default:
2016 dev_dbg(codec->dev, "Unrecognized Jack Status\n");
2017 break;
2018 }
2019
2020 snd_soc_jack_report(max98090->jack, status,
2021 SND_JACK_HEADSET | SND_JACK_BTN_0);
2022
2023 snd_soc_dapm_sync(dapm);
2024}
2025
2026static irqreturn_t max98090_interrupt(int irq, void *data)
2027{
2028 struct snd_soc_codec *codec = data;
2029 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2030 int ret;
2031 unsigned int mask;
2032 unsigned int active;
2033
2034 dev_dbg(codec->dev, "***** max98090_interrupt *****\n");
2035
2036 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2037
2038 if (ret != 0) {
2039 dev_err(codec->dev,
2040 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2041 ret);
2042 return IRQ_NONE;
2043 }
2044
2045 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2046
2047 if (ret != 0) {
2048 dev_err(codec->dev,
2049 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2050 ret);
2051 return IRQ_NONE;
2052 }
2053
2054 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2055 active, mask, active & mask);
2056
2057 active &= mask;
2058
2059 if (!active)
2060 return IRQ_NONE;
2061
2062 if (active & M98090_CLD_MASK) {
2063 dev_err(codec->dev, "M98090_CLD_MASK\n");
2064 }
2065
2066 if (active & M98090_SLD_MASK) {
2067 dev_dbg(codec->dev, "M98090_SLD_MASK\n");
442 } 2068 }
443 snd_soc_update_bits(codec, MAX98090_0x06_DAI_IF, 2069
444 MAX98090_DAI_IF_MASK, val); 2070 if (active & M98090_ULK_MASK) {
2071 dev_err(codec->dev, "M98090_ULK_MASK\n");
2072 }
2073
2074 if (active & M98090_JDET_MASK) {
2075 dev_dbg(codec->dev, "M98090_JDET_MASK\n");
2076
2077 pm_wakeup_event(codec->dev, 100);
2078
2079 schedule_delayed_work(&max98090->jack_work,
2080 msecs_to_jiffies(100));
2081 }
2082
2083 if (active & M98090_DRCACT_MASK) {
2084 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n");
2085 }
2086
2087 if (active & M98090_DRCCLP_MASK) {
2088 dev_err(codec->dev, "M98090_DRCCLP_MASK\n");
2089 }
2090
2091 return IRQ_HANDLED;
2092}
2093
2094/**
2095 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2096 *
2097 * @codec: MAX98090 codec
2098 * @jack: jack to report detection events on
2099 *
2100 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2101 * being used to bring out signals to the processor then only platform
2102 * data configuration is needed for MAX98090 and processor GPIOs should
2103 * be configured using snd_soc_jack_add_gpios() instead.
2104 *
2105 * If no jack is supplied detection will be disabled.
2106 */
2107int max98090_mic_detect(struct snd_soc_codec *codec,
2108 struct snd_soc_jack *jack)
2109{
2110 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2111
2112 dev_dbg(codec->dev, "max98090_mic_detect\n");
2113
2114 max98090->jack = jack;
2115 if (jack) {
2116 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2117 M98090_IJDET_MASK,
2118 1 << M98090_IJDET_SHIFT);
2119 } else {
2120 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2121 M98090_IJDET_MASK,
2122 0);
2123 }
2124
2125 /* Send an initial empty report */
2126 snd_soc_jack_report(max98090->jack, 0,
2127 SND_JACK_HEADSET | SND_JACK_BTN_0);
2128
2129 schedule_delayed_work(&max98090->jack_work,
2130 msecs_to_jiffies(100));
445 2131
446 return 0; 2132 return 0;
447} 2133}
2134EXPORT_SYMBOL_GPL(max98090_mic_detect);
448 2135
449#define MAX98090_RATES SNDRV_PCM_RATE_8000_96000 2136#define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
450#define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 2137#define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
451 2138
452static struct snd_soc_dai_ops max98090_dai_ops = { 2139static struct snd_soc_dai_ops max98090_dai_ops = {
453 .set_sysclk = max98090_dai_set_sysclk, 2140 .set_sysclk = max98090_dai_set_sysclk,
454 .set_fmt = max98090_dai_set_fmt, 2141 .set_fmt = max98090_dai_set_fmt,
455 .hw_params = max98090_dai_hw_params, 2142 .set_tdm_slot = max98090_set_tdm_slot,
2143 .hw_params = max98090_dai_hw_params,
2144 .digital_mute = max98090_dai_digital_mute,
456}; 2145};
457 2146
458static struct snd_soc_dai_driver max98090_dai = { 2147static struct snd_soc_dai_driver max98090_dai[] = {
459 .name = "max98090-Hifi", 2148{
2149 .name = "HiFi",
460 .playback = { 2150 .playback = {
461 .stream_name = "Playback", 2151 .stream_name = "HiFi Playback",
462 .channels_min = 1, 2152 .channels_min = 2,
463 .channels_max = 2, 2153 .channels_max = 2,
464 .rates = MAX98090_RATES, 2154 .rates = MAX98090_RATES,
465 .formats = MAX98090_FORMATS, 2155 .formats = MAX98090_FORMATS,
2156 },
2157 .capture = {
2158 .stream_name = "HiFi Capture",
2159 .channels_min = 1,
2160 .channels_max = 2,
2161 .rates = MAX98090_RATES,
2162 .formats = MAX98090_FORMATS,
466 }, 2163 },
467 .ops = &max98090_dai_ops, 2164 .ops = &max98090_dai_ops,
2165}
468}; 2166};
469 2167
2168static void max98090_handle_pdata(struct snd_soc_codec *codec)
2169{
2170 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2171 struct max98090_pdata *pdata = max98090->pdata;
2172
2173 if (!pdata) {
2174 dev_err(codec->dev, "No platform data\n");
2175 return;
2176 }
2177
2178}
2179
470static int max98090_probe(struct snd_soc_codec *codec) 2180static int max98090_probe(struct snd_soc_codec *codec)
471{ 2181{
472 struct max98090_priv *priv = snd_soc_codec_get_drvdata(codec); 2182 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
473 struct device *dev = codec->dev; 2183 struct max98090_cdata *cdata;
474 int ret; 2184 int ret = 0;
2185
2186 dev_dbg(codec->dev, "max98090_probe\n");
2187
2188 max98090->codec = codec;
2189
2190 codec->control_data = max98090->regmap;
475 2191
476 codec->control_data = priv->regmap;
477 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP); 2192 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
478 if (ret < 0) { 2193 if (ret != 0) {
479 dev_err(dev, "Failed to set cache I/O: %d\n", ret); 2194 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
480 return ret; 2195 return ret;
481 } 2196 }
482 2197
483 /* Device active */ 2198 /* Reset the codec, the DSP core, and disable all interrupts */
484 snd_soc_update_bits(codec, MAX98090_0x45_DEV_SHUTDOWN, 2199 max98090_reset(max98090);
485 MAX98090_SHDNRUN, MAX98090_SHDNRUN);
486 2200
487 return 0; 2201 /* Initialize private data */
2202
2203 max98090->sysclk = (unsigned)-1;
2204
2205 cdata = &max98090->dai[0];
2206 cdata->rate = (unsigned)-1;
2207 cdata->fmt = (unsigned)-1;
2208
2209 max98090->lin_state = 0;
2210 max98090->pa1en = 0;
2211 max98090->pa2en = 0;
2212 max98090->extmic_mux = 0;
2213
2214 ret = snd_soc_read(codec, M98090_REG_REVISION_ID);
2215 if (ret < 0) {
2216 dev_err(codec->dev, "Failed to read device revision: %d\n",
2217 ret);
2218 goto err_access;
2219 }
2220
2221 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2222 max98090->devtype = MAX98090;
2223 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret);
2224 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2225 max98090->devtype = MAX98091;
2226 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret);
2227 } else {
2228 max98090->devtype = MAX98090;
2229 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret);
2230 }
2231
2232 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2233
2234 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2235
2236 /* Enable jack detection */
2237 snd_soc_write(codec, M98090_REG_JACK_DETECT,
2238 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2239
2240 /* Register for interrupts */
2241 dev_dbg(codec->dev, "irq = %d\n", max98090->irq);
2242
2243 ret = request_threaded_irq(max98090->irq, NULL,
2244 max98090_interrupt, IRQF_TRIGGER_FALLING,
2245 "max98090_interrupt", codec);
2246 if (ret < 0) {
2247 dev_err(codec->dev, "request_irq failed: %d\n",
2248 ret);
2249 }
2250
2251 /*
2252 * Clear any old interrupts.
2253 * An old interrupt ocurring prior to installing the ISR
2254 * can keep a new interrupt from generating a trigger.
2255 */
2256 snd_soc_read(codec, M98090_REG_DEVICE_STATUS);
2257
2258 /* High Performance is default */
2259 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2260 M98090_DACHP_MASK,
2261 1 << M98090_DACHP_SHIFT);
2262 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2263 M98090_PERFMODE_MASK,
2264 0 << M98090_PERFMODE_SHIFT);
2265 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL,
2266 M98090_ADCHP_MASK,
2267 1 << M98090_ADCHP_SHIFT);
2268
2269 /* Turn on VCM bandgap reference */
2270 snd_soc_write(codec, M98090_REG_BIAS_CONTROL,
2271 M98090_VCM_MODE_MASK);
2272
2273 max98090_handle_pdata(codec);
2274
2275 max98090_add_widgets(codec);
2276
2277err_access:
2278 return ret;
488} 2279}
489 2280
490static int max98090_remove(struct snd_soc_codec *codec) 2281static int max98090_remove(struct snd_soc_codec *codec)
491{ 2282{
2283 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2284
2285 cancel_delayed_work_sync(&max98090->jack_work);
2286
492 return 0; 2287 return 0;
493} 2288}
494 2289
495static struct snd_soc_codec_driver soc_codec_dev_max98090 = { 2290static struct snd_soc_codec_driver soc_codec_dev_max98090 = {
496 .probe = max98090_probe, 2291 .probe = max98090_probe,
497 .remove = max98090_remove, 2292 .remove = max98090_remove,
498 .controls = max98090_snd_controls, 2293 .set_bias_level = max98090_set_bias_level,
499 .num_controls = ARRAY_SIZE(max98090_snd_controls),
500 .dapm_widgets = max98090_dapm_widgets,
501 .num_dapm_widgets = ARRAY_SIZE(max98090_dapm_widgets),
502 .dapm_routes = max98090_audio_map,
503 .num_dapm_routes = ARRAY_SIZE(max98090_audio_map),
504}; 2294};
505 2295
506static const struct regmap_config max98090_regmap = { 2296static const struct regmap_config max98090_regmap = {
507 .reg_bits = 8, 2297 .reg_bits = 8,
508 .val_bits = 8, 2298 .val_bits = 8,
509 .max_register = MAX98090_REG_END, 2299
510 .volatile_reg = max98090_volatile, 2300 .max_register = MAX98090_MAX_REGISTER,
511 .cache_type = REGCACHE_RBTREE, 2301 .reg_defaults = max98090_reg,
512 .reg_defaults = max98090_reg_defaults, 2302 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
513 .num_reg_defaults = ARRAY_SIZE(max98090_reg_defaults), 2303 .volatile_reg = max98090_volatile_register,
2304 .readable_reg = max98090_readable_register,
2305 .cache_type = REGCACHE_RBTREE,
514}; 2306};
515 2307
516static int max98090_i2c_probe(struct i2c_client *i2c, 2308static int max98090_i2c_probe(struct i2c_client *i2c,
517 const struct i2c_device_id *id) 2309 const struct i2c_device_id *id)
518{ 2310{
519 struct max98090_priv *priv; 2311 struct max98090_priv *max98090;
520 struct device *dev = &i2c->dev;
521 unsigned int val;
522 int ret; 2312 int ret;
523 2313
524 priv = devm_kzalloc(dev, sizeof(struct max98090_priv), 2314 pr_debug("max98090_i2c_probe\n");
525 GFP_KERNEL);
526 if (!priv)
527 return -ENOMEM;
528
529 priv->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
530 if (IS_ERR(priv->regmap)) {
531 ret = PTR_ERR(priv->regmap);
532 dev_err(dev, "Failed to init regmap: %d\n", ret);
533 return ret;
534 }
535 2315
536 i2c_set_clientdata(i2c, priv); 2316 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2317 GFP_KERNEL);
2318 if (max98090 == NULL)
2319 return -ENOMEM;
537 2320
538 ret = regmap_read(priv->regmap, MAX98090_0xFF_REV_ID, &val); 2321 max98090->devtype = id->driver_data;
539 if (ret < 0) { 2322 i2c_set_clientdata(i2c, max98090);
540 dev_err(dev, "Failed to read device revision: %d\n", ret); 2323 max98090->control_data = i2c;
541 return ret; 2324 max98090->pdata = i2c->dev.platform_data;
2325 max98090->irq = i2c->irq;
2326
2327 max98090->regmap = regmap_init_i2c(i2c, &max98090_regmap);
2328 if (IS_ERR(max98090->regmap)) {
2329 ret = PTR_ERR(max98090->regmap);
2330 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2331 goto err_enable;
542 } 2332 }
543 dev_info(dev, "revision 0x%02x\n", val);
544 2333
545 ret = snd_soc_register_codec(dev, 2334 ret = snd_soc_register_codec(&i2c->dev,
546 &soc_codec_dev_max98090, 2335 &soc_codec_dev_max98090, max98090_dai,
547 &max98090_dai, 1); 2336 ARRAY_SIZE(max98090_dai));
2337 if (ret < 0)
2338 regmap_exit(max98090->regmap);
548 2339
2340err_enable:
549 return ret; 2341 return ret;
550} 2342}
551 2343
552static int max98090_i2c_remove(struct i2c_client *client) 2344static int max98090_i2c_remove(struct i2c_client *client)
553{ 2345{
2346 struct max98090_priv *max98090 = dev_get_drvdata(&client->dev);
554 snd_soc_unregister_codec(&client->dev); 2347 snd_soc_unregister_codec(&client->dev);
2348 regmap_exit(max98090->regmap);
2349 return 0;
2350}
2351
2352static int max98090_runtime_resume(struct device *dev)
2353{
2354 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2355
2356 regcache_cache_only(max98090->regmap, false);
2357
2358 regcache_sync(max98090->regmap);
2359
555 return 0; 2360 return 0;
556} 2361}
557 2362
2363static int max98090_runtime_suspend(struct device *dev)
2364{
2365 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2366
2367 regcache_cache_only(max98090->regmap, true);
2368
2369 return 0;
2370}
2371
2372static struct dev_pm_ops max98090_pm = {
2373 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2374 max98090_runtime_resume, NULL)
2375};
2376
558static const struct i2c_device_id max98090_i2c_id[] = { 2377static const struct i2c_device_id max98090_i2c_id[] = {
559 { "max98090", 0 }, 2378 { "max98090", MAX98090 },
560 { } 2379 { }
561}; 2380};
562MODULE_DEVICE_TABLE(i2c, max98090_i2c_id); 2381MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
@@ -565,13 +2384,15 @@ static struct i2c_driver max98090_i2c_driver = {
565 .driver = { 2384 .driver = {
566 .name = "max98090", 2385 .name = "max98090",
567 .owner = THIS_MODULE, 2386 .owner = THIS_MODULE,
2387 .pm = &max98090_pm,
568 }, 2388 },
569 .probe = max98090_i2c_probe, 2389 .probe = max98090_i2c_probe,
570 .remove = max98090_i2c_remove, 2390 .remove = max98090_i2c_remove,
571 .id_table = max98090_i2c_id, 2391 .id_table = max98090_i2c_id,
572}; 2392};
2393
573module_i2c_driver(max98090_i2c_driver); 2394module_i2c_driver(max98090_i2c_driver);
574 2395
575MODULE_DESCRIPTION("ALSA SoC MAX98090 driver"); 2396MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
576MODULE_AUTHOR("Peter Hsiang, Kuninori Morimoto"); 2397MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
577MODULE_LICENSE("GPL"); 2398MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/max98090.h b/sound/soc/codecs/max98090.h
new file mode 100755
index 000000000000..7e103f249053
--- /dev/null
+++ b/sound/soc/codecs/max98090.h
@@ -0,0 +1,1549 @@
1/*
2 * max98090.h -- MAX98090 ALSA SoC Audio driver
3 *
4 * Copyright 2011-2012 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef _MAX98090_H
12#define _MAX98090_H
13
14#include <linux/version.h>
15
16/* One can override the Linux version here with an explicit version number */
17#define M98090_LINUX_VERSION LINUX_VERSION_CODE
18
19/*
20 * MAX98090 Register Definitions
21 */
22
23#define M98090_REG_SOFTWARE_RESET 0x00
24#define M98090_REG_DEVICE_STATUS 0x01
25#define M98090_REG_JACK_STATUS 0x02
26#define M98090_REG_INTERRUPT_S 0x03
27#define M98090_REG_QUICK_SYSTEM_CLOCK 0x04
28#define M98090_REG_QUICK_SAMPLE_RATE 0x05
29#define M98090_REG_DAI_INTERFACE 0x06
30#define M98090_REG_DAC_PATH 0x07
31#define M98090_REG_MIC_DIRECT_TO_ADC 0x08
32#define M98090_REG_LINE_TO_ADC 0x09
33#define M98090_REG_ANALOG_MIC_LOOP 0x0A
34#define M98090_REG_ANALOG_LINE_LOOP 0x0B
35#define M98090_REG_RESERVED 0x0C
36#define M98090_REG_LINE_INPUT_CONFIG 0x0D
37#define M98090_REG_LINE_INPUT_LEVEL 0x0E
38#define M98090_REG_INPUT_MODE 0x0F
39#define M98090_REG_MIC1_INPUT_LEVEL 0x10
40#define M98090_REG_MIC2_INPUT_LEVEL 0x11
41#define M98090_REG_MIC_BIAS_VOLTAGE 0x12
42#define M98090_REG_DIGITAL_MIC_ENABLE 0x13
43#define M98090_REG_DIGITAL_MIC_CONFIG 0x14
44#define M98090_REG_LEFT_ADC_MIXER 0x15
45#define M98090_REG_RIGHT_ADC_MIXER 0x16
46#define M98090_REG_LEFT_ADC_LEVEL 0x17
47#define M98090_REG_RIGHT_ADC_LEVEL 0x18
48#define M98090_REG_ADC_BIQUAD_LEVEL 0x19
49#define M98090_REG_ADC_SIDETONE 0x1A
50#define M98090_REG_SYSTEM_CLOCK 0x1B
51#define M98090_REG_CLOCK_MODE 0x1C
52#define M98090_REG_CLOCK_RATIO_NI_MSB 0x1D
53#define M98090_REG_CLOCK_RATIO_NI_LSB 0x1E
54#define M98090_REG_CLOCK_RATIO_MI_MSB 0x1F
55#define M98090_REG_CLOCK_RATIO_MI_LSB 0x20
56#define M98090_REG_MASTER_MODE 0x21
57#define M98090_REG_INTERFACE_FORMAT 0x22
58#define M98090_REG_TDM_CONTROL 0x23
59#define M98090_REG_TDM_FORMAT 0x24
60#define M98090_REG_IO_CONFIGURATION 0x25
61#define M98090_REG_FILTER_CONFIG 0x26
62#define M98090_REG_DAI_PLAYBACK_LEVEL 0x27
63#define M98090_REG_DAI_PLAYBACK_LEVEL_EQ 0x28
64#define M98090_REG_LEFT_HP_MIXER 0x29
65#define M98090_REG_RIGHT_HP_MIXER 0x2A
66#define M98090_REG_HP_CONTROL 0x2B
67#define M98090_REG_LEFT_HP_VOLUME 0x2C
68#define M98090_REG_RIGHT_HP_VOLUME 0x2D
69#define M98090_REG_LEFT_SPK_MIXER 0x2E
70#define M98090_REG_RIGHT_SPK_MIXER 0x2F
71#define M98090_REG_SPK_CONTROL 0x30
72#define M98090_REG_LEFT_SPK_VOLUME 0x31
73#define M98090_REG_RIGHT_SPK_VOLUME 0x32
74#define M98090_REG_DRC_TIMING 0x33
75#define M98090_REG_DRC_COMPRESSOR 0x34
76#define M98090_REG_DRC_EXPANDER 0x35
77#define M98090_REG_DRC_GAIN 0x36
78#define M98090_REG_RCV_LOUTL_MIXER 0x37
79#define M98090_REG_RCV_LOUTL_CONTROL 0x38
80#define M98090_REG_RCV_LOUTL_VOLUME 0x39
81#define M98090_REG_LOUTR_MIXER 0x3A
82#define M98090_REG_LOUTR_CONTROL 0x3B
83#define M98090_REG_LOUTR_VOLUME 0x3C
84#define M98090_REG_JACK_DETECT 0x3D
85#define M98090_REG_INPUT_ENABLE 0x3E
86#define M98090_REG_OUTPUT_ENABLE 0x3F
87#define M98090_REG_LEVEL_CONTROL 0x40
88#define M98090_REG_DSP_FILTER_ENABLE 0x41
89#define M98090_REG_BIAS_CONTROL 0x42
90#define M98090_REG_DAC_CONTROL 0x43
91#define M98090_REG_ADC_CONTROL 0x44
92#define M98090_REG_DEVICE_SHUTDOWN 0x45
93#define M98090_REG_EQUALIZER_BASE 0x46
94#define M98090_REG_RECORD_BIQUAD_BASE 0xAF
95#define M98090_REG_DMIC3_VOLUME 0xBE
96#define M98090_REG_DMIC4_VOLUME 0xBF
97#define M98090_REG_DMIC34_BQ_PREATTEN 0xC0
98#define M98090_REG_RECORD_TDM_SLOT 0xC1
99#define M98090_REG_SAMPLE_RATE 0xC2
100#define M98090_REG_DMIC34_BIQUAD_BASE 0xC3
101#define M98090_REG_REVISION_ID 0xFF
102
103#define M98090_REG_CNT (0xFF+1)
104#define MAX98090_MAX_REGISTER 0xFF
105
106/* MAX98090 Register Bit Fields */
107
108/*
109 * M98090_REG_SOFTWARE_RESET
110 */
111#define M98090_SWRESET_MASK (1<<7)
112#define M98090_SWRESET_SHIFT 7
113#define M98090_SWRESET_WIDTH 1
114
115/*
116 * M98090_REG_DEVICE_STATUS
117 */
118#define M98090_CLD_MASK (1<<7)
119#define M98090_CLD_SHIFT 7
120#define M98090_CLD_WIDTH 1
121#define M98090_SLD_MASK (1<<6)
122#define M98090_SLD_SHIFT 6
123#define M98090_SLD_WIDTH 1
124#define M98090_ULK_MASK (1<<5)
125#define M98090_ULK_SHIFT 5
126#define M98090_ULK_WIDTH 1
127#define M98090_JDET_MASK (1<<2)
128#define M98090_JDET_SHIFT 2
129#define M98090_JDET_WIDTH 1
130#define M98090_DRCACT_MASK (1<<1)
131#define M98090_DRCACT_SHIFT 1
132#define M98090_DRCACT_WIDTH 1
133#define M98090_DRCCLP_MASK (1<<0)
134#define M98090_DRCCLP_SHIFT 0
135#define M98090_DRCCLP_WIDTH 1
136
137/*
138 * M98090_REG_JACK_STATUS
139 */
140#define M98090_LSNS_MASK (1<<2)
141#define M98090_LSNS_SHIFT 2
142#define M98090_LSNS_WIDTH 1
143#define M98090_JKSNS_MASK (1<<1)
144#define M98090_JKSNS_SHIFT 1
145#define M98090_JKSNS_WIDTH 1
146
147/*
148 * M98090_REG_INTERRUPT_S
149 */
150#define M98090_ICLD_MASK (1<<7)
151#define M98090_ICLD_SHIFT 7
152#define M98090_ICLD_WIDTH 1
153#define M98090_ISLD_MASK (1<<6)
154#define M98090_ISLD_SHIFT 6
155#define M98090_ISLD_WIDTH 1
156#define M98090_IULK_MASK (1<<5)
157#define M98090_IULK_SHIFT 5
158#define M98090_IULK_WIDTH 1
159#define M98090_IJDET_MASK (1<<2)
160#define M98090_IJDET_SHIFT 2
161#define M98090_IJDET_WIDTH 1
162#define M98090_IDRCACT_MASK (1<<1)
163#define M98090_IDRCACT_SHIFT 1
164#define M98090_IDRCACT_WIDTH 1
165#define M98090_IDRCCLP_MASK (1<<0)
166#define M98090_IDRCCLP_SHIFT 0
167#define M98090_IDRCCLP_WIDTH 1
168
169/*
170 * M98090_REG_QUICK_SYSTEM_CLOCK
171 */
172#define M98090_26M_MASK (1<<7)
173#define M98090_26M_SHIFT 7
174#define M98090_26M_WIDTH 1
175#define M98090_19P2M_MASK (1<<6)
176#define M98090_19P2M_SHIFT 6
177#define M98090_19P2M_WIDTH 1
178#define M98090_13M_MASK (1<<5)
179#define M98090_13M_SHIFT 5
180#define M98090_13M_WIDTH 1
181#define M98090_12P288M_MASK (1<<4)
182#define M98090_12P288M_SHIFT 4
183#define M98090_12P288M_WIDTH 1
184#define M98090_12M_MASK (1<<3)
185#define M98090_12M_SHIFT 3
186#define M98090_12M_WIDTH 1
187#define M98090_11P2896M_MASK (1<<2)
188#define M98090_11P2896M_SHIFT 2
189#define M98090_11P2896M_WIDTH 1
190#define M98090_256FS_MASK (1<<0)
191#define M98090_256FS_SHIFT 0
192#define M98090_256FS_WIDTH 1
193#define M98090_CLK_ALL_SHIFT 0
194#define M98090_CLK_ALL_WIDTH 8
195#define M98090_CLK_ALL_NUM (1<<M98090_CLK_ALL_WIDTH)
196
197/*
198 * M98090_REG_QUICK_SAMPLE_RATE
199 */
200#define M98090_SR_96K_MASK (1<<5)
201#define M98090_SR_96K_SHIFT 5
202#define M98090_SR_96K_WIDTH 1
203#define M98090_SR_32K_MASK (1<<4)
204#define M98090_SR_32K_SHIFT 4
205#define M98090_SR_32K_WIDTH 1
206#define M98090_SR_48K_MASK (1<<3)
207#define M98090_SR_48K_SHIFT 3
208#define M98090_SR_48K_WIDTH 1
209#define M98090_SR_44K1_MASK (1<<2)
210#define M98090_SR_44K1_SHIFT 2
211#define M98090_SR_44K1_WIDTH 1
212#define M98090_SR_16K_MASK (1<<1)
213#define M98090_SR_16K_SHIFT 1
214#define M98090_SR_16K_WIDTH 1
215#define M98090_SR_8K_MASK (1<<0)
216#define M98090_SR_8K_SHIFT 0
217#define M98090_SR_8K_WIDTH 1
218#define M98090_SR_MASK 0x3F
219#define M98090_SR_ALL_SHIFT 0
220#define M98090_SR_ALL_WIDTH 8
221#define M98090_SR_ALL_NUM (1<<M98090_SR_ALL_WIDTH)
222
223/*
224 * M98090_REG_DAI_INTERFACE
225 */
226#define M98090_RJ_M_MASK (1<<5)
227#define M98090_RJ_M_SHIFT 5
228#define M98090_RJ_M_WIDTH 1
229#define M98090_RJ_S_MASK (1<<4)
230#define M98090_RJ_S_SHIFT 4
231#define M98090_RJ_S_WIDTH 1
232#define M98090_LJ_M_MASK (1<<3)
233#define M98090_LJ_M_SHIFT 3
234#define M98090_LJ_M_WIDTH 1
235#define M98090_LJ_S_MASK (1<<2)
236#define M98090_LJ_S_SHIFT 2
237#define M98090_LJ_S_WIDTH 1
238#define M98090_I2S_M_MASK (1<<1)
239#define M98090_I2S_M_SHIFT 1
240#define M98090_I2S_M_WIDTH 1
241#define M98090_I2S_S_MASK (1<<0)
242#define M98090_I2S_S_SHIFT 0
243#define M98090_I2S_S_WIDTH 1
244#define M98090_DAI_ALL_SHIFT 0
245#define M98090_DAI_ALL_WIDTH 8
246#define M98090_DAI_ALL_NUM (1<<M98090_DAI_ALL_WIDTH)
247
248/*
249 * M98090_REG_DAC_PATH
250 */
251#define M98090_DIG2_HP_MASK (1<<7)
252#define M98090_DIG2_HP_SHIFT 7
253#define M98090_DIG2_HP_WIDTH 1
254#define M98090_DIG2_EAR_MASK (1<<6)
255#define M98090_DIG2_EAR_SHIFT 6
256#define M98090_DIG2_EAR_WIDTH 1
257#define M98090_DIG2_SPK_MASK (1<<5)
258#define M98090_DIG2_SPK_SHIFT 5
259#define M98090_DIG2_SPK_WIDTH 1
260#define M98090_DIG2_LOUT_MASK (1<<4)
261#define M98090_DIG2_LOUT_SHIFT 4
262#define M98090_DIG2_LOUT_WIDTH 1
263#define M98090_DIG2_ALL_SHIFT 0
264#define M98090_DIG2_ALL_WIDTH 8
265#define M98090_DIG2_ALL_NUM (1<<M98090_DIG2_ALL_WIDTH)
266
267/*
268 * M98090_REG_MIC_DIRECT_TO_ADC
269 */
270#define M98090_IN12_MIC1_MASK (1<<7)
271#define M98090_IN12_MIC1_SHIFT 7
272#define M98090_IN12_MIC1_WIDTH 1
273#define M98090_IN34_MIC2_MASK (1<<6)
274#define M98090_IN34_MIC2_SHIFT 6
275#define M98090_IN34_MIC2_WIDTH 1
276#define M98090_IN56_MIC1_MASK (1<<5)
277#define M98090_IN56_MIC1_SHIFT 5
278#define M98090_IN56_MIC1_WIDTH 1
279#define M98090_IN56_MIC2_MASK (1<<4)
280#define M98090_IN56_MIC2_SHIFT 4
281#define M98090_IN56_MIC2_WIDTH 1
282#define M98090_IN12_DADC_MASK (1<<3)
283#define M98090_IN12_DADC_SHIFT 3
284#define M98090_IN12_DADC_WIDTH 1
285#define M98090_IN34_DADC_MASK (1<<2)
286#define M98090_IN34_DADC_SHIFT 2
287#define M98090_IN34_DADC_WIDTH 1
288#define M98090_IN56_DADC_MASK (1<<1)
289#define M98090_IN56_DADC_SHIFT 1
290#define M98090_IN56_DADC_WIDTH 1
291#define M98090_MIC_ALL_SHIFT 0
292#define M98090_MIC_ALL_WIDTH 8
293#define M98090_MIC_ALL_NUM (1<<M98090_MIC_ALL_WIDTH)
294
295/*
296 * M98090_REG_LINE_TO_ADC
297 */
298#define M98090_IN12S_AB_MASK (1<<7)
299#define M98090_IN12S_AB_SHIFT 7
300#define M98090_IN12S_AB_WIDTH 1
301#define M98090_IN34S_AB_MASK (1<<6)
302#define M98090_IN34S_AB_SHIFT 6
303#define M98090_IN34S_AB_WIDTH 1
304#define M98090_IN56S_AB_MASK (1<<5)
305#define M98090_IN56S_AB_SHIFT 5
306#define M98090_IN56S_AB_WIDTH 1
307#define M98090_IN34D_A_MASK (1<<4)
308#define M98090_IN34D_A_SHIFT 4
309#define M98090_IN34D_A_WIDTH 1
310#define M98090_IN56D_B_MASK (1<<3)
311#define M98090_IN56D_B_SHIFT 3
312#define M98090_IN56D_B_WIDTH 1
313#define M98090_LINE_ALL_SHIFT 0
314#define M98090_LINE_ALL_WIDTH 8
315#define M98090_LINE_ALL_NUM (1<<M98090_LINE_ALL_WIDTH)
316
317/*
318 * M98090_REG_ANALOG_MIC_LOOP
319 */
320#define M98090_IN12_M1HPL_MASK (1<<7)
321#define M98090_IN12_M1HPL_SHIFT 7
322#define M98090_IN12_M1HPL_WIDTH 1
323#define M98090_IN12_M1SPKL_MASK (1<<6)
324#define M98090_IN12_M1SPKL_SHIFT 6
325#define M98090_IN12_M1SPKL_WIDTH 1
326#define M98090_IN12_M1EAR_MASK (1<<5)
327#define M98090_IN12_M1EAR_SHIFT 5
328#define M98090_IN12_M1EAR_WIDTH 1
329#define M98090_IN12_M1LOUTL_MASK (1<<4)
330#define M98090_IN12_M1LOUTL_SHIFT 4
331#define M98090_IN12_M1LOUTL_WIDTH 1
332#define M98090_IN34_M2HPR_MASK (1<<3)
333#define M98090_IN34_M2HPR_SHIFT 3
334#define M98090_IN34_M2HPR_WIDTH 1
335#define M98090_IN34_M2SPKR_MASK (1<<2)
336#define M98090_IN34_M2SPKR_SHIFT 2
337#define M98090_IN34_M2SPKR_WIDTH 1
338#define M98090_IN34_M2EAR_MASK (1<<1)
339#define M98090_IN34_M2EAR_SHIFT 1
340#define M98090_IN34_M2EAR_WIDTH 1
341#define M98090_IN34_M2LOUTR_MASK (1<<0)
342#define M98090_IN34_M2LOUTR_SHIFT 0
343#define M98090_IN34_M2LOUTR_WIDTH 1
344#define M98090_AMIC_ALL_SHIFT 0
345#define M98090_AMIC_ALL_WIDTH 8
346#define M98090_AMIC_ALL_NUM (1<<M98090_AMIC_ALL_WIDTH)
347
348/*
349 * M98090_REG_ANALOG_LINE_LOOP
350 */
351#define M98090_IN12S_ABHP_MASK (1<<7)
352#define M98090_IN12S_ABHP_SHIFT 7
353#define M98090_IN12S_ABHP_WIDTH 1
354#define M98090_IN34D_ASPKL_MASK (1<<6)
355#define M98090_IN34D_ASPKL_SHIFT 6
356#define M98090_IN34D_ASPKL_WIDTH 1
357#define M98090_IN34D_AEAR_MASK (1<<5)
358#define M98090_IN34D_AEAR_SHIFT 5
359#define M98090_IN34D_AEAR_WIDTH 1
360#define M98090_IN12S_ABLOUT_MASK (1<<4)
361#define M98090_IN12S_ABLOUT_SHIFT 4
362#define M98090_IN12S_ABLOUT_WIDTH 1
363#define M98090_IN34S_ABHP_MASK (1<<3)
364#define M98090_IN34S_ABHP_SHIFT 3
365#define M98090_IN34S_ABHP_WIDTH 1
366#define M98090_IN56D_BSPKR_MASK (1<<2)
367#define M98090_IN56D_BSPKR_SHIFT 2
368#define M98090_IN56D_BSPKR_WIDTH 1
369#define M98090_IN56D_BEAR_MASK (1<<1)
370#define M98090_IN56D_BEAR_SHIFT 1
371#define M98090_IN56D_BEAR_WIDTH 1
372#define M98090_IN34S_ABLOUT_MASK (1<<0)
373#define M98090_IN34S_ABLOUT_SHIFT 0
374#define M98090_IN34S_ABLOUT_WIDTH 1
375#define M98090_ALIN_ALL_SHIFT 0
376#define M98090_ALIN_ALL_WIDTH 8
377#define M98090_ALIN_ALL_NUM (1<<M98090_ALIN_ALL_WIDTH)
378
379/*
380 * M98090_REG_RESERVED
381 */
382
383/*
384 * M98090_REG_LINE_INPUT_CONFIG
385 */
386#define M98090_IN34DIFF_MASK (1<<7)
387#define M98090_IN34DIFF_SHIFT 7
388#define M98090_IN34DIFF_WIDTH 1
389#define M98090_IN56DIFF_MASK (1<<6)
390#define M98090_IN56DIFF_SHIFT 6
391#define M98090_IN56DIFF_WIDTH 1
392#define M98090_IN1SEEN_MASK (1<<5)
393#define M98090_IN1SEEN_SHIFT 5
394#define M98090_IN1SEEN_WIDTH 1
395#define M98090_IN2SEEN_MASK (1<<4)
396#define M98090_IN2SEEN_SHIFT 4
397#define M98090_IN2SEEN_WIDTH 1
398#define M98090_IN3SEEN_MASK (1<<3)
399#define M98090_IN3SEEN_SHIFT 3
400#define M98090_IN3SEEN_WIDTH 1
401#define M98090_IN4SEEN_MASK (1<<2)
402#define M98090_IN4SEEN_SHIFT 2
403#define M98090_IN4SEEN_WIDTH 1
404#define M98090_IN5SEEN_MASK (1<<1)
405#define M98090_IN5SEEN_SHIFT 1
406#define M98090_IN5SEEN_WIDTH 1
407#define M98090_IN6SEEN_MASK (1<<0)
408#define M98090_IN6SEEN_SHIFT 0
409#define M98090_IN6SEEN_WIDTH 1
410
411/*
412 * M98090_REG_LINE_INPUT_LEVEL
413 */
414#define M98090_MIXG135_MASK (1<<7)
415#define M98090_MIXG135_SHIFT 7
416#define M98090_MIXG135_WIDTH 1
417#define M98090_MIXG135_NUM (1<<M98090_MIXG135_WIDTH)
418#define M98090_MIXG246_MASK (1<<6)
419#define M98090_MIXG246_SHIFT 6
420#define M98090_MIXG246_WIDTH 1
421#define M98090_MIXG246_NUM (1<<M98090_MIXG246_WIDTH)
422#define M98090_LINAPGA_MASK (7<<3)
423#define M98090_LINAPGA_SHIFT 3
424#define M98090_LINAPGA_WIDTH 3
425#define M98090_LINAPGA_NUM 6
426#define M98090_LINBPGA_MASK (7<<0)
427#define M98090_LINBPGA_SHIFT 0
428#define M98090_LINBPGA_WIDTH 3
429#define M98090_LINBPGA_NUM 6
430
431/*
432 * M98090_REG_INPUT_MODE
433 */
434#define M98090_EXTBUFA_MASK (1<<7)
435#define M98090_EXTBUFA_SHIFT 7
436#define M98090_EXTBUFA_WIDTH 1
437#define M98090_EXTBUFA_NUM (1<<M98090_EXTBUFA_WIDTH)
438#define M98090_EXTBUFB_MASK (1<<6)
439#define M98090_EXTBUFB_SHIFT 6
440#define M98090_EXTBUFB_WIDTH 1
441#define M98090_EXTBUFB_NUM (1<<M98090_EXTBUFB_WIDTH)
442#define M98090_EXTMIC_MASK (3<<0)
443#define M98090_EXTMIC_SHIFT 0
444#define M98090_EXTMIC1_SHIFT 0
445#define M98090_EXTMIC2_SHIFT 1
446#define M98090_EXTMIC_WIDTH 2
447#define M98090_EXTMIC_NONE (0<<0)
448#define M98090_EXTMIC_MIC1 (1<<0)
449#define M98090_EXTMIC_MIC2 (2<<0)
450
451/*
452 * M98090_REG_MIC1_INPUT_LEVEL
453 */
454#define M98090_MIC_PA1EN_MASK (3<<5)
455#define M98090_MIC_PA1EN_SHIFT 5
456#define M98090_MIC_PA1EN_WIDTH 2
457#define M98090_MIC_PA1EN_NUM 3
458#define M98090_MIC_PGAM1_MASK (31<<0)
459#define M98090_MIC_PGAM1_SHIFT 0
460#define M98090_MIC_PGAM1_WIDTH 5
461#define M98090_MIC_PGAM1_NUM 21
462
463/*
464 * M98090_REG_MIC2_INPUT_LEVEL
465 */
466#define M98090_MIC_PA2EN_MASK (3<<5)
467#define M98090_MIC_PA2EN_SHIFT 5
468#define M98090_MIC_PA2EN_WIDTH 2
469#define M98090_MIC_PA2EN_NUM 3
470#define M98090_MIC_PGAM2_MASK (31<<0)
471#define M98090_MIC_PGAM2_SHIFT 0
472#define M98090_MIC_PGAM2_WIDTH 5
473#define M98090_MIC_PGAM2_NUM 21
474
475/*
476 * M98090_REG_MIC_BIAS_VOLTAGE
477 */
478#define M98090_MBVSEL_MASK (3<<0)
479#define M98090_MBVSEL_SHIFT 0
480#define M98090_MBVSEL_WIDTH 2
481#define M98090_MBVSEL_2V8 (3<<0)
482#define M98090_MBVSEL_2V55 (2<<0)
483#define M98090_MBVSEL_2V4 (1<<0)
484#define M98090_MBVSEL_2V2 (0<<0)
485
486/*
487 * M98090_REG_DIGITAL_MIC_ENABLE
488 */
489#define M98090_MICCLK_MASK (7<<4)
490#define M98090_MICCLK_SHIFT 4
491#define M98090_MICCLK_WIDTH 3
492#define M98090_DIGMIC4_MASK (1<<3)
493#define M98090_DIGMIC4_SHIFT 3
494#define M98090_DIGMIC4_WIDTH 1
495#define M98090_DIGMIC4_NUM (1<<M98090_DIGMIC4_WIDTH)
496#define M98090_DIGMIC3_MASK (1<<2)
497#define M98090_DIGMIC3_SHIFT 2
498#define M98090_DIGMIC3_WIDTH 1
499#define M98090_DIGMIC3_NUM (1<<M98090_DIGMIC3_WIDTH)
500#define M98090_DIGMICR_MASK (1<<1)
501#define M98090_DIGMICR_SHIFT 1
502#define M98090_DIGMICR_WIDTH 1
503#define M98090_DIGMICR_NUM (1<<M98090_DIGMICR_WIDTH)
504#define M98090_DIGMICL_MASK (1<<0)
505#define M98090_DIGMICL_SHIFT 0
506#define M98090_DIGMICL_WIDTH 1
507#define M98090_DIGMICL_NUM (1<<M98090_DIGMICL_WIDTH)
508
509/*
510 * M98090_REG_DIGITAL_MIC_CONFIG
511 */
512#define M98090_DMIC_COMP_MASK (15<<4)
513#define M98090_DMIC_COMP_SHIFT 4
514#define M98090_DMIC_COMP_WIDTH 4
515#define M98090_DMIC_COMP_NUM (1<<M98090_DMIC_COMP_WIDTH)
516#define M98090_DMIC_FREQ_MASK (3<<0)
517#define M98090_DMIC_FREQ_SHIFT 0
518#define M98090_DMIC_FREQ_WIDTH 2
519
520/*
521 * M98090_REG_LEFT_ADC_MIXER
522 */
523#define M98090_MIXADL_MIC2_MASK (1<<6)
524#define M98090_MIXADL_MIC2_SHIFT 6
525#define M98090_MIXADL_MIC2_WIDTH 1
526#define M98090_MIXADL_MIC1_MASK (1<<5)
527#define M98090_MIXADL_MIC1_SHIFT 5
528#define M98090_MIXADL_MIC1_WIDTH 1
529#define M98090_MIXADL_LINEB_MASK (1<<4)
530#define M98090_MIXADL_LINEB_SHIFT 4
531#define M98090_MIXADL_LINEB_WIDTH 1
532#define M98090_MIXADL_LINEA_MASK (1<<3)
533#define M98090_MIXADL_LINEA_SHIFT 3
534#define M98090_MIXADL_LINEA_WIDTH 1
535#define M98090_MIXADL_IN65DIFF_MASK (1<<2)
536#define M98090_MIXADL_IN65DIFF_SHIFT 2
537#define M98090_MIXADL_IN65DIFF_WIDTH 1
538#define M98090_MIXADL_IN34DIFF_MASK (1<<1)
539#define M98090_MIXADL_IN34DIFF_SHIFT 1
540#define M98090_MIXADL_IN34DIFF_WIDTH 1
541#define M98090_MIXADL_IN12DIFF_MASK (1<<0)
542#define M98090_MIXADL_IN12DIFF_SHIFT 0
543#define M98090_MIXADL_IN12DIFF_WIDTH 1
544#define M98090_MIXADL_MASK (255<<0)
545#define M98090_MIXADL_SHIFT 0
546#define M98090_MIXADL_WIDTH 8
547
548/*
549 * M98090_REG_RIGHT_ADC_MIXER
550 */
551#define M98090_MIXADR_MIC2_MASK (1<<6)
552#define M98090_MIXADR_MIC2_SHIFT 6
553#define M98090_MIXADR_MIC2_WIDTH 1
554#define M98090_MIXADR_MIC1_MASK (1<<5)
555#define M98090_MIXADR_MIC1_SHIFT 5
556#define M98090_MIXADR_MIC1_WIDTH 1
557#define M98090_MIXADR_LINEB_MASK (1<<4)
558#define M98090_MIXADR_LINEB_SHIFT 4
559#define M98090_MIXADR_LINEB_WIDTH 1
560#define M98090_MIXADR_LINEA_MASK (1<<3)
561#define M98090_MIXADR_LINEA_SHIFT 3
562#define M98090_MIXADR_LINEA_WIDTH 1
563#define M98090_MIXADR_IN65DIFF_MASK (1<<2)
564#define M98090_MIXADR_IN65DIFF_SHIFT 2
565#define M98090_MIXADR_IN65DIFF_WIDTH 1
566#define M98090_MIXADR_IN34DIFF_MASK (1<<1)
567#define M98090_MIXADR_IN34DIFF_SHIFT 1
568#define M98090_MIXADR_IN34DIFF_WIDTH 1
569#define M98090_MIXADR_IN12DIFF_MASK (1<<0)
570#define M98090_MIXADR_IN12DIFF_SHIFT 0
571#define M98090_MIXADR_IN12DIFF_WIDTH 1
572#define M98090_MIXADR_MASK (255<<0)
573#define M98090_MIXADR_SHIFT 0
574#define M98090_MIXADR_WIDTH 8
575
576/*
577 * M98090_REG_LEFT_ADC_LEVEL
578 */
579#define M98090_AVLG_MASK (7<<4)
580#define M98090_AVLG_SHIFT 4
581#define M98090_AVLG_WIDTH 3
582#define M98090_AVLG_NUM (1<<M98090_AVLG_WIDTH)
583#define M98090_AVL_MASK (15<<0)
584#define M98090_AVL_SHIFT 0
585#define M98090_AVL_WIDTH 4
586#define M98090_AVL_NUM (1<<M98090_AVL_WIDTH)
587
588/*
589 * M98090_REG_RIGHT_ADC_LEVEL
590 */
591#define M98090_AVRG_MASK (7<<4)
592#define M98090_AVRG_SHIFT 4
593#define M98090_AVRG_WIDTH 3
594#define M98090_AVRG_NUM (1<<M98090_AVRG_WIDTH)
595#define M98090_AVR_MASK (15<<0)
596#define M98090_AVR_SHIFT 0
597#define M98090_AVR_WIDTH 4
598#define M98090_AVR_NUM (1<<M98090_AVR_WIDTH)
599
600/*
601 * M98090_REG_ADC_BIQUAD_LEVEL
602 */
603#define M98090_AVBQ_MASK (15<<0)
604#define M98090_AVBQ_SHIFT 0
605#define M98090_AVBQ_WIDTH 4
606#define M98090_AVBQ_NUM (1<<M98090_AVBQ_WIDTH)
607
608/*
609 * M98090_REG_ADC_SIDETONE
610 */
611#define M98090_DSTSR_MASK (1<<7)
612#define M98090_DSTSR_SHIFT 7
613#define M98090_DSTSR_WIDTH 1
614#define M98090_DSTSL_MASK (1<<6)
615#define M98090_DSTSL_SHIFT 6
616#define M98090_DSTSL_WIDTH 1
617#define M98090_DVST_MASK (31<<0)
618#define M98090_DVST_SHIFT 0
619#define M98090_DVST_WIDTH 5
620#define M98090_DVST_NUM 31
621
622/*
623 * M98090_REG_SYSTEM_CLOCK
624 */
625#define M98090_PSCLK_MASK (3<<4)
626#define M98090_PSCLK_SHIFT 4
627#define M98090_PSCLK_WIDTH 2
628#define M98090_PSCLK_DISABLED (0<<4)
629#define M98090_PSCLK_DIV1 (1<<4)
630#define M98090_PSCLK_DIV2 (2<<4)
631#define M98090_PSCLK_DIV4 (3<<4)
632
633/*
634 * M98090_REG_CLOCK_MODE
635 */
636#define M98090_FREQ_MASK (15<<4)
637#define M98090_FREQ_SHIFT 4
638#define M98090_FREQ_WIDTH 4
639#define M98090_USE_M1_MASK (1<<0)
640#define M98090_USE_M1_SHIFT 0
641#define M98090_USE_M1_WIDTH 1
642#define M98090_USE_M1_NUM (1<<M98090_USE_M1_WIDTH)
643
644/*
645 * M98090_REG_CLOCK_RATIO_NI_MSB
646 */
647#define M98090_NI_HI_MASK (127<<0)
648#define M98090_NI_HI_SHIFT 0
649#define M98090_NI_HI_WIDTH 7
650#define M98090_NI_HI_NUM (1<<M98090_NI_HI_WIDTH)
651
652/*
653 * M98090_REG_CLOCK_RATIO_NI_LSB
654 */
655#define M98090_NI_LO_MASK (255<<0)
656#define M98090_NI_LO_SHIFT 0
657#define M98090_NI_LO_WIDTH 8
658#define M98090_NI_LO_NUM (1<<M98090_NI_LO_WIDTH)
659
660/*
661 * M98090_REG_CLOCK_RATIO_MI_MSB
662 */
663#define M98090_MI_HI_MASK (255<<0)
664#define M98090_MI_HI_SHIFT 0
665#define M98090_MI_HI_WIDTH 8
666#define M98090_MI_HI_NUM (1<<M98090_MI_HI_WIDTH)
667
668/*
669 * M98090_REG_CLOCK_RATIO_MI_LSB
670 */
671#define M98090_MI_LO_MASK (255<<0)
672#define M98090_MI_LO_SHIFT 0
673#define M98090_MI_LO_WIDTH 8
674#define M98090_MI_LO_NUM (1<<M98090_MI_LO_WIDTH)
675
676/*
677 * M98090_REG_MASTER_MODE
678 */
679#define M98090_MAS_MASK (1<<7)
680#define M98090_MAS_SHIFT 7
681#define M98090_MAS_WIDTH 1
682#define M98090_BSEL_MASK (1<<0)
683#define M98090_BSEL_SHIFT 0
684#define M98090_BSEL_WIDTH 1
685#define M98090_BSEL_32 (1<<0)
686#define M98090_BSEL_48 (2<<0)
687#define M98090_BSEL_64 (3<<0)
688
689/*
690 * M98090_REG_INTERFACE_FORMAT
691 */
692#define M98090_RJ_MASK (1<<5)
693#define M98090_RJ_SHIFT 5
694#define M98090_RJ_WIDTH 1
695#define M98090_WCI_MASK (1<<4)
696#define M98090_WCI_SHIFT 4
697#define M98090_WCI_WIDTH 1
698#define M98090_BCI_MASK (1<<3)
699#define M98090_BCI_SHIFT 3
700#define M98090_BCI_WIDTH 1
701#define M98090_DLY_MASK (1<<2)
702#define M98090_DLY_SHIFT 2
703#define M98090_DLY_WIDTH 1
704#define M98090_WS_MASK (3<<0)
705#define M98090_WS_SHIFT 0
706#define M98090_WS_WIDTH 2
707#define M98090_WS_NUM (1<<M98090_WS_WIDTH)
708
709/*
710 * M98090_REG_TDM_CONTROL
711 */
712#define M98090_FSW_MASK (1<<1)
713#define M98090_FSW_SHIFT 1
714#define M98090_FSW_WIDTH 1
715#define M98090_TDM_MASK (1<<0)
716#define M98090_TDM_SHIFT 0
717#define M98090_TDM_WIDTH 1
718#define M98090_TDM_NUM (1<<M98090_TDM_WIDTH)
719
720/*
721 * M98090_REG_TDM_FORMAT
722 */
723#define M98090_TDM_SLOTL_MASK (3<<6)
724#define M98090_TDM_SLOTL_SHIFT 6
725#define M98090_TDM_SLOTL_WIDTH 2
726#define M98090_TDM_SLOTL_NUM (1<<M98090_TDM_SLOTL_WIDTH)
727#define M98090_TDM_SLOTR_MASK (3<<4)
728#define M98090_TDM_SLOTR_SHIFT 4
729#define M98090_TDM_SLOTR_WIDTH 2
730#define M98090_TDM_SLOTR_NUM (1<<M98090_TDM_SLOTR_WIDTH)
731#define M98090_TDM_SLOTDLY_MASK (15<<0)
732#define M98090_TDM_SLOTDLY_SHIFT 0
733#define M98090_TDM_SLOTDLY_WIDTH 4
734#define M98090_TDM_SLOTDLY_NUM (1<<M98090_TDM_SLOTDLY_WIDTH)
735
736/*
737 * M98090_REG_IO_CONFIGURATION
738 */
739#define M98090_LTEN_MASK (1<<5)
740#define M98090_LTEN_SHIFT 5
741#define M98090_LTEN_WIDTH 1
742#define M98090_LTEN_NUM (1<<M98090_LTEN_WIDTH)
743#define M98090_LBEN_MASK (1<<4)
744#define M98090_LBEN_SHIFT 4
745#define M98090_LBEN_WIDTH 1
746#define M98090_LBEN_NUM (1<<M98090_LBEN_WIDTH)
747#define M98090_DMONO_MASK (1<<3)
748#define M98090_DMONO_SHIFT 3
749#define M98090_DMONO_WIDTH 1
750#define M98090_DMONO_NUM (1<<M98090_DMONO_WIDTH)
751#define M98090_HIZOFF_MASK (1<<2)
752#define M98090_HIZOFF_SHIFT 2
753#define M98090_HIZOFF_WIDTH 1
754#define M98090_HIZOFF_NUM (1<<M98090_HIZOFF_WIDTH)
755#define M98090_SDOEN_MASK (1<<1)
756#define M98090_SDOEN_SHIFT 1
757#define M98090_SDOEN_WIDTH 1
758#define M98090_SDOEN_NUM (1<<M98090_SDOEN_WIDTH)
759#define M98090_SDIEN_MASK (1<<0)
760#define M98090_SDIEN_SHIFT 0
761#define M98090_SDIEN_WIDTH 1
762#define M98090_SDIEN_NUM (1<<M98090_SDIEN_WIDTH)
763
764/*
765 * M98090_REG_FILTER_CONFIG
766 */
767#define M98090_MODE_MASK (1<<7)
768#define M98090_MODE_SHIFT 7
769#define M98090_MODE_WIDTH 1
770#define M98090_AHPF_MASK (1<<6)
771#define M98090_AHPF_SHIFT 6
772#define M98090_AHPF_WIDTH 1
773#define M98090_AHPF_NUM (1<<M98090_AHPF_WIDTH)
774#define M98090_DHPF_MASK (1<<5)
775#define M98090_DHPF_SHIFT 5
776#define M98090_DHPF_WIDTH 1
777#define M98090_DHPF_NUM (1<<M98090_DHPF_WIDTH)
778#define M98090_DHF_MASK (1<<4)
779#define M98090_DHF_SHIFT 4
780#define M98090_DHF_WIDTH 1
781#define M98090_FLT_DMIC34MODE_MASK (1<<3)
782#define M98090_FLT_DMIC34MODE_SHIFT 3
783#define M98090_FLT_DMIC34MODE_WIDTH 1
784#define M98090_FLT_DMIC34HPF_MASK (1<<2)
785#define M98090_FLT_DMIC34HPF_SHIFT 2
786#define M98090_FLT_DMIC34HPF_WIDTH 1
787#define M98090_FLT_DMIC34HPF_NUM (1<<M98090_FLT_DMIC34HPF_WIDTH)
788
789/*
790 * M98090_REG_DAI_PLAYBACK_LEVEL
791 */
792#define M98090_DVM_MASK (1<<7)
793#define M98090_DVM_SHIFT 7
794#define M98090_DVM_WIDTH 1
795#define M98090_DVG_MASK (3<<4)
796#define M98090_DVG_SHIFT 4
797#define M98090_DVG_WIDTH 2
798#define M98090_DVG_NUM (1<<M98090_DVG_WIDTH)
799#define M98090_DV_MASK (15<<0)
800#define M98090_DV_SHIFT 0
801#define M98090_DV_WIDTH 4
802#define M98090_DV_NUM (1<<M98090_DV_WIDTH)
803
804/*
805 * M98090_REG_DAI_PLAYBACK_LEVEL_EQ
806 */
807#define M98090_EQCLPN_MASK (1<<4)
808#define M98090_EQCLPN_SHIFT 4
809#define M98090_EQCLPN_WIDTH 1
810#define M98090_EQCLPN_NUM (1<<M98090_EQCLPN_WIDTH)
811#define M98090_DVEQ_MASK (15<<0)
812#define M98090_DVEQ_SHIFT 0
813#define M98090_DVEQ_WIDTH 4
814#define M98090_DVEQ_NUM (1<<M98090_DVEQ_WIDTH)
815
816/*
817 * M98090_REG_LEFT_HP_MIXER
818 */
819#define M98090_MIXHPL_MIC2_MASK (1<<5)
820#define M98090_MIXHPL_MIC2_SHIFT 5
821#define M98090_MIXHPL_MIC2_WIDTH 1
822#define M98090_MIXHPL_MIC1_MASK (1<<4)
823#define M98090_MIXHPL_MIC1_SHIFT 4
824#define M98090_MIXHPL_MIC1_WIDTH 1
825#define M98090_MIXHPL_LINEB_MASK (1<<3)
826#define M98090_MIXHPL_LINEB_SHIFT 3
827#define M98090_MIXHPL_LINEB_WIDTH 1
828#define M98090_MIXHPL_LINEA_MASK (1<<2)
829#define M98090_MIXHPL_LINEA_SHIFT 2
830#define M98090_MIXHPL_LINEA_WIDTH 1
831#define M98090_MIXHPL_DACR_MASK (1<<1)
832#define M98090_MIXHPL_DACR_SHIFT 1
833#define M98090_MIXHPL_DACR_WIDTH 1
834#define M98090_MIXHPL_DACL_MASK (1<<0)
835#define M98090_MIXHPL_DACL_SHIFT 0
836#define M98090_MIXHPL_DACL_WIDTH 1
837#define M98090_MIXHPL_MASK (63<<0)
838#define M98090_MIXHPL_SHIFT 0
839#define M98090_MIXHPL_WIDTH 6
840
841/*
842 * M98090_REG_RIGHT_HP_MIXER
843 */
844#define M98090_MIXHPR_MIC2_MASK (1<<5)
845#define M98090_MIXHPR_MIC2_SHIFT 5
846#define M98090_MIXHPR_MIC2_WIDTH 1
847#define M98090_MIXHPR_MIC1_MASK (1<<4)
848#define M98090_MIXHPR_MIC1_SHIFT 4
849#define M98090_MIXHPR_MIC1_WIDTH 1
850#define M98090_MIXHPR_LINEB_MASK (1<<3)
851#define M98090_MIXHPR_LINEB_SHIFT 3
852#define M98090_MIXHPR_LINEB_WIDTH 1
853#define M98090_MIXHPR_LINEA_MASK (1<<2)
854#define M98090_MIXHPR_LINEA_SHIFT 2
855#define M98090_MIXHPR_LINEA_WIDTH 1
856#define M98090_MIXHPR_DACR_MASK (1<<1)
857#define M98090_MIXHPR_DACR_SHIFT 1
858#define M98090_MIXHPR_DACR_WIDTH 1
859#define M98090_MIXHPR_DACL_MASK (1<<0)
860#define M98090_MIXHPR_DACL_SHIFT 0
861#define M98090_MIXHPR_DACL_WIDTH 1
862#define M98090_MIXHPR_MASK (63<<0)
863#define M98090_MIXHPR_SHIFT 0
864#define M98090_MIXHPR_WIDTH 6
865
866/*
867 * M98090_REG_HP_CONTROL
868 */
869#define M98090_MIXHPRSEL_MASK (1<<5)
870#define M98090_MIXHPRSEL_SHIFT 5
871#define M98090_MIXHPRSEL_WIDTH 1
872#define M98090_MIXHPLSEL_MASK (1<<4)
873#define M98090_MIXHPLSEL_SHIFT 4
874#define M98090_MIXHPLSEL_WIDTH 1
875#define M98090_MIXHPRG_MASK (3<<2)
876#define M98090_MIXHPRG_SHIFT 2
877#define M98090_MIXHPRG_WIDTH 2
878#define M98090_MIXHPRG_NUM (1<<M98090_MIXHPRG_WIDTH)
879#define M98090_MIXHPLG_MASK (3<<0)
880#define M98090_MIXHPLG_SHIFT 0
881#define M98090_MIXHPLG_WIDTH 2
882#define M98090_MIXHPLG_NUM (1<<M98090_MIXHPLG_WIDTH)
883
884/*
885 * M98090_REG_LEFT_HP_VOLUME
886 */
887#define M98090_HPLM_MASK (1<<7)
888#define M98090_HPLM_SHIFT 7
889#define M98090_HPLM_WIDTH 1
890#define M98090_HPVOLL_MASK (31<<0)
891#define M98090_HPVOLL_SHIFT 0
892#define M98090_HPVOLL_WIDTH 5
893#define M98090_HPVOLL_NUM (1<<M98090_HPVOLL_WIDTH)
894
895/*
896 * M98090_REG_RIGHT_HP_VOLUME
897 */
898#define M98090_HPRM_MASK (1<<7)
899#define M98090_HPRM_SHIFT 7
900#define M98090_HPRM_WIDTH 1
901#define M98090_HPVOLR_MASK (31<<0)
902#define M98090_HPVOLR_SHIFT 0
903#define M98090_HPVOLR_WIDTH 5
904#define M98090_HPVOLR_NUM (1<<M98090_HPVOLR_WIDTH)
905
906/*
907 * M98090_REG_LEFT_SPK_MIXER
908 */
909#define M98090_MIXSPL_MIC2_MASK (1<<5)
910#define M98090_MIXSPL_MIC2_SHIFT 5
911#define M98090_MIXSPL_MIC2_WIDTH 1
912#define M98090_MIXSPL_MIC1_MASK (1<<4)
913#define M98090_MIXSPL_MIC1_SHIFT 4
914#define M98090_MIXSPL_MIC1_WIDTH 1
915#define M98090_MIXSPL_LINEB_MASK (1<<3)
916#define M98090_MIXSPL_LINEB_SHIFT 3
917#define M98090_MIXSPL_LINEB_WIDTH 1
918#define M98090_MIXSPL_LINEA_MASK (1<<2)
919#define M98090_MIXSPL_LINEA_SHIFT 2
920#define M98090_MIXSPL_LINEA_WIDTH 1
921#define M98090_MIXSPL_DACR_MASK (1<<1)
922#define M98090_MIXSPL_DACR_SHIFT 1
923#define M98090_MIXSPL_DACR_WIDTH 1
924#define M98090_MIXSPL_DACL_MASK (1<<0)
925#define M98090_MIXSPL_DACL_SHIFT 0
926#define M98090_MIXSPL_DACL_WIDTH 1
927#define M98090_MIXSPL_MASK (63<<0)
928#define M98090_MIXSPL_SHIFT 0
929#define M98090_MIXSPL_WIDTH 6
930#define M98090_MIXSPR_DACR_MASK (1<<1)
931#define M98090_MIXSPR_DACR_SHIFT 1
932#define M98090_MIXSPR_DACR_WIDTH 1
933
934
935/*
936 * M98090_REG_RIGHT_SPK_MIXER
937 */
938#define M98090_SPK_SLAVE_MASK (1<<6)
939#define M98090_SPK_SLAVE_SHIFT 6
940#define M98090_SPK_SLAVE_WIDTH 1
941#define M98090_MIXSPR_MIC2_MASK (1<<5)
942#define M98090_MIXSPR_MIC2_SHIFT 5
943#define M98090_MIXSPR_MIC2_WIDTH 1
944#define M98090_MIXSPR_MIC1_MASK (1<<4)
945#define M98090_MIXSPR_MIC1_SHIFT 4
946#define M98090_MIXSPR_MIC1_WIDTH 1
947#define M98090_MIXSPR_LINEB_MASK (1<<3)
948#define M98090_MIXSPR_LINEB_SHIFT 3
949#define M98090_MIXSPR_LINEB_WIDTH 1
950#define M98090_MIXSPR_LINEA_MASK (1<<2)
951#define M98090_MIXSPR_LINEA_SHIFT 2
952#define M98090_MIXSPR_LINEA_WIDTH 1
953#define M98090_MIXSPR_DACR_MASK (1<<1)
954#define M98090_MIXSPR_DACR_SHIFT 1
955#define M98090_MIXSPR_DACR_WIDTH 1
956#define M98090_MIXSPR_DACL_MASK (1<<0)
957#define M98090_MIXSPR_DACL_SHIFT 0
958#define M98090_MIXSPR_DACL_WIDTH 1
959#define M98090_MIXSPR_MASK (63<<0)
960#define M98090_MIXSPR_SHIFT 0
961#define M98090_MIXSPR_WIDTH 6
962
963/*
964 * M98090_REG_SPK_CONTROL
965 */
966#define M98090_MIXSPRG_MASK (3<<2)
967#define M98090_MIXSPRG_SHIFT 2
968#define M98090_MIXSPRG_WIDTH 2
969#define M98090_MIXSPRG_NUM (1<<M98090_MIXSPRG_WIDTH)
970#define M98090_MIXSPLG_MASK (3<<0)
971#define M98090_MIXSPLG_SHIFT 0
972#define M98090_MIXSPLG_WIDTH 2
973#define M98090_MIXSPLG_NUM (1<<M98090_MIXSPLG_WIDTH)
974
975/*
976 * M98090_REG_LEFT_SPK_VOLUME
977 */
978#define M98090_SPLM_MASK (1<<7)
979#define M98090_SPLM_SHIFT 7
980#define M98090_SPLM_WIDTH 1
981#define M98090_SPVOLL_MASK (63<<0)
982#define M98090_SPVOLL_SHIFT 0
983#define M98090_SPVOLL_WIDTH 6
984#define M98090_SPVOLL_NUM 40
985
986/*
987 * M98090_REG_RIGHT_SPK_VOLUME
988 */
989#define M98090_SPRM_MASK (1<<7)
990#define M98090_SPRM_SHIFT 7
991#define M98090_SPRM_WIDTH 1
992#define M98090_SPVOLR_MASK (63<<0)
993#define M98090_SPVOLR_SHIFT 0
994#define M98090_SPVOLR_WIDTH 6
995#define M98090_SPVOLR_NUM 40
996
997/*
998 * M98090_REG_DRC_TIMING
999 */
1000#define M98090_DRCEN_MASK (1<<7)
1001#define M98090_DRCEN_SHIFT 7
1002#define M98090_DRCEN_WIDTH 1
1003#define M98090_DRCEN_NUM (1<<M98090_DRCEN_WIDTH)
1004#define M98090_DRCRLS_MASK (7<<4)
1005#define M98090_DRCRLS_SHIFT 4
1006#define M98090_DRCRLS_WIDTH 3
1007#define M98090_DRCATK_MASK (7<<0)
1008#define M98090_DRCATK_SHIFT 0
1009#define M98090_DRCATK_WIDTH 3
1010
1011/*
1012 * M98090_REG_DRC_COMPRESSOR
1013 */
1014#define M98090_DRCCMP_MASK (7<<5)
1015#define M98090_DRCCMP_SHIFT 5
1016#define M98090_DRCCMP_WIDTH 3
1017#define M98090_DRCTHC_MASK (31<<0)
1018#define M98090_DRCTHC_SHIFT 0
1019#define M98090_DRCTHC_WIDTH 5
1020#define M98090_DRCTHC_NUM (1<<M98090_DRCTHC_WIDTH)
1021
1022/*
1023 * M98090_REG_DRC_EXPANDER
1024 */
1025#define M98090_DRCEXP_MASK (7<<5)
1026#define M98090_DRCEXP_SHIFT 5
1027#define M98090_DRCEXP_WIDTH 3
1028#define M98090_DRCTHE_MASK (31<<0)
1029#define M98090_DRCTHE_SHIFT 0
1030#define M98090_DRCTHE_WIDTH 5
1031#define M98090_DRCTHE_NUM (1<<M98090_DRCTHE_WIDTH)
1032
1033/*
1034 * M98090_REG_DRC_GAIN
1035 */
1036#define M98090_DRCG_MASK (31<<0)
1037#define M98090_DRCG_SHIFT 0
1038#define M98090_DRCG_WIDTH 5
1039#define M98090_DRCG_NUM 13
1040
1041/*
1042 * M98090_REG_RCV_LOUTL_MIXER
1043 */
1044#define M98090_MIXRCVL_MIC2_MASK (1<<5)
1045#define M98090_MIXRCVL_MIC2_SHIFT 5
1046#define M98090_MIXRCVL_MIC2_WIDTH 1
1047#define M98090_MIXRCVL_MIC1_MASK (1<<4)
1048#define M98090_MIXRCVL_MIC1_SHIFT 4
1049#define M98090_MIXRCVL_MIC1_WIDTH 1
1050#define M98090_MIXRCVL_LINEB_MASK (1<<3)
1051#define M98090_MIXRCVL_LINEB_SHIFT 3
1052#define M98090_MIXRCVL_LINEB_WIDTH 1
1053#define M98090_MIXRCVL_LINEA_MASK (1<<2)
1054#define M98090_MIXRCVL_LINEA_SHIFT 2
1055#define M98090_MIXRCVL_LINEA_WIDTH 1
1056#define M98090_MIXRCVL_DACR_MASK (1<<1)
1057#define M98090_MIXRCVL_DACR_SHIFT 1
1058#define M98090_MIXRCVL_DACR_WIDTH 1
1059#define M98090_MIXRCVL_DACL_MASK (1<<0)
1060#define M98090_MIXRCVL_DACL_SHIFT 0
1061#define M98090_MIXRCVL_DACL_WIDTH 1
1062#define M98090_MIXRCVL_MASK (63<<0)
1063#define M98090_MIXRCVL_SHIFT 0
1064#define M98090_MIXRCVL_WIDTH 6
1065
1066/*
1067 * M98090_REG_RCV_LOUTL_CONTROL
1068 */
1069#define M98090_MIXRCVLG_MASK (3<<0)
1070#define M98090_MIXRCVLG_SHIFT 0
1071#define M98090_MIXRCVLG_WIDTH 2
1072#define M98090_MIXRCVLG_NUM (1<<M98090_MIXRCVLG_WIDTH)
1073
1074/*
1075 * M98090_REG_RCV_LOUTL_VOLUME
1076 */
1077#define M98090_RCVLM_MASK (1<<7)
1078#define M98090_RCVLM_SHIFT 7
1079#define M98090_RCVLM_WIDTH 1
1080#define M98090_RCVLVOL_MASK (31<<0)
1081#define M98090_RCVLVOL_SHIFT 0
1082#define M98090_RCVLVOL_WIDTH 5
1083#define M98090_RCVLVOL_NUM (1<<M98090_RCVLVOL_WIDTH)
1084
1085/*
1086 * M98090_REG_LOUTR_MIXER
1087 */
1088#define M98090_LINMOD_MASK (1<<7)
1089#define M98090_LINMOD_SHIFT 7
1090#define M98090_LINMOD_WIDTH 1
1091#define M98090_MIXRCVR_MIC2_MASK (1<<5)
1092#define M98090_MIXRCVR_MIC2_SHIFT 5
1093#define M98090_MIXRCVR_MIC2_WIDTH 1
1094#define M98090_MIXRCVR_MIC1_MASK (1<<4)
1095#define M98090_MIXRCVR_MIC1_SHIFT 4
1096#define M98090_MIXRCVR_MIC1_WIDTH 1
1097#define M98090_MIXRCVR_LINEB_MASK (1<<3)
1098#define M98090_MIXRCVR_LINEB_SHIFT 3
1099#define M98090_MIXRCVR_LINEB_WIDTH 1
1100#define M98090_MIXRCVR_LINEA_MASK (1<<2)
1101#define M98090_MIXRCVR_LINEA_SHIFT 2
1102#define M98090_MIXRCVR_LINEA_WIDTH 1
1103#define M98090_MIXRCVR_DACR_MASK (1<<1)
1104#define M98090_MIXRCVR_DACR_SHIFT 1
1105#define M98090_MIXRCVR_DACR_WIDTH 1
1106#define M98090_MIXRCVR_DACL_MASK (1<<0)
1107#define M98090_MIXRCVR_DACL_SHIFT 0
1108#define M98090_MIXRCVR_DACL_WIDTH 1
1109#define M98090_MIXRCVR_MASK (63<<0)
1110#define M98090_MIXRCVR_SHIFT 0
1111#define M98090_MIXRCVR_WIDTH 6
1112
1113/*
1114 * M98090_REG_LOUTR_CONTROL
1115 */
1116#define M98090_MIXRCVRG_MASK (3<<0)
1117#define M98090_MIXRCVRG_SHIFT 0
1118#define M98090_MIXRCVRG_WIDTH 2
1119#define M98090_MIXRCVRG_NUM (1<<M98090_MIXRCVRG_WIDTH)
1120
1121/*
1122 * M98090_REG_LOUTR_VOLUME
1123 */
1124#define M98090_RCVRM_MASK (1<<7)
1125#define M98090_RCVRM_SHIFT 7
1126#define M98090_RCVRM_WIDTH 1
1127#define M98090_RCVRVOL_MASK (31<<0)
1128#define M98090_RCVRVOL_SHIFT 0
1129#define M98090_RCVRVOL_WIDTH 5
1130#define M98090_RCVRVOL_NUM (1<<M98090_RCVRVOL_WIDTH)
1131
1132/*
1133 * M98090_REG_JACK_DETECT
1134 */
1135#define M98090_JDETEN_MASK (1<<7)
1136#define M98090_JDETEN_SHIFT 7
1137#define M98090_JDETEN_WIDTH 1
1138#define M98090_JDWK_MASK (1<<6)
1139#define M98090_JDWK_SHIFT 6
1140#define M98090_JDWK_WIDTH 1
1141#define M98090_JDEB_MASK (3<<0)
1142#define M98090_JDEB_SHIFT 0
1143#define M98090_JDEB_WIDTH 2
1144#define M98090_JDEB_25MS (0<<0)
1145#define M98090_JDEB_50MS (1<<0)
1146#define M98090_JDEB_100MS (2<<0)
1147#define M98090_JDEB_200MS (3<<0)
1148
1149/*
1150 * M98090_REG_INPUT_ENABLE
1151 */
1152#define M98090_MBEN_MASK (1<<4)
1153#define M98090_MBEN_SHIFT 4
1154#define M98090_MBEN_WIDTH 1
1155#define M98090_LINEAEN_MASK (1<<3)
1156#define M98090_LINEAEN_SHIFT 3
1157#define M98090_LINEAEN_WIDTH 1
1158#define M98090_LINEBEN_MASK (1<<2)
1159#define M98090_LINEBEN_SHIFT 2
1160#define M98090_LINEBEN_WIDTH 1
1161#define M98090_ADREN_MASK (1<<1)
1162#define M98090_ADREN_SHIFT 1
1163#define M98090_ADREN_WIDTH 1
1164#define M98090_ADLEN_MASK (1<<0)
1165#define M98090_ADLEN_SHIFT 0
1166#define M98090_ADLEN_WIDTH 1
1167
1168/*
1169 * M98090_REG_OUTPUT_ENABLE
1170 */
1171#define M98090_HPREN_MASK (1<<7)
1172#define M98090_HPREN_SHIFT 7
1173#define M98090_HPREN_WIDTH 1
1174#define M98090_HPLEN_MASK (1<<6)
1175#define M98090_HPLEN_SHIFT 6
1176#define M98090_HPLEN_WIDTH 1
1177#define M98090_SPREN_MASK (1<<5)
1178#define M98090_SPREN_SHIFT 5
1179#define M98090_SPREN_WIDTH 1
1180#define M98090_SPLEN_MASK (1<<4)
1181#define M98090_SPLEN_SHIFT 4
1182#define M98090_SPLEN_WIDTH 1
1183#define M98090_RCVLEN_MASK (1<<3)
1184#define M98090_RCVLEN_SHIFT 3
1185#define M98090_RCVLEN_WIDTH 1
1186#define M98090_RCVREN_MASK (1<<2)
1187#define M98090_RCVREN_SHIFT 2
1188#define M98090_RCVREN_WIDTH 1
1189#define M98090_DAREN_MASK (1<<1)
1190#define M98090_DAREN_SHIFT 1
1191#define M98090_DAREN_WIDTH 1
1192#define M98090_DALEN_MASK (1<<0)
1193#define M98090_DALEN_SHIFT 0
1194#define M98090_DALEN_WIDTH 1
1195
1196/*
1197 * M98090_REG_LEVEL_CONTROL
1198 */
1199#define M98090_ZDENN_MASK (1<<2)
1200#define M98090_ZDENN_SHIFT 2
1201#define M98090_ZDENN_WIDTH 1
1202#define M98090_ZDENN_NUM (1<<M98090_ZDENN_WIDTH)
1203#define M98090_VS2ENN_MASK (1<<1)
1204#define M98090_VS2ENN_SHIFT 1
1205#define M98090_VS2ENN_WIDTH 1
1206#define M98090_VS2ENN_NUM (1<<M98090_VS2ENN_WIDTH)
1207#define M98090_VSENN_MASK (1<<0)
1208#define M98090_VSENN_SHIFT 0
1209#define M98090_VSENN_WIDTH 1
1210#define M98090_VSENN_NUM (1<<M98090_VSENN_WIDTH)
1211
1212/*
1213 * M98090_REG_DSP_FILTER_ENABLE
1214 */
1215#define M98090_DMIC34BQEN_MASK (1<<4)
1216#define M98090_DMIC34BQEN_SHIFT 4
1217#define M98090_DMIC34BQEN_WIDTH 1
1218#define M98090_DMIC34BQEN_NUM (1<<M98090_DMIC34BQEN_WIDTH)
1219#define M98090_ADCBQEN_MASK (1<<3)
1220#define M98090_ADCBQEN_SHIFT 3
1221#define M98090_ADCBQEN_WIDTH 1
1222#define M98090_ADCBQEN_NUM (1<<M98090_ADCBQEN_WIDTH)
1223#define M98090_EQ3BANDEN_MASK (1<<2)
1224#define M98090_EQ3BANDEN_SHIFT 2
1225#define M98090_EQ3BANDEN_WIDTH 1
1226#define M98090_EQ3BANDEN_NUM (1<<M98090_EQ3BANDEN_WIDTH)
1227#define M98090_EQ5BANDEN_MASK (1<<1)
1228#define M98090_EQ5BANDEN_SHIFT 1
1229#define M98090_EQ5BANDEN_WIDTH 1
1230#define M98090_EQ5BANDEN_NUM (1<<M98090_EQ5BANDEN_WIDTH)
1231#define M98090_EQ7BANDEN_MASK (1<<0)
1232#define M98090_EQ7BANDEN_SHIFT 0
1233#define M98090_EQ7BANDEN_WIDTH 1
1234#define M98090_EQ7BANDEN_NUM (1<<M98090_EQ7BANDEN_WIDTH)
1235
1236/*
1237 * M98090_REG_BIAS_CONTROL
1238 */
1239#define M98090_VCM_MODE_MASK (1<<0)
1240#define M98090_VCM_MODE_SHIFT 0
1241#define M98090_VCM_MODE_WIDTH 1
1242#define M98090_VCM_MODE_NUM (1<<M98090_VCM_MODE_WIDTH)
1243
1244/*
1245 * M98090_REG_DAC_CONTROL
1246 */
1247#define M98090_PERFMODE_MASK (1<<1)
1248#define M98090_PERFMODE_SHIFT 1
1249#define M98090_PERFMODE_WIDTH 1
1250#define M98090_PERFMODE_NUM (1<<M98090_PERFMODE_WIDTH)
1251#define M98090_DACHP_MASK (1<<0)
1252#define M98090_DACHP_SHIFT 0
1253#define M98090_DACHP_WIDTH 1
1254#define M98090_DACHP_NUM (1<<M98090_DACHP_WIDTH)
1255
1256/*
1257 * M98090_REG_ADC_CONTROL
1258 */
1259#define M98090_OSR128_MASK (1<<2)
1260#define M98090_OSR128_SHIFT 2
1261#define M98090_OSR128_WIDTH 1
1262#define M98090_ADCDITHER_MASK (1<<1)
1263#define M98090_ADCDITHER_SHIFT 1
1264#define M98090_ADCDITHER_WIDTH 1
1265#define M98090_ADCDITHER_NUM (1<<M98090_ADCDITHER_WIDTH)
1266#define M98090_ADCHP_MASK (1<<0)
1267#define M98090_ADCHP_SHIFT 0
1268#define M98090_ADCHP_WIDTH 1
1269#define M98090_ADCHP_NUM (1<<M98090_ADCHP_WIDTH)
1270
1271/*
1272 * M98090_REG_DEVICE_SHUTDOWN
1273 */
1274#define M98090_SHDNN_MASK (1<<7)
1275#define M98090_SHDNN_SHIFT 7
1276#define M98090_SHDNN_WIDTH 1
1277
1278/*
1279 * M98090_REG_EQUALIZER_BASE
1280 */
1281#define M98090_B0_1_HI_MASK (255<<0)
1282#define M98090_B0_1_HI_SHIFT 0
1283#define M98090_B0_1_HI_WIDTH 8
1284#define M98090_B0_1_MID_MASK (255<<0)
1285#define M98090_B0_1_MID_SHIFT 0
1286#define M98090_B0_1_MID_WIDTH 8
1287#define M98090_B0_1_LO_MASK (255<<0)
1288#define M98090_B0_1_LO_SHIFT 0
1289#define M98090_B0_1_LO_WIDTH 8
1290#define M98090_B1_1_HI_MASK (255<<0)
1291#define M98090_B1_1_HI_SHIFT 0
1292#define M98090_B1_1_HI_WIDTH 8
1293#define M98090_B1_1_MID_MASK (255<<0)
1294#define M98090_B1_1_MID_SHIFT 0
1295#define M98090_B1_1_MID_WIDTH 8
1296#define M98090_B1_1_LO_MASK (255<<0)
1297#define M98090_B1_1_LO_SHIFT 0
1298#define M98090_B1_1_LO_WIDTH 8
1299#define M98090_B2_1_HI_MASK (255<<0)
1300#define M98090_B2_1_HI_SHIFT 0
1301#define M98090_B2_1_HI_WIDTH 8
1302#define M98090_B2_1_MID_MASK (255<<0)
1303#define M98090_B2_1_MID_SHIFT 0
1304#define M98090_B2_1_MID_WIDTH 8
1305#define M98090_B2_1_LO_MASK (255<<0)
1306#define M98090_B2_1_LO_SHIFT 0
1307#define M98090_B2_1_LO_WIDTH 8
1308#define M98090_A1_1_HI_MASK (255<<0)
1309#define M98090_A1_1_HI_SHIFT 0
1310#define M98090_A1_1_HI_WIDTH 8
1311#define M98090_A1_1_MID_MASK (255<<0)
1312#define M98090_A1_1_MID_SHIFT 0
1313#define M98090_A1_1_MID_WIDTH 8
1314#define M98090_A1_1_LO_MASK (255<<0)
1315#define M98090_A1_1_LO_SHIFT 0
1316#define M98090_A1_1_LO_WIDTH 8
1317#define M98090_A2_1_HI_MASK (255<<0)
1318#define M98090_A2_1_HI_SHIFT 0
1319#define M98090_A2_1_HI_WIDTH 8
1320#define M98090_A2_1_MID_MASK (255<<0)
1321#define M98090_A2_1_MID_SHIFT 0
1322#define M98090_A2_1_MID_WIDTH 8
1323#define M98090_A2_1_LO_MASK (255<<0)
1324#define M98090_A2_1_LO_SHIFT 0
1325#define M98090_A2_1_LO_WIDTH 8
1326
1327#define M98090_COEFS_PER_BAND 5
1328#define M98090_COEFS_BLK_SZ (M98090_COEFS_PER_BAND * 3)
1329#define M98090_COEFS_MAX_SZ (M98090_COEFS_BLK_SZ * 7)
1330
1331/*
1332 * M98090_REG_RECORD_BIQUAD_BASE
1333 */
1334#define M98090_REC_B0_HI_MASK (255<<0)
1335#define M98090_REC_B0_HI_SHIFT 0
1336#define M98090_REC_B0_HI_WIDTH 8
1337#define M98090_REC_B0_MID_MASK (255<<0)
1338#define M98090_REC_B0_MID_SHIFT 0
1339#define M98090_REC_B0_MID_WIDTH 8
1340#define M98090_REC_B0_LO_MASK (255<<0)
1341#define M98090_REC_B0_LO_SHIFT 0
1342#define M98090_REC_B0_LO_WIDTH 8
1343#define M98090_REC_B1_HI_MASK (255<<0)
1344#define M98090_REC_B1_HI_SHIFT 0
1345#define M98090_REC_B1_HI_WIDTH 8
1346#define M98090_REC_B1_MID_MASK (255<<0)
1347#define M98090_REC_B1_MID_SHIFT 0
1348#define M98090_REC_B1_MID_WIDTH 8
1349#define M98090_REC_B1_LO_MASK (255<<0)
1350#define M98090_REC_B1_LO_SHIFT 0
1351#define M98090_REC_B1_LO_WIDTH 8
1352#define M98090_REC_B2_HI_MASK (255<<0)
1353#define M98090_REC_B2_HI_SHIFT 0
1354#define M98090_REC_B2_HI_WIDTH 8
1355#define M98090_REC_B2_MID_MASK (255<<0)
1356#define M98090_REC_B2_MID_SHIFT 0
1357#define M98090_REC_B2_MID_WIDTH 8
1358#define M98090_REC_B2_LO_MASK (255<<0)
1359#define M98090_REC_B2_LO_SHIFT 0
1360#define M98090_REC_B2_LO_WIDTH 8
1361#define M98090_REC_A1_HI_MASK (255<<0)
1362#define M98090_REC_A1_HI_SHIFT 0
1363#define M98090_REC_A1_HI_WIDTH 8
1364#define M98090_REC_A1_MID_MASK (255<<0)
1365#define M98090_REC_A1_MID_SHIFT 0
1366#define M98090_REC_A1_MID_WIDTH 8
1367#define M98090_REC_A1_LO_MASK (255<<0)
1368#define M98090_REC_A1_LO_SHIFT 0
1369#define M98090_REC_A1_LO_WIDTH 8
1370#define M98090_REC_A2_HI_MASK (255<<0)
1371#define M98090_REC_A2_HI_SHIFT 0
1372#define M98090_REC_A2_HI_WIDTH 8
1373#define M98090_REC_A2_MID_MASK (255<<0)
1374#define M98090_REC_A2_MID_SHIFT 0
1375#define M98090_REC_A2_MID_WIDTH 8
1376#define M98090_REC_A2_LO_MASK (255<<0)
1377#define M98090_REC_A2_LO_SHIFT 0
1378#define M98090_REC_A2_LO_WIDTH 8
1379
1380/*
1381 * M98090_REG_DMIC3_VOLUME
1382 */
1383#define M98090_DMIC_AV3G_MASK (7<<4)
1384#define M98090_DMIC_AV3G_SHIFT 4
1385#define M98090_DMIC_AV3G_WIDTH 3
1386#define M98090_DMIC_AV3G_NUM (1<<M98090_DMIC_AV3G_WIDTH)
1387#define M98090_DMIC_AV3_MASK (15<<0)
1388#define M98090_DMIC_AV3_SHIFT 0
1389#define M98090_DMIC_AV3_WIDTH 4
1390#define M98090_DMIC_AV3_NUM (1<<M98090_DMIC_AV3_WIDTH)
1391
1392/*
1393 * M98090_REG_DMIC4_VOLUME
1394 */
1395#define M98090_DMIC_AV4G_MASK (7<<4)
1396#define M98090_DMIC_AV4G_SHIFT 4
1397#define M98090_DMIC_AV4G_WIDTH 3
1398#define M98090_DMIC_AV4G_NUM (1<<M98090_DMIC_AV4G_WIDTH)
1399#define M98090_DMIC_AV4_MASK (15<<0)
1400#define M98090_DMIC_AV4_SHIFT 0
1401#define M98090_DMIC_AV4_WIDTH 4
1402#define M98090_DMIC_AV4_NUM (1<<M98090_DMIC_AV4_WIDTH)
1403
1404/*
1405 * M98090_REG_DMIC34_BQ_PREATTEN
1406 */
1407#define M98090_AV34BQ_MASK (15<<0)
1408#define M98090_AV34BQ_SHIFT 0
1409#define M98090_AV34BQ_WIDTH 4
1410#define M98090_AV34BQ_NUM (1<<M98090_AV34BQ_WIDTH)
1411
1412/*
1413 * M98090_REG_RECORD_TDM_SLOT
1414 */
1415#define M98090_TDM_SLOTADCL_MASK (3<<6)
1416#define M98090_TDM_SLOTADCL_SHIFT 6
1417#define M98090_TDM_SLOTADCL_WIDTH 2
1418#define M98090_TDM_SLOTADCL_NUM (1<<M98090_TDM_SLOTADCL_WIDTH)
1419#define M98090_TDM_SLOTADCR_MASK (3<<4)
1420#define M98090_TDM_SLOTADCR_SHIFT 4
1421#define M98090_TDM_SLOTADCR_WIDTH 2
1422#define M98090_TDM_SLOTADCR_NUM (1<<M98090_TDM_SLOTADCR_WIDTH)
1423#define M98090_TDM_SLOTDMIC3_MASK (3<<2)
1424#define M98090_TDM_SLOTDMIC3_SHIFT 2
1425#define M98090_TDM_SLOTDMIC3_WIDTH 2
1426#define M98090_TDM_SLOTDMIC3_NUM (1<<M98090_TDM_SLOTDMIC3_WIDTH)
1427#define M98090_TDM_SLOTDMIC4_MASK (3<<0)
1428#define M98090_TDM_SLOTDMIC4_SHIFT 0
1429#define M98090_TDM_SLOTDMIC4_WIDTH 2
1430#define M98090_TDM_SLOTDMIC4_NUM (1<<M98090_TDM_SLOTDMIC4_WIDTH)
1431
1432/*
1433 * M98090_REG_SAMPLE_RATE
1434 */
1435#define M98090_DMIC34_ZEROPAD_MASK (1<<4)
1436#define M98090_DMIC34_ZEROPAD_SHIFT 4
1437#define M98090_DMIC34_ZEROPAD_WIDTH 1
1438#define M98090_DMIC34_ZEROPAD_NUM (1<<M98090_DIGMIC4_WIDTH)
1439#define M98090_DMIC34_SRDIV_MASK (7<<0)
1440#define M98090_DMIC34_SRDIV_SHIFT 0
1441#define M98090_DMIC34_SRDIV_WIDTH 3
1442
1443/*
1444 * M98090_REG_DMIC34_BIQUAD_BASE
1445 */
1446#define M98090_DMIC34_B0_HI_MASK (255<<0)
1447#define M98090_DMIC34_B0_HI_SHIFT 0
1448#define M98090_DMIC34_B0_HI_WIDTH 8
1449#define M98090_DMIC34_B0_MID_MASK (255<<0)
1450#define M98090_DMIC34_B0_MID_SHIFT 0
1451#define M98090_DMIC34_B0_MID_WIDTH 8
1452#define M98090_DMIC34_B0_LO_MASK (255<<0)
1453#define M98090_DMIC34_B0_LO_SHIFT 0
1454#define M98090_DMIC34_B0_LO_WIDTH 8
1455#define M98090_DMIC34_B1_HI_MASK (255<<0)
1456#define M98090_DMIC34_B1_HI_SHIFT 0
1457#define M98090_DMIC34_B1_HI_WIDTH 8
1458#define M98090_DMIC34_B1_MID_MASK (255<<0)
1459#define M98090_DMIC34_B1_MID_SHIFT 0
1460#define M98090_DMIC34_B1_MID_WIDTH 8
1461#define M98090_DMIC34_B1_LO_MASK (255<<0)
1462#define M98090_DMIC34_B1_LO_SHIFT 0
1463#define M98090_DMIC34_B1_LO_WIDTH 8
1464#define M98090_DMIC34_B2_HI_MASK (255<<0)
1465#define M98090_DMIC34_B2_HI_SHIFT 0
1466#define M98090_DMIC34_B2_HI_WIDTH 8
1467#define M98090_DMIC34_B2_MID_MASK (255<<0)
1468#define M98090_DMIC34_B2_MID_SHIFT 0
1469#define M98090_DMIC34_B2_MID_WIDTH 8
1470#define M98090_DMIC34_B2_LO_MASK (255<<0)
1471#define M98090_DMIC34_B2_LO_SHIFT 0
1472#define M98090_DMIC34_B2_LO_WIDTH 8
1473#define M98090_DMIC34_A1_HI_MASK (255<<0)
1474#define M98090_DMIC34_A1_HI_SHIFT 0
1475#define M98090_DMIC34_A1_HI_WIDTH 8
1476#define M98090_DMIC34_A1_MID_MASK (255<<0)
1477#define M98090_DMIC34_A1_MID_SHIFT 0
1478#define M98090_DMIC34_A1_MID_WIDTH 8
1479#define M98090_DMIC34_A1_LO_MASK (255<<0)
1480#define M98090_DMIC34_A1_LO_SHIFT 0
1481#define M98090_DMIC34_A1_LO_WIDTH 8
1482#define M98090_DMIC34_A2_HI_MASK (255<<0)
1483#define M98090_DMIC34_A2_HI_SHIFT 0
1484#define M98090_DMIC34_A2_HI_WIDTH 8
1485#define M98090_DMIC34_A2_MID_MASK (255<<0)
1486#define M98090_DMIC34_A2_MID_SHIFT 0
1487#define M98090_DMIC34_A2_MID_WIDTH 8
1488#define M98090_DMIC34_A2_LO_MASK (255<<0)
1489#define M98090_DMIC34_A2_LO_SHIFT 0
1490#define M98090_DMIC34_A2_LO_WIDTH 8
1491
1492#define M98090_JACK_STATE_NO_HEADSET 0
1493#define M98090_JACK_STATE_NO_HEADSET_2 1
1494#define M98090_JACK_STATE_HEADPHONE 2
1495#define M98090_JACK_STATE_HEADSET 3
1496
1497/*
1498 * M98090_REG_REVISION_ID
1499 */
1500#define M98090_REVID_MASK (255<<0)
1501#define M98090_REVID_SHIFT 0
1502#define M98090_REVID_WIDTH 8
1503#define M98090_REVID_NUM (1<<M98090_REVID_WIDTH)
1504
1505#define M98090_BYTE1(w) ((w >> 8) & 0xff)
1506#define M98090_BYTE0(w) (w & 0xff)
1507
1508/* Silicon revision number */
1509#define M98090_REVA 0x40
1510#define M98091_REVA 0x50
1511
1512enum max98090_type {
1513 MAX98090,
1514 MAX98091,
1515};
1516
1517struct max98090_cdata {
1518 unsigned int rate;
1519 unsigned int fmt;
1520};
1521
1522struct max98090_priv {
1523 struct regmap *regmap;
1524 struct snd_soc_codec *codec;
1525 enum max98090_type devtype;
1526 void *control_data;
1527 struct max98090_pdata *pdata;
1528 unsigned int sysclk;
1529 unsigned int bclk;
1530 unsigned int lrclk;
1531 struct max98090_cdata dai[1];
1532 int irq;
1533 int jack_state;
1534 struct delayed_work jack_work;
1535 struct snd_soc_jack *jack;
1536 unsigned int dai_fmt;
1537 int tdm_slots;
1538 int tdm_width;
1539 u8 lin_state;
1540 unsigned int pa1en;
1541 unsigned int pa2en;
1542 unsigned int extmic_mux;
1543 unsigned int sidetone;
1544};
1545
1546int max98090_mic_detect(struct snd_soc_codec *codec,
1547 struct snd_soc_jack *jack);
1548
1549#endif
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 5708a973a776..65d09d60b7c6 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -85,6 +85,9 @@ struct aic3x_priv {
85#define AIC3X_MODEL_33 1 85#define AIC3X_MODEL_33 1
86#define AIC3X_MODEL_3007 2 86#define AIC3X_MODEL_3007 2
87 u16 model; 87 u16 model;
88
89 /* Selects the micbias voltage */
90 enum aic3x_micbias_voltage micbias_vg;
88}; 91};
89 92
90/* 93/*
@@ -195,6 +198,37 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
195 return ret; 198 return ret;
196} 199}
197 200
201/*
202 * mic bias power on/off share the same register bits with
203 * output voltage of mic bias. when power on mic bias, we
204 * need reclaim it to voltage value.
205 * 0x0 = Powered off
206 * 0x1 = MICBIAS output is powered to 2.0V,
207 * 0x2 = MICBIAS output is powered to 2.5V
208 * 0x3 = MICBIAS output is connected to AVDD
209 */
210static int mic_bias_event(struct snd_soc_dapm_widget *w,
211 struct snd_kcontrol *kcontrol, int event)
212{
213 struct snd_soc_codec *codec = w->codec;
214 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
215
216 switch (event) {
217 case SND_SOC_DAPM_POST_PMU:
218 /* change mic bias voltage to user defined */
219 snd_soc_update_bits(codec, MICBIAS_CTRL,
220 MICBIAS_LEVEL_MASK,
221 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
222 break;
223
224 case SND_SOC_DAPM_PRE_PMD:
225 snd_soc_update_bits(codec, MICBIAS_CTRL,
226 MICBIAS_LEVEL_MASK, 0);
227 break;
228 }
229 return 0;
230}
231
198static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; 232static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
199static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; 233static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
200static const char *aic3x_left_hpcom_mux[] = 234static const char *aic3x_left_hpcom_mux[] =
@@ -596,12 +630,9 @@ static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
596 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), 630 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
597 631
598 /* Mic Bias */ 632 /* Mic Bias */
599 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V", 633 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
600 MICBIAS_CTRL, 6, 3, 1, 0), 634 mic_bias_event,
601 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V", 635 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
602 MICBIAS_CTRL, 6, 3, 2, 0),
603 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
604 MICBIAS_CTRL, 6, 3, 3, 0),
605 636
606 /* Output mixers */ 637 /* Output mixers */
607 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 638 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
@@ -1210,13 +1241,13 @@ static struct snd_soc_dai_driver aic3x_dai = {
1210 .name = "tlv320aic3x-hifi", 1241 .name = "tlv320aic3x-hifi",
1211 .playback = { 1242 .playback = {
1212 .stream_name = "Playback", 1243 .stream_name = "Playback",
1213 .channels_min = 1, 1244 .channels_min = 2,
1214 .channels_max = 2, 1245 .channels_max = 2,
1215 .rates = AIC3X_RATES, 1246 .rates = AIC3X_RATES,
1216 .formats = AIC3X_FORMATS,}, 1247 .formats = AIC3X_FORMATS,},
1217 .capture = { 1248 .capture = {
1218 .stream_name = "Capture", 1249 .stream_name = "Capture",
1219 .channels_min = 1, 1250 .channels_min = 2,
1220 .channels_max = 2, 1251 .channels_max = 2,
1221 .rates = AIC3X_RATES, 1252 .rates = AIC3X_RATES,
1222 .formats = AIC3X_FORMATS,}, 1253 .formats = AIC3X_FORMATS,},
@@ -1386,6 +1417,24 @@ static int aic3x_probe(struct snd_soc_codec *codec)
1386 if (aic3x->model == AIC3X_MODEL_3007) 1417 if (aic3x->model == AIC3X_MODEL_3007)
1387 snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1); 1418 snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
1388 1419
1420 /* set mic bias voltage */
1421 switch (aic3x->micbias_vg) {
1422 case AIC3X_MICBIAS_2_0V:
1423 case AIC3X_MICBIAS_2_5V:
1424 case AIC3X_MICBIAS_AVDDV:
1425 snd_soc_update_bits(codec, MICBIAS_CTRL,
1426 MICBIAS_LEVEL_MASK,
1427 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1428 break;
1429 case AIC3X_MICBIAS_OFF:
1430 /*
1431 * noting to do. target won't enter here. This is just to avoid
1432 * compile time warning "warning: enumeration value
1433 * 'AIC3X_MICBIAS_OFF' not handled in switch"
1434 */
1435 break;
1436 }
1437
1389 aic3x_add_widgets(codec); 1438 aic3x_add_widgets(codec);
1390 list_add(&aic3x->list, &reset_list); 1439 list_add(&aic3x->list, &reset_list);
1391 1440
@@ -1461,6 +1510,7 @@ static int aic3x_i2c_probe(struct i2c_client *i2c,
1461 struct aic3x_setup_data *ai3x_setup; 1510 struct aic3x_setup_data *ai3x_setup;
1462 struct device_node *np = i2c->dev.of_node; 1511 struct device_node *np = i2c->dev.of_node;
1463 int ret; 1512 int ret;
1513 u32 value;
1464 1514
1465 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL); 1515 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
1466 if (aic3x == NULL) { 1516 if (aic3x == NULL) {
@@ -1474,6 +1524,7 @@ static int aic3x_i2c_probe(struct i2c_client *i2c,
1474 if (pdata) { 1524 if (pdata) {
1475 aic3x->gpio_reset = pdata->gpio_reset; 1525 aic3x->gpio_reset = pdata->gpio_reset;
1476 aic3x->setup = pdata->setup; 1526 aic3x->setup = pdata->setup;
1527 aic3x->micbias_vg = pdata->micbias_vg;
1477 } else if (np) { 1528 } else if (np) {
1478 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup), 1529 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
1479 GFP_KERNEL); 1530 GFP_KERNEL);
@@ -1493,6 +1544,26 @@ static int aic3x_i2c_probe(struct i2c_client *i2c,
1493 aic3x->setup = ai3x_setup; 1544 aic3x->setup = ai3x_setup;
1494 } 1545 }
1495 1546
1547 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1548 switch (value) {
1549 case 1 :
1550 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1551 break;
1552 case 2 :
1553 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1554 break;
1555 case 3 :
1556 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1557 break;
1558 default :
1559 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1560 dev_err(&i2c->dev, "Unsuitable MicBias voltage "
1561 "found in DT\n");
1562 }
1563 } else {
1564 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1565 }
1566
1496 } else { 1567 } else {
1497 aic3x->gpio_reset = -1; 1568 aic3x->gpio_reset = -1;
1498 } 1569 }
diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h
index 6db3c41b0163..e521ac3ddde8 100644
--- a/sound/soc/codecs/tlv320aic3x.h
+++ b/sound/soc/codecs/tlv320aic3x.h
@@ -238,6 +238,10 @@
238/* Default input volume */ 238/* Default input volume */
239#define DEFAULT_GAIN 0x20 239#define DEFAULT_GAIN 0x20
240 240
241/* MICBIAS Control Register */
242#define MICBIAS_LEVEL_SHIFT (6)
243#define MICBIAS_LEVEL_MASK (3 << 6)
244
241/* headset detection / button API */ 245/* headset detection / button API */
242 246
243/* The AIC3x supports detection of stereo headsets (GND + left + right signal) 247/* The AIC3x supports detection of stereo headsets (GND + left + right signal)
diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c
index 782b0cded2e6..4f358393d6d6 100644
--- a/sound/soc/codecs/tlv320dac33.c
+++ b/sound/soc/codecs/tlv320dac33.c
@@ -1452,20 +1452,6 @@ static int dac33_soc_remove(struct snd_soc_codec *codec)
1452 return 0; 1452 return 0;
1453} 1453}
1454 1454
1455static int dac33_soc_suspend(struct snd_soc_codec *codec)
1456{
1457 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1458
1459 return 0;
1460}
1461
1462static int dac33_soc_resume(struct snd_soc_codec *codec)
1463{
1464 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1465
1466 return 0;
1467}
1468
1469static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = { 1455static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1470 .read = dac33_read_reg_cache, 1456 .read = dac33_read_reg_cache,
1471 .write = dac33_write_locked, 1457 .write = dac33_write_locked,
@@ -1476,8 +1462,6 @@ static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1476 .reg_cache_default = dac33_reg, 1462 .reg_cache_default = dac33_reg,
1477 .probe = dac33_soc_probe, 1463 .probe = dac33_soc_probe,
1478 .remove = dac33_soc_remove, 1464 .remove = dac33_soc_remove,
1479 .suspend = dac33_soc_suspend,
1480 .resume = dac33_soc_resume,
1481 1465
1482 .controls = dac33_snd_controls, 1466 .controls = dac33_snd_controls,
1483 .num_controls = ARRAY_SIZE(dac33_snd_controls), 1467 .num_controls = ARRAY_SIZE(dac33_snd_controls),
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 63b280b06035..8e6e5b016021 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -41,6 +41,11 @@
41/* Register descriptions are here */ 41/* Register descriptions are here */
42#include <linux/mfd/twl4030-audio.h> 42#include <linux/mfd/twl4030-audio.h>
43 43
44/* TWL4030 PMBR1 Register */
45#define TWL4030_PMBR1_REG 0x0D
46/* TWL4030 PMBR1 Register GPIO6 mux bits */
47#define TWL4030_GPIO6_PWM0_MUTE(value) ((value & 0x03) << 2)
48
44/* Shadow register used by the audio driver */ 49/* Shadow register used by the audio driver */
45#define TWL4030_REG_SW_SHADOW 0x4A 50#define TWL4030_REG_SW_SHADOW 0x4A
46#define TWL4030_CACHEREGNUM (TWL4030_REG_SW_SHADOW + 1) 51#define TWL4030_CACHEREGNUM (TWL4030_REG_SW_SHADOW + 1)
@@ -348,19 +353,32 @@ static void twl4030_init_chip(struct snd_soc_codec *codec)
348 353
349 pdata = twl4030_get_pdata(codec); 354 pdata = twl4030_get_pdata(codec);
350 355
351 if (pdata && pdata->hs_extmute && 356 if (pdata && pdata->hs_extmute) {
352 gpio_is_valid(pdata->hs_extmute_gpio)) { 357 if (gpio_is_valid(pdata->hs_extmute_gpio)) {
353 int ret; 358 int ret;
354 359
355 if (!pdata->hs_extmute_gpio) 360 if (!pdata->hs_extmute_gpio)
356 dev_warn(codec->dev, 361 dev_warn(codec->dev,
357 "Extmute GPIO is 0 is this correct?\n"); 362 "Extmute GPIO is 0 is this correct?\n");
358 363
359 ret = gpio_request_one(pdata->hs_extmute_gpio, 364 ret = gpio_request_one(pdata->hs_extmute_gpio,
360 GPIOF_OUT_INIT_LOW, "hs_extmute"); 365 GPIOF_OUT_INIT_LOW,
361 if (ret) { 366 "hs_extmute");
362 dev_err(codec->dev, "Failed to get hs_extmute GPIO\n"); 367 if (ret) {
363 pdata->hs_extmute_gpio = -1; 368 dev_err(codec->dev,
369 "Failed to get hs_extmute GPIO\n");
370 pdata->hs_extmute_gpio = -1;
371 }
372 } else {
373 u8 pin_mux;
374
375 /* Set TWL4030 GPIO6 as EXTMUTE signal */
376 twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux,
377 TWL4030_PMBR1_REG);
378 pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03);
379 pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02);
380 twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux,
381 TWL4030_PMBR1_REG);
364 } 382 }
365 } 383 }
366 384
@@ -1306,6 +1324,9 @@ static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1306 SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0), 1324 SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1307 SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0), 1325 SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
1308 1326
1327 SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0,
1328 TWL4030_REG_VOICE_IF, 6, 0),
1329
1309 /* Analog bypasses */ 1330 /* Analog bypasses */
1310 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0, 1331 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1311 &twl4030_dapm_abypassr1_control), 1332 &twl4030_dapm_abypassr1_control),
@@ -1438,6 +1459,9 @@ static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1438 SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0), 1459 SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1439 SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0), 1460 SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
1440 1461
1462 SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0,
1463 TWL4030_REG_VOICE_IF, 5, 0),
1464
1441 /* Analog/Digital mic path selection. 1465 /* Analog/Digital mic path selection.
1442 TX1 Left/Right: either analog Left/Right or Digimic0 1466 TX1 Left/Right: either analog Left/Right or Digimic0
1443 TX2 Left/Right: either analog Left/Right or Digimic1 */ 1467 TX2 Left/Right: either analog Left/Right or Digimic1 */
@@ -1473,10 +1497,15 @@ static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1473 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0, 1497 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1474 NULL, 0), 1498 NULL, 0),
1475 1499
1476 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0), 1500 /* Microphone bias */
1477 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0), 1501 SND_SOC_DAPM_SUPPLY("Mic Bias 1",
1478 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0), 1502 TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0),
1503 SND_SOC_DAPM_SUPPLY("Mic Bias 2",
1504 TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0),
1505 SND_SOC_DAPM_SUPPLY("Headset Mic Bias",
1506 TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0),
1479 1507
1508 SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0),
1480}; 1509};
1481 1510
1482static const struct snd_soc_dapm_route intercon[] = { 1511static const struct snd_soc_dapm_route intercon[] = {
@@ -1485,17 +1514,16 @@ static const struct snd_soc_dapm_route intercon[] = {
1485 {"DAC Left1", NULL, "HiFi Playback"}, 1514 {"DAC Left1", NULL, "HiFi Playback"},
1486 {"DAC Right2", NULL, "HiFi Playback"}, 1515 {"DAC Right2", NULL, "HiFi Playback"},
1487 {"DAC Left2", NULL, "HiFi Playback"}, 1516 {"DAC Left2", NULL, "HiFi Playback"},
1488 {"DAC Voice", NULL, "Voice Playback"}, 1517 {"DAC Voice", NULL, "VAIFIN"},
1489 1518
1490 /* ADC -> Stream mapping */ 1519 /* ADC -> Stream mapping */
1491 {"HiFi Capture", NULL, "ADC Virtual Left1"}, 1520 {"HiFi Capture", NULL, "ADC Virtual Left1"},
1492 {"HiFi Capture", NULL, "ADC Virtual Right1"}, 1521 {"HiFi Capture", NULL, "ADC Virtual Right1"},
1493 {"HiFi Capture", NULL, "ADC Virtual Left2"}, 1522 {"HiFi Capture", NULL, "ADC Virtual Left2"},
1494 {"HiFi Capture", NULL, "ADC Virtual Right2"}, 1523 {"HiFi Capture", NULL, "ADC Virtual Right2"},
1495 {"Voice Capture", NULL, "ADC Virtual Left1"}, 1524 {"VAIFOUT", NULL, "ADC Virtual Left2"},
1496 {"Voice Capture", NULL, "ADC Virtual Right1"}, 1525 {"VAIFOUT", NULL, "ADC Virtual Right2"},
1497 {"Voice Capture", NULL, "ADC Virtual Left2"}, 1526 {"VAIFOUT", NULL, "VIF Enable"},
1498 {"Voice Capture", NULL, "ADC Virtual Right2"},
1499 1527
1500 {"Digital L1 Playback Mixer", NULL, "DAC Left1"}, 1528 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1501 {"Digital R1 Playback Mixer", NULL, "DAC Right1"}, 1529 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
@@ -1510,6 +1538,7 @@ static const struct snd_soc_dapm_route intercon[] = {
1510 {"DAC Right1", NULL, "AIF Enable"}, 1538 {"DAC Right1", NULL, "AIF Enable"},
1511 {"DAC Left2", NULL, "AIF Enable"}, 1539 {"DAC Left2", NULL, "AIF Enable"},
1512 {"DAC Right1", NULL, "AIF Enable"}, 1540 {"DAC Right1", NULL, "AIF Enable"},
1541 {"DAC Voice", NULL, "VIF Enable"},
1513 1542
1514 {"Digital R2 Playback Mixer", NULL, "AIF Enable"}, 1543 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1515 {"Digital L2 Playback Mixer", NULL, "AIF Enable"}, 1544 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
@@ -2267,18 +2296,6 @@ static struct snd_soc_dai_driver twl4030_dai[] = {
2267}, 2296},
2268}; 2297};
2269 2298
2270static int twl4030_soc_suspend(struct snd_soc_codec *codec)
2271{
2272 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2273 return 0;
2274}
2275
2276static int twl4030_soc_resume(struct snd_soc_codec *codec)
2277{
2278 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2279 return 0;
2280}
2281
2282static int twl4030_soc_probe(struct snd_soc_codec *codec) 2299static int twl4030_soc_probe(struct snd_soc_codec *codec)
2283{ 2300{
2284 struct twl4030_priv *twl4030; 2301 struct twl4030_priv *twl4030;
@@ -2316,8 +2333,6 @@ static int twl4030_soc_remove(struct snd_soc_codec *codec)
2316static struct snd_soc_codec_driver soc_codec_dev_twl4030 = { 2333static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2317 .probe = twl4030_soc_probe, 2334 .probe = twl4030_soc_probe,
2318 .remove = twl4030_soc_remove, 2335 .remove = twl4030_soc_remove,
2319 .suspend = twl4030_soc_suspend,
2320 .resume = twl4030_soc_resume,
2321 .read = twl4030_read_reg_cache, 2336 .read = twl4030_read_reg_cache,
2322 .write = twl4030_write, 2337 .write = twl4030_write,
2323 .set_bias_level = twl4030_set_bias_level, 2338 .set_bias_level = twl4030_set_bias_level,
diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c
index 3fc3fc64dd8b..9b9a6e587610 100644
--- a/sound/soc/codecs/twl6040.c
+++ b/sound/soc/codecs/twl6040.c
@@ -69,13 +69,8 @@ struct twl6040_data {
69 int hs_power_mode_locked; 69 int hs_power_mode_locked;
70 unsigned int clk_in; 70 unsigned int clk_in;
71 unsigned int sysclk; 71 unsigned int sysclk;
72 u16 hs_left_step;
73 u16 hs_right_step;
74 u16 hf_left_step;
75 u16 hf_right_step;
76 struct twl6040_jack_data hs_jack; 72 struct twl6040_jack_data hs_jack;
77 struct snd_soc_codec *codec; 73 struct snd_soc_codec *codec;
78 struct workqueue_struct *workqueue;
79 struct mutex mutex; 74 struct mutex mutex;
80}; 75};
81 76
@@ -404,8 +399,7 @@ static irqreturn_t twl6040_audio_handler(int irq, void *data)
404 struct snd_soc_codec *codec = data; 399 struct snd_soc_codec *codec = data;
405 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); 400 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
406 401
407 queue_delayed_work(priv->workqueue, &priv->hs_jack.work, 402 schedule_delayed_work(&priv->hs_jack.work, msecs_to_jiffies(200));
408 msecs_to_jiffies(200));
409 403
410 return IRQ_HANDLED; 404 return IRQ_HANDLED;
411} 405}
@@ -1115,7 +1109,6 @@ static int twl6040_suspend(struct snd_soc_codec *codec)
1115static int twl6040_resume(struct snd_soc_codec *codec) 1109static int twl6040_resume(struct snd_soc_codec *codec)
1116{ 1110{
1117 twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1111 twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1118 twl6040_set_bias_level(codec, codec->dapm.suspend_bias_level);
1119 1112
1120 return 0; 1113 return 0;
1121} 1114}
@@ -1127,83 +1120,46 @@ static int twl6040_resume(struct snd_soc_codec *codec)
1127static int twl6040_probe(struct snd_soc_codec *codec) 1120static int twl6040_probe(struct snd_soc_codec *codec)
1128{ 1121{
1129 struct twl6040_data *priv; 1122 struct twl6040_data *priv;
1130 struct twl6040_codec_data *pdata = dev_get_platdata(codec->dev);
1131 struct platform_device *pdev = container_of(codec->dev, 1123 struct platform_device *pdev = container_of(codec->dev,
1132 struct platform_device, dev); 1124 struct platform_device, dev);
1133 int ret = 0; 1125 int ret = 0;
1134 1126
1135 priv = kzalloc(sizeof(struct twl6040_data), GFP_KERNEL); 1127 priv = devm_kzalloc(codec->dev, sizeof(*priv), GFP_KERNEL);
1136 if (priv == NULL) 1128 if (priv == NULL)
1137 return -ENOMEM; 1129 return -ENOMEM;
1130
1138 snd_soc_codec_set_drvdata(codec, priv); 1131 snd_soc_codec_set_drvdata(codec, priv);
1139 1132
1140 priv->codec = codec; 1133 priv->codec = codec;
1141 codec->control_data = dev_get_drvdata(codec->dev->parent); 1134 codec->control_data = dev_get_drvdata(codec->dev->parent);
1142 1135
1143 if (pdata && pdata->hs_left_step && pdata->hs_right_step) {
1144 priv->hs_left_step = pdata->hs_left_step;
1145 priv->hs_right_step = pdata->hs_right_step;
1146 } else {
1147 priv->hs_left_step = 1;
1148 priv->hs_right_step = 1;
1149 }
1150
1151 if (pdata && pdata->hf_left_step && pdata->hf_right_step) {
1152 priv->hf_left_step = pdata->hf_left_step;
1153 priv->hf_right_step = pdata->hf_right_step;
1154 } else {
1155 priv->hf_left_step = 1;
1156 priv->hf_right_step = 1;
1157 }
1158
1159 priv->plug_irq = platform_get_irq(pdev, 0); 1136 priv->plug_irq = platform_get_irq(pdev, 0);
1160 if (priv->plug_irq < 0) { 1137 if (priv->plug_irq < 0) {
1161 dev_err(codec->dev, "invalid irq\n"); 1138 dev_err(codec->dev, "invalid irq\n");
1162 ret = -EINVAL; 1139 return -EINVAL;
1163 goto work_err;
1164 }
1165
1166 priv->workqueue = alloc_workqueue("twl6040-codec", 0, 0);
1167 if (!priv->workqueue) {
1168 ret = -ENOMEM;
1169 goto work_err;
1170 } 1140 }
1171 1141
1172 INIT_DELAYED_WORK(&priv->hs_jack.work, twl6040_accessory_work); 1142 INIT_DELAYED_WORK(&priv->hs_jack.work, twl6040_accessory_work);
1173 1143
1174 mutex_init(&priv->mutex); 1144 mutex_init(&priv->mutex);
1175 1145
1176 ret = request_threaded_irq(priv->plug_irq, NULL, twl6040_audio_handler, 1146 ret = devm_request_threaded_irq(codec->dev, priv->plug_irq, NULL,
1177 0, "twl6040_irq_plug", codec); 1147 twl6040_audio_handler, IRQF_NO_SUSPEND,
1148 "twl6040_irq_plug", codec);
1178 if (ret) { 1149 if (ret) {
1179 dev_err(codec->dev, "PLUG IRQ request failed: %d\n", ret); 1150 dev_err(codec->dev, "PLUG IRQ request failed: %d\n", ret);
1180 goto plugirq_err; 1151 return ret;
1181 } 1152 }
1182 1153
1183 twl6040_init_chip(codec); 1154 twl6040_init_chip(codec);
1184 1155
1185 /* power on device */ 1156 /* power on device */
1186 ret = twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1157 return twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1187 if (!ret)
1188 return 0;
1189
1190 /* Error path */
1191 free_irq(priv->plug_irq, codec);
1192plugirq_err:
1193 destroy_workqueue(priv->workqueue);
1194work_err:
1195 kfree(priv);
1196 return ret;
1197} 1158}
1198 1159
1199static int twl6040_remove(struct snd_soc_codec *codec) 1160static int twl6040_remove(struct snd_soc_codec *codec)
1200{ 1161{
1201 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
1202
1203 twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF); 1162 twl6040_set_bias_level(codec, SND_SOC_BIAS_OFF);
1204 free_irq(priv->plug_irq, codec);
1205 destroy_workqueue(priv->workqueue);
1206 kfree(priv);
1207 1163
1208 return 0; 1164 return 0;
1209} 1165}
diff --git a/sound/soc/codecs/wm2000.c b/sound/soc/codecs/wm2000.c
index 12bcae63a7f0..f2ac38b61a1b 100644
--- a/sound/soc/codecs/wm2000.c
+++ b/sound/soc/codecs/wm2000.c
@@ -26,6 +26,7 @@
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/init.h> 27#include <linux/init.h>
28#include <linux/firmware.h> 28#include <linux/firmware.h>
29#include <linux/clk.h>
29#include <linux/delay.h> 30#include <linux/delay.h>
30#include <linux/pm.h> 31#include <linux/pm.h>
31#include <linux/i2c.h> 32#include <linux/i2c.h>
@@ -62,6 +63,7 @@ enum wm2000_anc_mode {
62struct wm2000_priv { 63struct wm2000_priv {
63 struct i2c_client *i2c; 64 struct i2c_client *i2c;
64 struct regmap *regmap; 65 struct regmap *regmap;
66 struct clk *mclk;
65 67
66 struct regulator_bulk_data supplies[WM2000_NUM_SUPPLIES]; 68 struct regulator_bulk_data supplies[WM2000_NUM_SUPPLIES];
67 69
@@ -71,11 +73,12 @@ struct wm2000_priv {
71 unsigned int anc_eng_ena:1; 73 unsigned int anc_eng_ena:1;
72 unsigned int spk_ena:1; 74 unsigned int spk_ena:1;
73 75
74 unsigned int mclk_div:1;
75 unsigned int speech_clarity:1; 76 unsigned int speech_clarity:1;
76 77
77 int anc_download_size; 78 int anc_download_size;
78 char *anc_download; 79 char *anc_download;
80
81 struct mutex lock;
79}; 82};
80 83
81static int wm2000_write(struct i2c_client *i2c, unsigned int reg, 84static int wm2000_write(struct i2c_client *i2c, unsigned int reg,
@@ -131,6 +134,7 @@ static int wm2000_poll_bit(struct i2c_client *i2c,
131static int wm2000_power_up(struct i2c_client *i2c, int analogue) 134static int wm2000_power_up(struct i2c_client *i2c, int analogue)
132{ 135{
133 struct wm2000_priv *wm2000 = dev_get_drvdata(&i2c->dev); 136 struct wm2000_priv *wm2000 = dev_get_drvdata(&i2c->dev);
137 unsigned long rate;
134 int ret; 138 int ret;
135 139
136 BUG_ON(wm2000->anc_mode != ANC_OFF); 140 BUG_ON(wm2000->anc_mode != ANC_OFF);
@@ -143,7 +147,8 @@ static int wm2000_power_up(struct i2c_client *i2c, int analogue)
143 return ret; 147 return ret;
144 } 148 }
145 149
146 if (!wm2000->mclk_div) { 150 rate = clk_get_rate(wm2000->mclk);
151 if (rate <= 13500000) {
147 dev_dbg(&i2c->dev, "Disabling MCLK divider\n"); 152 dev_dbg(&i2c->dev, "Disabling MCLK divider\n");
148 wm2000_write(i2c, WM2000_REG_SYS_CTL2, 153 wm2000_write(i2c, WM2000_REG_SYS_CTL2,
149 WM2000_MCLK_DIV2_ENA_CLR); 154 WM2000_MCLK_DIV2_ENA_CLR);
@@ -550,6 +555,15 @@ static int wm2000_anc_transition(struct wm2000_priv *wm2000,
550 return -EINVAL; 555 return -EINVAL;
551 } 556 }
552 557
558 /* Maintain clock while active */
559 if (anc_transitions[i].source == ANC_OFF) {
560 ret = clk_prepare_enable(wm2000->mclk);
561 if (ret != 0) {
562 dev_err(&i2c->dev, "Failed to enable MCLK: %d\n", ret);
563 return ret;
564 }
565 }
566
553 for (j = 0; j < ARRAY_SIZE(anc_transitions[j].step); j++) { 567 for (j = 0; j < ARRAY_SIZE(anc_transitions[j].step); j++) {
554 if (!anc_transitions[i].step[j]) 568 if (!anc_transitions[i].step[j])
555 break; 569 break;
@@ -559,7 +573,10 @@ static int wm2000_anc_transition(struct wm2000_priv *wm2000,
559 return ret; 573 return ret;
560 } 574 }
561 575
562 return 0; 576 if (anc_transitions[i].dest == ANC_OFF)
577 clk_disable_unprepare(wm2000->mclk);
578
579 return ret;
563} 580}
564 581
565static int wm2000_anc_set_mode(struct wm2000_priv *wm2000) 582static int wm2000_anc_set_mode(struct wm2000_priv *wm2000)
@@ -599,13 +616,20 @@ static int wm2000_anc_mode_put(struct snd_kcontrol *kcontrol,
599 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 616 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
600 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev); 617 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev);
601 int anc_active = ucontrol->value.enumerated.item[0]; 618 int anc_active = ucontrol->value.enumerated.item[0];
619 int ret;
602 620
603 if (anc_active > 1) 621 if (anc_active > 1)
604 return -EINVAL; 622 return -EINVAL;
605 623
624 mutex_lock(&wm2000->lock);
625
606 wm2000->anc_active = anc_active; 626 wm2000->anc_active = anc_active;
607 627
608 return wm2000_anc_set_mode(wm2000); 628 ret = wm2000_anc_set_mode(wm2000);
629
630 mutex_unlock(&wm2000->lock);
631
632 return ret;
609} 633}
610 634
611static int wm2000_speaker_get(struct snd_kcontrol *kcontrol, 635static int wm2000_speaker_get(struct snd_kcontrol *kcontrol,
@@ -625,16 +649,24 @@ static int wm2000_speaker_put(struct snd_kcontrol *kcontrol,
625 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 649 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
626 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev); 650 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev);
627 int val = ucontrol->value.enumerated.item[0]; 651 int val = ucontrol->value.enumerated.item[0];
652 int ret;
628 653
629 if (val > 1) 654 if (val > 1)
630 return -EINVAL; 655 return -EINVAL;
631 656
657 mutex_lock(&wm2000->lock);
658
632 wm2000->spk_ena = val; 659 wm2000->spk_ena = val;
633 660
634 return wm2000_anc_set_mode(wm2000); 661 ret = wm2000_anc_set_mode(wm2000);
662
663 mutex_unlock(&wm2000->lock);
664
665 return ret;
635} 666}
636 667
637static const struct snd_kcontrol_new wm2000_controls[] = { 668static const struct snd_kcontrol_new wm2000_controls[] = {
669 SOC_SINGLE("ANC Volume", WM2000_REG_ANC_GAIN_CTRL, 0, 255, 0),
638 SOC_SINGLE_BOOL_EXT("WM2000 ANC Switch", 0, 670 SOC_SINGLE_BOOL_EXT("WM2000 ANC Switch", 0,
639 wm2000_anc_mode_get, 671 wm2000_anc_mode_get,
640 wm2000_anc_mode_put), 672 wm2000_anc_mode_put),
@@ -648,6 +680,9 @@ static int wm2000_anc_power_event(struct snd_soc_dapm_widget *w,
648{ 680{
649 struct snd_soc_codec *codec = w->codec; 681 struct snd_soc_codec *codec = w->codec;
650 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev); 682 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev);
683 int ret;
684
685 mutex_lock(&wm2000->lock);
651 686
652 if (SND_SOC_DAPM_EVENT_ON(event)) 687 if (SND_SOC_DAPM_EVENT_ON(event))
653 wm2000->anc_eng_ena = 1; 688 wm2000->anc_eng_ena = 1;
@@ -655,7 +690,11 @@ static int wm2000_anc_power_event(struct snd_soc_dapm_widget *w,
655 if (SND_SOC_DAPM_EVENT_OFF(event)) 690 if (SND_SOC_DAPM_EVENT_OFF(event))
656 wm2000->anc_eng_ena = 0; 691 wm2000->anc_eng_ena = 0;
657 692
658 return wm2000_anc_set_mode(wm2000); 693 ret = wm2000_anc_set_mode(wm2000);
694
695 mutex_unlock(&wm2000->lock);
696
697 return ret;
659} 698}
660 699
661static const struct snd_soc_dapm_widget wm2000_dapm_widgets[] = { 700static const struct snd_soc_dapm_widget wm2000_dapm_widgets[] = {
@@ -702,6 +741,9 @@ static bool wm2000_readable_reg(struct device *dev, unsigned int reg)
702{ 741{
703 switch (reg) { 742 switch (reg) {
704 case WM2000_REG_SYS_START: 743 case WM2000_REG_SYS_START:
744 case WM2000_REG_ANC_GAIN_CTRL:
745 case WM2000_REG_MSE_TH1:
746 case WM2000_REG_MSE_TH2:
705 case WM2000_REG_SPEECH_CLARITY: 747 case WM2000_REG_SPEECH_CLARITY:
706 case WM2000_REG_SYS_WATCHDOG: 748 case WM2000_REG_SYS_WATCHDOG:
707 case WM2000_REG_ANA_VMID_PD_TIME: 749 case WM2000_REG_ANA_VMID_PD_TIME:
@@ -737,6 +779,8 @@ static int wm2000_probe(struct snd_soc_codec *codec)
737{ 779{
738 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev); 780 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev);
739 781
782 snd_soc_codec_set_cache_io(codec, 16, 8, SND_SOC_REGMAP);
783
740 /* This will trigger a transition to standby mode by default */ 784 /* This will trigger a transition to standby mode by default */
741 wm2000_anc_set_mode(wm2000); 785 wm2000_anc_set_mode(wm2000);
742 786
@@ -782,6 +826,8 @@ static int wm2000_i2c_probe(struct i2c_client *i2c,
782 return -ENOMEM; 826 return -ENOMEM;
783 } 827 }
784 828
829 mutex_init(&wm2000->lock);
830
785 dev_set_drvdata(&i2c->dev, wm2000); 831 dev_set_drvdata(&i2c->dev, wm2000);
786 832
787 wm2000->regmap = devm_regmap_init_i2c(i2c, &wm2000_regmap); 833 wm2000->regmap = devm_regmap_init_i2c(i2c, &wm2000_regmap);
@@ -823,10 +869,16 @@ static int wm2000_i2c_probe(struct i2c_client *i2c,
823 reg = wm2000_read(i2c, WM2000_REG_REVISON); 869 reg = wm2000_read(i2c, WM2000_REG_REVISON);
824 dev_info(&i2c->dev, "revision %c\n", reg + 'A'); 870 dev_info(&i2c->dev, "revision %c\n", reg + 'A');
825 871
872 wm2000->mclk = devm_clk_get(&i2c->dev, "MCLK");
873 if (IS_ERR(wm2000->mclk)) {
874 ret = PTR_ERR(wm2000->mclk);
875 dev_err(&i2c->dev, "Failed to get MCLK: %d\n", ret);
876 goto err_supplies;
877 }
878
826 filename = "wm2000_anc.bin"; 879 filename = "wm2000_anc.bin";
827 pdata = dev_get_platdata(&i2c->dev); 880 pdata = dev_get_platdata(&i2c->dev);
828 if (pdata) { 881 if (pdata) {
829 wm2000->mclk_div = pdata->mclkdiv2;
830 wm2000->speech_clarity = !pdata->speech_enh_disable; 882 wm2000->speech_clarity = !pdata->speech_enh_disable;
831 883
832 if (pdata->download_file) 884 if (pdata->download_file)
diff --git a/sound/soc/codecs/wm2000.h b/sound/soc/codecs/wm2000.h
index abcd82a93995..fb812cd9e77d 100644
--- a/sound/soc/codecs/wm2000.h
+++ b/sound/soc/codecs/wm2000.h
@@ -10,6 +10,9 @@
10#define _WM2000_H 10#define _WM2000_H
11 11
12#define WM2000_REG_SYS_START 0x8000 12#define WM2000_REG_SYS_START 0x8000
13#define WM2000_REG_ANC_GAIN_CTRL 0x8fa2
14#define WM2000_REG_MSE_TH2 0x8fdf
15#define WM2000_REG_MSE_TH1 0x8fe0
13#define WM2000_REG_SPEECH_CLARITY 0x8fef 16#define WM2000_REG_SPEECH_CLARITY 0x8fef
14#define WM2000_REG_SYS_WATCHDOG 0x8ff6 17#define WM2000_REG_SYS_WATCHDOG 0x8ff6
15#define WM2000_REG_ANA_VMID_PD_TIME 0x8ff7 18#define WM2000_REG_ANA_VMID_PD_TIME 0x8ff7
diff --git a/sound/soc/codecs/wm2200.c b/sound/soc/codecs/wm2200.c
index d8c65f574658..ddc98f02ecbd 100644
--- a/sound/soc/codecs/wm2200.c
+++ b/sound/soc/codecs/wm2200.c
@@ -1109,6 +1109,16 @@ static int wm2200_mixer_values[] = {
1109 static WM2200_MUX_CTL_DECL(name##_aux5); \ 1109 static WM2200_MUX_CTL_DECL(name##_aux5); \
1110 static WM2200_MUX_CTL_DECL(name##_aux6); 1110 static WM2200_MUX_CTL_DECL(name##_aux6);
1111 1111
1112static const char *wm2200_rxanc_input_sel_texts[] = {
1113 "None", "IN1", "IN2", "IN3",
1114};
1115
1116static const struct soc_enum wm2200_rxanc_input_sel =
1117 SOC_ENUM_SINGLE(WM2200_RXANC_SRC,
1118 WM2200_IN_RXANC_SEL_SHIFT,
1119 ARRAY_SIZE(wm2200_rxanc_input_sel_texts),
1120 wm2200_rxanc_input_sel_texts);
1121
1112static const struct snd_kcontrol_new wm2200_snd_controls[] = { 1122static const struct snd_kcontrol_new wm2200_snd_controls[] = {
1113SOC_SINGLE("IN1 High Performance Switch", WM2200_IN1L_CONTROL, 1123SOC_SINGLE("IN1 High Performance Switch", WM2200_IN1L_CONTROL,
1114 WM2200_IN1_OSR_SHIFT, 1, 0), 1124 WM2200_IN1_OSR_SHIFT, 1, 0),
@@ -1126,9 +1136,9 @@ SOC_DOUBLE_R_TLV("IN3 Volume", WM2200_IN3L_CONTROL, WM2200_IN3R_CONTROL,
1126 1136
1127SOC_DOUBLE_R("IN1 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_1L, 1137SOC_DOUBLE_R("IN1 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_1L,
1128 WM2200_ADC_DIGITAL_VOLUME_1R, WM2200_IN1L_MUTE_SHIFT, 1, 1), 1138 WM2200_ADC_DIGITAL_VOLUME_1R, WM2200_IN1L_MUTE_SHIFT, 1, 1),
1129SOC_DOUBLE_R("IN2 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_1L, 1139SOC_DOUBLE_R("IN2 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_2L,
1130 WM2200_ADC_DIGITAL_VOLUME_2R, WM2200_IN2L_MUTE_SHIFT, 1, 1), 1140 WM2200_ADC_DIGITAL_VOLUME_2R, WM2200_IN2L_MUTE_SHIFT, 1, 1),
1131SOC_DOUBLE_R("IN3 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_1L, 1141SOC_DOUBLE_R("IN3 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_3L,
1132 WM2200_ADC_DIGITAL_VOLUME_3R, WM2200_IN3L_MUTE_SHIFT, 1, 1), 1142 WM2200_ADC_DIGITAL_VOLUME_3R, WM2200_IN3L_MUTE_SHIFT, 1, 1),
1133 1143
1134SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_1L, 1144SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_1L,
@@ -1141,6 +1151,12 @@ SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_3L,
1141 WM2200_ADC_DIGITAL_VOLUME_3R, WM2200_IN3L_DIG_VOL_SHIFT, 1151 WM2200_ADC_DIGITAL_VOLUME_3R, WM2200_IN3L_DIG_VOL_SHIFT,
1142 0xbf, 0, digital_tlv), 1152 0xbf, 0, digital_tlv),
1143 1153
1154SND_SOC_BYTES_MASK("EQL Coefficients", WM2200_EQL_1, 20, WM2200_EQL_ENA),
1155SND_SOC_BYTES_MASK("EQR Coefficients", WM2200_EQR_1, 20, WM2200_EQR_ENA),
1156
1157SND_SOC_BYTES("LHPF1 Coefficeints", WM2200_HPLPF1_2, 1),
1158SND_SOC_BYTES("LHPF2 Coefficeints", WM2200_HPLPF2_2, 1),
1159
1144SOC_SINGLE("OUT1 High Performance Switch", WM2200_DAC_DIGITAL_VOLUME_1L, 1160SOC_SINGLE("OUT1 High Performance Switch", WM2200_DAC_DIGITAL_VOLUME_1L,
1145 WM2200_OUT1_OSR_SHIFT, 1, 0), 1161 WM2200_OUT1_OSR_SHIFT, 1, 0),
1146SOC_SINGLE("OUT2 High Performance Switch", WM2200_DAC_DIGITAL_VOLUME_2L, 1162SOC_SINGLE("OUT2 High Performance Switch", WM2200_DAC_DIGITAL_VOLUME_2L,
@@ -1162,6 +1178,7 @@ SOC_DOUBLE_R_TLV("OUT2 Digital Volume", WM2200_DAC_DIGITAL_VOLUME_2L,
1162 digital_tlv), 1178 digital_tlv),
1163SOC_DOUBLE("OUT2 Switch", WM2200_PDM_1, WM2200_SPK1L_MUTE_SHIFT, 1179SOC_DOUBLE("OUT2 Switch", WM2200_PDM_1, WM2200_SPK1L_MUTE_SHIFT,
1164 WM2200_SPK1R_MUTE_SHIFT, 1, 1), 1180 WM2200_SPK1R_MUTE_SHIFT, 1, 1),
1181SOC_ENUM("RxANC Src", wm2200_rxanc_input_sel),
1165}; 1182};
1166 1183
1167WM2200_MIXER_ENUMS(OUT1L, WM2200_OUT1LMIX_INPUT_1_SOURCE); 1184WM2200_MIXER_ENUMS(OUT1L, WM2200_OUT1LMIX_INPUT_1_SOURCE);
@@ -1548,6 +1565,10 @@ static int wm2200_probe(struct snd_soc_codec *codec)
1548 return ret; 1565 return ret;
1549 } 1566 }
1550 1567
1568 ret = snd_soc_add_codec_controls(codec, wm_adsp_fw_controls, 2);
1569 if (ret != 0)
1570 return ret;
1571
1551 return ret; 1572 return ret;
1552} 1573}
1553 1574
@@ -2182,6 +2203,7 @@ static int wm2200_i2c_probe(struct i2c_client *i2c,
2182 struct wm2200_priv *wm2200; 2203 struct wm2200_priv *wm2200;
2183 unsigned int reg; 2204 unsigned int reg;
2184 int ret, i; 2205 int ret, i;
2206 int val;
2185 2207
2186 wm2200 = devm_kzalloc(&i2c->dev, sizeof(struct wm2200_priv), 2208 wm2200 = devm_kzalloc(&i2c->dev, sizeof(struct wm2200_priv),
2187 GFP_KERNEL); 2209 GFP_KERNEL);
@@ -2205,6 +2227,9 @@ static int wm2200_i2c_probe(struct i2c_client *i2c,
2205 wm2200->dsp[i].num = i + 1; 2227 wm2200->dsp[i].num = i + 1;
2206 wm2200->dsp[i].dev = &i2c->dev; 2228 wm2200->dsp[i].dev = &i2c->dev;
2207 wm2200->dsp[i].regmap = wm2200->regmap; 2229 wm2200->dsp[i].regmap = wm2200->regmap;
2230 wm2200->dsp[i].sysclk_reg = WM2200_CLOCKING_3;
2231 wm2200->dsp[i].sysclk_mask = WM2200_SYSCLK_FREQ_MASK;
2232 wm2200->dsp[i].sysclk_shift = WM2200_SYSCLK_FREQ_SHIFT;
2208 } 2233 }
2209 2234
2210 wm2200->dsp[0].base = WM2200_DSP1_CONTROL_1; 2235 wm2200->dsp[0].base = WM2200_DSP1_CONTROL_1;
@@ -2215,6 +2240,9 @@ static int wm2200_i2c_probe(struct i2c_client *i2c,
2215 wm2200->dsp[1].mem = wm2200_dsp2_regions; 2240 wm2200->dsp[1].mem = wm2200_dsp2_regions;
2216 wm2200->dsp[1].num_mems = ARRAY_SIZE(wm2200_dsp2_regions); 2241 wm2200->dsp[1].num_mems = ARRAY_SIZE(wm2200_dsp2_regions);
2217 2242
2243 for (i = 0; i < ARRAY_SIZE(wm2200->dsp); i++)
2244 wm_adsp1_init(&wm2200->dsp[i]);
2245
2218 if (pdata) 2246 if (pdata)
2219 wm2200->pdata = *pdata; 2247 wm2200->pdata = *pdata;
2220 2248
@@ -2326,6 +2354,36 @@ static int wm2200_i2c_probe(struct i2c_client *i2c,
2326 regmap_write(wm2200->regmap, WM2200_AUDIO_IF_1_16 + i, i); 2354 regmap_write(wm2200->regmap, WM2200_AUDIO_IF_1_16 + i, i);
2327 } 2355 }
2328 2356
2357 for (i = 0; i < WM2200_MAX_MICBIAS; i++) {
2358 if (!wm2200->pdata.micbias[i].mb_lvl &&
2359 !wm2200->pdata.micbias[i].bypass)
2360 continue;
2361
2362 /* Apply default for bypass mode */
2363 if (!wm2200->pdata.micbias[i].mb_lvl)
2364 wm2200->pdata.micbias[i].mb_lvl
2365 = WM2200_MBIAS_LVL_1V5;
2366
2367 val = (wm2200->pdata.micbias[i].mb_lvl -1)
2368 << WM2200_MICB1_LVL_SHIFT;
2369
2370 if (wm2200->pdata.micbias[i].discharge)
2371 val |= WM2200_MICB1_DISCH;
2372
2373 if (wm2200->pdata.micbias[i].fast_start)
2374 val |= WM2200_MICB1_RATE;
2375
2376 if (wm2200->pdata.micbias[i].bypass)
2377 val |= WM2200_MICB1_MODE;
2378
2379 regmap_update_bits(wm2200->regmap,
2380 WM2200_MIC_BIAS_CTRL_1 + i,
2381 WM2200_MICB1_LVL_MASK |
2382 WM2200_MICB1_DISCH |
2383 WM2200_MICB1_MODE |
2384 WM2200_MICB1_RATE, val);
2385 }
2386
2329 for (i = 0; i < ARRAY_SIZE(wm2200->pdata.in_mode); i++) { 2387 for (i = 0; i < ARRAY_SIZE(wm2200->pdata.in_mode); i++) {
2330 regmap_update_bits(wm2200->regmap, wm2200_mic_ctrl_reg[i], 2388 regmap_update_bits(wm2200->regmap, wm2200_mic_ctrl_reg[i],
2331 WM2200_IN1_MODE_MASK | 2389 WM2200_IN1_MODE_MASK |
diff --git a/sound/soc/codecs/wm5100.c b/sound/soc/codecs/wm5100.c
index 54397a508073..ac1745d030d6 100644
--- a/sound/soc/codecs/wm5100.c
+++ b/sound/soc/codecs/wm5100.c
@@ -563,6 +563,19 @@ SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
563SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L, 563SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
564 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1), 564 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
565 565
566SND_SOC_BYTES_MASK("EQ1 Coefficients", WM5100_EQ1_1, 20, WM5100_EQ1_ENA),
567SND_SOC_BYTES_MASK("EQ2 Coefficients", WM5100_EQ2_1, 20, WM5100_EQ2_ENA),
568SND_SOC_BYTES_MASK("EQ3 Coefficients", WM5100_EQ3_1, 20, WM5100_EQ3_ENA),
569SND_SOC_BYTES_MASK("EQ4 Coefficients", WM5100_EQ4_1, 20, WM5100_EQ4_ENA),
570
571SND_SOC_BYTES_MASK("DRC Coefficients", WM5100_DRC1_CTRL1, 5,
572 WM5100_DRCL_ENA | WM5100_DRCR_ENA),
573
574SND_SOC_BYTES("LHPF1 Coefficeints", WM5100_HPLPF1_2, 1),
575SND_SOC_BYTES("LHPF2 Coefficeints", WM5100_HPLPF2_2, 1),
576SND_SOC_BYTES("LHPF3 Coefficeints", WM5100_HPLPF3_2, 1),
577SND_SOC_BYTES("LHPF4 Coefficeints", WM5100_HPLPF4_2, 1),
578
566SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L, 579SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
567 WM5100_OUT1_OSR_SHIFT, 1, 0), 580 WM5100_OUT1_OSR_SHIFT, 1, 0),
568SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L, 581SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
diff --git a/sound/soc/codecs/wm5102.c b/sound/soc/codecs/wm5102.c
index 1440b3f9b7bb..5e85b645f2eb 100644
--- a/sound/soc/codecs/wm5102.c
+++ b/sound/soc/codecs/wm5102.c
@@ -45,6 +45,7 @@ static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0);
45static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 45static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
46static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0); 46static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
47static DECLARE_TLV_DB_SCALE(noise_tlv, 0, 600, 0); 47static DECLARE_TLV_DB_SCALE(noise_tlv, 0, 600, 0);
48static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
48 49
49static const struct wm_adsp_region wm5102_dsp1_regions[] = { 50static const struct wm_adsp_region wm5102_dsp1_regions[] = {
50 { .type = WMFW_ADSP2_PM, .base = 0x100000 }, 51 { .type = WMFW_ADSP2_PM, .base = 0x100000 },
@@ -603,6 +604,17 @@ static int wm5102_sysclk_ev(struct snd_soc_dapm_widget *w,
603 return 0; 604 return 0;
604} 605}
605 606
607#define WM5102_NG_SRC(name, base) \
608 SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \
609 SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \
610 SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \
611 SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \
612 SOC_SINGLE(name " NG EPOUT Switch", base, 4, 1, 0), \
613 SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \
614 SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0), \
615 SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \
616 SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0)
617
606static const struct snd_kcontrol_new wm5102_snd_controls[] = { 618static const struct snd_kcontrol_new wm5102_snd_controls[] = {
607SOC_SINGLE("IN1 High Performance Switch", ARIZONA_IN1L_CONTROL, 619SOC_SINGLE("IN1 High Performance Switch", ARIZONA_IN1L_CONTROL,
608 ARIZONA_IN1_OSR_SHIFT, 1, 0), 620 ARIZONA_IN1_OSR_SHIFT, 1, 0),
@@ -611,32 +623,44 @@ SOC_SINGLE("IN2 High Performance Switch", ARIZONA_IN2L_CONTROL,
611SOC_SINGLE("IN3 High Performance Switch", ARIZONA_IN3L_CONTROL, 623SOC_SINGLE("IN3 High Performance Switch", ARIZONA_IN3L_CONTROL,
612 ARIZONA_IN3_OSR_SHIFT, 1, 0), 624 ARIZONA_IN3_OSR_SHIFT, 1, 0),
613 625
614SOC_DOUBLE_R_RANGE_TLV("IN1 Volume", ARIZONA_IN1L_CONTROL, 626SOC_SINGLE_RANGE_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL,
615 ARIZONA_IN1R_CONTROL, 627 ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
616 ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), 628SOC_SINGLE_RANGE_TLV("IN1R Volume", ARIZONA_IN1R_CONTROL,
617SOC_DOUBLE_R_RANGE_TLV("IN2 Volume", ARIZONA_IN2L_CONTROL, 629 ARIZONA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
618 ARIZONA_IN2R_CONTROL, 630SOC_SINGLE_RANGE_TLV("IN2L Volume", ARIZONA_IN2L_CONTROL,
619 ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), 631 ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
620SOC_DOUBLE_R_RANGE_TLV("IN3 Volume", ARIZONA_IN3L_CONTROL, 632SOC_SINGLE_RANGE_TLV("IN2R Volume", ARIZONA_IN2R_CONTROL,
621 ARIZONA_IN3R_CONTROL, 633 ARIZONA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
622 ARIZONA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), 634SOC_SINGLE_RANGE_TLV("IN3L Volume", ARIZONA_IN3L_CONTROL,
623 635 ARIZONA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
624SOC_DOUBLE_R("IN1 Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_1L, 636SOC_SINGLE_RANGE_TLV("IN3R Volume", ARIZONA_IN3R_CONTROL,
625 ARIZONA_ADC_DIGITAL_VOLUME_1R, ARIZONA_IN1L_MUTE_SHIFT, 1, 1), 637 ARIZONA_IN3R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
626SOC_DOUBLE_R("IN2 Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_2L, 638
627 ARIZONA_ADC_DIGITAL_VOLUME_2R, ARIZONA_IN2L_MUTE_SHIFT, 1, 1), 639SOC_SINGLE("IN1L Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_1L,
628SOC_DOUBLE_R("IN3 Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_3L, 640 ARIZONA_IN1L_MUTE_SHIFT, 1, 1),
629 ARIZONA_ADC_DIGITAL_VOLUME_3R, ARIZONA_IN3L_MUTE_SHIFT, 1, 1), 641SOC_SINGLE("IN1R Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_1R,
630 642 ARIZONA_IN1R_MUTE_SHIFT, 1, 1),
631SOC_DOUBLE_R_TLV("IN1 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L, 643SOC_SINGLE("IN2L Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_2L,
632 ARIZONA_ADC_DIGITAL_VOLUME_1R, ARIZONA_IN1L_DIG_VOL_SHIFT, 644 ARIZONA_IN2L_MUTE_SHIFT, 1, 1),
633 0xbf, 0, digital_tlv), 645SOC_SINGLE("IN2R Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_2R,
634SOC_DOUBLE_R_TLV("IN2 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L, 646 ARIZONA_IN2R_MUTE_SHIFT, 1, 1),
635 ARIZONA_ADC_DIGITAL_VOLUME_2R, ARIZONA_IN2L_DIG_VOL_SHIFT, 647SOC_SINGLE("IN3L Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_3L,
636 0xbf, 0, digital_tlv), 648 ARIZONA_IN3L_MUTE_SHIFT, 1, 1),
637SOC_DOUBLE_R_TLV("IN3 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3L, 649SOC_SINGLE("IN3R Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_3R,
638 ARIZONA_ADC_DIGITAL_VOLUME_3R, ARIZONA_IN3L_DIG_VOL_SHIFT, 650 ARIZONA_IN3R_MUTE_SHIFT, 1, 1),
639 0xbf, 0, digital_tlv), 651
652SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L,
653 ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
654SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R,
655 ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
656SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L,
657 ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
658SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R,
659 ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
660SOC_SINGLE_TLV("IN3L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3L,
661 ARIZONA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
662SOC_SINGLE_TLV("IN3R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3R,
663 ARIZONA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
640 664
641SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp), 665SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp),
642SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp), 666SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp),
@@ -774,6 +798,22 @@ SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp),
774SOC_DOUBLE("SPKDAT1 Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT, 798SOC_DOUBLE("SPKDAT1 Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT,
775 ARIZONA_SPK1R_MUTE_SHIFT, 1, 1), 799 ARIZONA_SPK1R_MUTE_SHIFT, 1, 1),
776 800
801SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL,
802 ARIZONA_NGATE_ENA_SHIFT, 1, 0),
803SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL,
804 ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv),
805SOC_ENUM("Noise Gate Hold", arizona_ng_hold),
806
807WM5102_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L),
808WM5102_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R),
809WM5102_NG_SRC("HPOUT2L", ARIZONA_NOISE_GATE_SELECT_2L),
810WM5102_NG_SRC("HPOUT2R", ARIZONA_NOISE_GATE_SELECT_2R),
811WM5102_NG_SRC("EPOUT", ARIZONA_NOISE_GATE_SELECT_3L),
812WM5102_NG_SRC("SPKOUTL", ARIZONA_NOISE_GATE_SELECT_4L),
813WM5102_NG_SRC("SPKOUTR", ARIZONA_NOISE_GATE_SELECT_4R),
814WM5102_NG_SRC("SPKDAT1L", ARIZONA_NOISE_GATE_SELECT_5L),
815WM5102_NG_SRC("SPKDAT1R", ARIZONA_NOISE_GATE_SELECT_5R),
816
777ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE), 817ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE),
778ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE), 818ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE),
779ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE), 819ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE),
@@ -880,6 +920,18 @@ ARIZONA_MUX_ENUMS(ASRC1R, ARIZONA_ASRC1RMIX_INPUT_1_SOURCE);
880ARIZONA_MUX_ENUMS(ASRC2L, ARIZONA_ASRC2LMIX_INPUT_1_SOURCE); 920ARIZONA_MUX_ENUMS(ASRC2L, ARIZONA_ASRC2LMIX_INPUT_1_SOURCE);
881ARIZONA_MUX_ENUMS(ASRC2R, ARIZONA_ASRC2RMIX_INPUT_1_SOURCE); 921ARIZONA_MUX_ENUMS(ASRC2R, ARIZONA_ASRC2RMIX_INPUT_1_SOURCE);
882 922
923ARIZONA_MUX_ENUMS(ISRC1INT1, ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE);
924ARIZONA_MUX_ENUMS(ISRC1INT2, ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE);
925
926ARIZONA_MUX_ENUMS(ISRC1DEC1, ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE);
927ARIZONA_MUX_ENUMS(ISRC1DEC2, ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE);
928
929ARIZONA_MUX_ENUMS(ISRC2INT1, ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE);
930ARIZONA_MUX_ENUMS(ISRC2INT2, ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE);
931
932ARIZONA_MUX_ENUMS(ISRC2DEC1, ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE);
933ARIZONA_MUX_ENUMS(ISRC2DEC2, ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE);
934
883ARIZONA_MIXER_ENUMS(DSP1L, ARIZONA_DSP1LMIX_INPUT_1_SOURCE); 935ARIZONA_MIXER_ENUMS(DSP1L, ARIZONA_DSP1LMIX_INPUT_1_SOURCE);
884ARIZONA_MIXER_ENUMS(DSP1R, ARIZONA_DSP1RMIX_INPUT_1_SOURCE); 936ARIZONA_MIXER_ENUMS(DSP1R, ARIZONA_DSP1RMIX_INPUT_1_SOURCE);
885 937
@@ -1002,6 +1054,26 @@ SND_SOC_DAPM_PGA("ASRC2L", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2L_ENA_SHIFT, 0,
1002SND_SOC_DAPM_PGA("ASRC2R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2R_ENA_SHIFT, 0, 1054SND_SOC_DAPM_PGA("ASRC2R", ARIZONA_ASRC_ENABLE, ARIZONA_ASRC2R_ENA_SHIFT, 0,
1003 NULL, 0), 1055 NULL, 0),
1004 1056
1057SND_SOC_DAPM_PGA("ISRC1INT1", ARIZONA_ISRC_1_CTRL_3,
1058 ARIZONA_ISRC1_INT0_ENA_SHIFT, 0, NULL, 0),
1059SND_SOC_DAPM_PGA("ISRC1INT2", ARIZONA_ISRC_1_CTRL_3,
1060 ARIZONA_ISRC1_INT1_ENA_SHIFT, 0, NULL, 0),
1061
1062SND_SOC_DAPM_PGA("ISRC1DEC1", ARIZONA_ISRC_1_CTRL_3,
1063 ARIZONA_ISRC1_DEC0_ENA_SHIFT, 0, NULL, 0),
1064SND_SOC_DAPM_PGA("ISRC1DEC2", ARIZONA_ISRC_1_CTRL_3,
1065 ARIZONA_ISRC1_DEC1_ENA_SHIFT, 0, NULL, 0),
1066
1067SND_SOC_DAPM_PGA("ISRC2INT1", ARIZONA_ISRC_2_CTRL_3,
1068 ARIZONA_ISRC2_INT0_ENA_SHIFT, 0, NULL, 0),
1069SND_SOC_DAPM_PGA("ISRC2INT2", ARIZONA_ISRC_2_CTRL_3,
1070 ARIZONA_ISRC2_INT1_ENA_SHIFT, 0, NULL, 0),
1071
1072SND_SOC_DAPM_PGA("ISRC2DEC1", ARIZONA_ISRC_2_CTRL_3,
1073 ARIZONA_ISRC2_DEC0_ENA_SHIFT, 0, NULL, 0),
1074SND_SOC_DAPM_PGA("ISRC2DEC2", ARIZONA_ISRC_2_CTRL_3,
1075 ARIZONA_ISRC2_DEC1_ENA_SHIFT, 0, NULL, 0),
1076
1005SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0, 1077SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 0,
1006 ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0), 1078 ARIZONA_AIF1_TX_ENABLES, ARIZONA_AIF1TX1_ENA_SHIFT, 0),
1007SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 0, 1079SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 0,
@@ -1138,6 +1210,18 @@ ARIZONA_MUX_WIDGETS(ASRC1R, "ASRC1R"),
1138ARIZONA_MUX_WIDGETS(ASRC2L, "ASRC2L"), 1210ARIZONA_MUX_WIDGETS(ASRC2L, "ASRC2L"),
1139ARIZONA_MUX_WIDGETS(ASRC2R, "ASRC2R"), 1211ARIZONA_MUX_WIDGETS(ASRC2R, "ASRC2R"),
1140 1212
1213ARIZONA_MUX_WIDGETS(ISRC1DEC1, "ISRC1DEC1"),
1214ARIZONA_MUX_WIDGETS(ISRC1DEC2, "ISRC1DEC2"),
1215
1216ARIZONA_MUX_WIDGETS(ISRC1INT1, "ISRC1INT1"),
1217ARIZONA_MUX_WIDGETS(ISRC1INT2, "ISRC1INT2"),
1218
1219ARIZONA_MUX_WIDGETS(ISRC2DEC1, "ISRC2DEC1"),
1220ARIZONA_MUX_WIDGETS(ISRC2DEC2, "ISRC2DEC2"),
1221
1222ARIZONA_MUX_WIDGETS(ISRC2INT1, "ISRC2INT1"),
1223ARIZONA_MUX_WIDGETS(ISRC2INT2, "ISRC2INT2"),
1224
1141WM_ADSP2("DSP1", 0), 1225WM_ADSP2("DSP1", 0),
1142 1226
1143SND_SOC_DAPM_OUTPUT("HPOUT1L"), 1227SND_SOC_DAPM_OUTPUT("HPOUT1L"),
@@ -1193,6 +1277,14 @@ SND_SOC_DAPM_OUTPUT("SPKDAT1R"),
1193 { name, "ASRC1R", "ASRC1R" }, \ 1277 { name, "ASRC1R", "ASRC1R" }, \
1194 { name, "ASRC2L", "ASRC2L" }, \ 1278 { name, "ASRC2L", "ASRC2L" }, \
1195 { name, "ASRC2R", "ASRC2R" }, \ 1279 { name, "ASRC2R", "ASRC2R" }, \
1280 { name, "ISRC1DEC1", "ISRC1DEC1" }, \
1281 { name, "ISRC1DEC2", "ISRC1DEC2" }, \
1282 { name, "ISRC1INT1", "ISRC1INT1" }, \
1283 { name, "ISRC1INT2", "ISRC1INT2" }, \
1284 { name, "ISRC2DEC1", "ISRC2DEC1" }, \
1285 { name, "ISRC2DEC2", "ISRC2DEC2" }, \
1286 { name, "ISRC2INT1", "ISRC2INT1" }, \
1287 { name, "ISRC2INT2", "ISRC2INT2" }, \
1196 { name, "DSP1.1", "DSP1" }, \ 1288 { name, "DSP1.1", "DSP1" }, \
1197 { name, "DSP1.2", "DSP1" }, \ 1289 { name, "DSP1.2", "DSP1" }, \
1198 { name, "DSP1.3", "DSP1" }, \ 1290 { name, "DSP1.3", "DSP1" }, \
@@ -1289,6 +1381,18 @@ static const struct snd_soc_dapm_route wm5102_dapm_routes[] = {
1289 { "ASRC2L", NULL, "ASRC2L Input" }, 1381 { "ASRC2L", NULL, "ASRC2L Input" },
1290 { "ASRC2R", NULL, "ASRC2R Input" }, 1382 { "ASRC2R", NULL, "ASRC2R Input" },
1291 1383
1384 { "ISRC1DEC1", NULL, "ISRC1DEC1 Input" },
1385 { "ISRC1DEC2", NULL, "ISRC1DEC2 Input" },
1386
1387 { "ISRC1INT1", NULL, "ISRC1INT1 Input" },
1388 { "ISRC1INT2", NULL, "ISRC1INT2 Input" },
1389
1390 { "ISRC2DEC1", NULL, "ISRC2DEC1 Input" },
1391 { "ISRC2DEC2", NULL, "ISRC2DEC2 Input" },
1392
1393 { "ISRC2INT1", NULL, "ISRC2INT1 Input" },
1394 { "ISRC2INT2", NULL, "ISRC2INT2 Input" },
1395
1292 ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"), 1396 ARIZONA_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1293 ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"), 1397 ARIZONA_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1294 ARIZONA_MIXER_ROUTES("OUT2L", "HPOUT2L"), 1398 ARIZONA_MIXER_ROUTES("OUT2L", "HPOUT2L"),
@@ -1336,6 +1440,18 @@ static const struct snd_soc_dapm_route wm5102_dapm_routes[] = {
1336 ARIZONA_MUX_ROUTES("ASRC2L"), 1440 ARIZONA_MUX_ROUTES("ASRC2L"),
1337 ARIZONA_MUX_ROUTES("ASRC2R"), 1441 ARIZONA_MUX_ROUTES("ASRC2R"),
1338 1442
1443 ARIZONA_MUX_ROUTES("ISRC1INT1"),
1444 ARIZONA_MUX_ROUTES("ISRC1INT2"),
1445
1446 ARIZONA_MUX_ROUTES("ISRC1DEC1"),
1447 ARIZONA_MUX_ROUTES("ISRC1DEC2"),
1448
1449 ARIZONA_MUX_ROUTES("ISRC2INT1"),
1450 ARIZONA_MUX_ROUTES("ISRC2INT2"),
1451
1452 ARIZONA_MUX_ROUTES("ISRC2DEC1"),
1453 ARIZONA_MUX_ROUTES("ISRC2DEC2"),
1454
1339 ARIZONA_DSP_ROUTES("DSP1"), 1455 ARIZONA_DSP_ROUTES("DSP1"),
1340 1456
1341 { "AEC Loopback", "HPOUT1L", "OUT1L" }, 1457 { "AEC Loopback", "HPOUT1L", "OUT1L" },
@@ -1463,6 +1579,10 @@ static int wm5102_codec_probe(struct snd_soc_codec *codec)
1463 if (ret != 0) 1579 if (ret != 0)
1464 return ret; 1580 return ret;
1465 1581
1582 ret = snd_soc_add_codec_controls(codec, wm_adsp_fw_controls, 1);
1583 if (ret != 0)
1584 return ret;
1585
1466 snd_soc_dapm_disable_pin(&codec->dapm, "HAPTICS"); 1586 snd_soc_dapm_disable_pin(&codec->dapm, "HAPTICS");
1467 1587
1468 priv->core.arizona->dapm = &codec->dapm; 1588 priv->core.arizona->dapm = &codec->dapm;
diff --git a/sound/soc/codecs/wm5110.c b/sound/soc/codecs/wm5110.c
index 7a090968c4f7..23199372d518 100644
--- a/sound/soc/codecs/wm5110.c
+++ b/sound/soc/codecs/wm5110.c
@@ -41,6 +41,21 @@ static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0);
41static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 41static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
42static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0); 42static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
43static DECLARE_TLV_DB_SCALE(noise_tlv, 0, 600, 0); 43static DECLARE_TLV_DB_SCALE(noise_tlv, 0, 600, 0);
44static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
45
46#define WM5110_NG_SRC(name, base) \
47 SOC_SINGLE(name " NG HPOUT1L Switch", base, 0, 1, 0), \
48 SOC_SINGLE(name " NG HPOUT1R Switch", base, 1, 1, 0), \
49 SOC_SINGLE(name " NG HPOUT2L Switch", base, 2, 1, 0), \
50 SOC_SINGLE(name " NG HPOUT2R Switch", base, 3, 1, 0), \
51 SOC_SINGLE(name " NG HPOUT3L Switch", base, 4, 1, 0), \
52 SOC_SINGLE(name " NG HPOUT3R Switch", base, 5, 1, 0), \
53 SOC_SINGLE(name " NG SPKOUTL Switch", base, 6, 1, 0), \
54 SOC_SINGLE(name " NG SPKOUTR Switch", base, 7, 1, 0), \
55 SOC_SINGLE(name " NG SPKDAT1L Switch", base, 8, 1, 0), \
56 SOC_SINGLE(name " NG SPKDAT1R Switch", base, 9, 1, 0), \
57 SOC_SINGLE(name " NG SPKDAT2L Switch", base, 10, 1, 0), \
58 SOC_SINGLE(name " NG SPKDAT2R Switch", base, 11, 1, 0)
44 59
45static const struct snd_kcontrol_new wm5110_snd_controls[] = { 60static const struct snd_kcontrol_new wm5110_snd_controls[] = {
46SOC_SINGLE("IN1 High Performance Switch", ARIZONA_IN1L_CONTROL, 61SOC_SINGLE("IN1 High Performance Switch", ARIZONA_IN1L_CONTROL,
@@ -52,37 +67,52 @@ SOC_SINGLE("IN3 High Performance Switch", ARIZONA_IN3L_CONTROL,
52SOC_SINGLE("IN4 High Performance Switch", ARIZONA_IN4L_CONTROL, 67SOC_SINGLE("IN4 High Performance Switch", ARIZONA_IN4L_CONTROL,
53 ARIZONA_IN4_OSR_SHIFT, 1, 0), 68 ARIZONA_IN4_OSR_SHIFT, 1, 0),
54 69
55SOC_DOUBLE_R_RANGE_TLV("IN1 Volume", ARIZONA_IN1L_CONTROL, 70SOC_SINGLE_RANGE_TLV("IN1L Volume", ARIZONA_IN1L_CONTROL,
56 ARIZONA_IN1R_CONTROL, 71 ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
57 ARIZONA_IN1L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), 72SOC_SINGLE_RANGE_TLV("IN1R Volume", ARIZONA_IN1R_CONTROL,
58SOC_DOUBLE_R_RANGE_TLV("IN2 Volume", ARIZONA_IN2L_CONTROL, 73 ARIZONA_IN1R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
59 ARIZONA_IN2R_CONTROL, 74SOC_SINGLE_RANGE_TLV("IN2L Volume", ARIZONA_IN2L_CONTROL,
60 ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), 75 ARIZONA_IN2L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
61SOC_DOUBLE_R_RANGE_TLV("IN3 Volume", ARIZONA_IN3L_CONTROL, 76SOC_SINGLE_RANGE_TLV("IN2R Volume", ARIZONA_IN2R_CONTROL,
62 ARIZONA_IN3R_CONTROL, 77 ARIZONA_IN2R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
63 ARIZONA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv), 78SOC_SINGLE_RANGE_TLV("IN3L Volume", ARIZONA_IN3L_CONTROL,
64 79 ARIZONA_IN3L_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
65SOC_DOUBLE_R("IN1 Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_1L, 80SOC_SINGLE_RANGE_TLV("IN3R Volume", ARIZONA_IN3R_CONTROL,
66 ARIZONA_ADC_DIGITAL_VOLUME_1R, ARIZONA_IN1L_MUTE_SHIFT, 1, 1), 81 ARIZONA_IN3R_PGA_VOL_SHIFT, 0x40, 0x5f, 0, ana_tlv),
67SOC_DOUBLE_R("IN2 Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_2L, 82
68 ARIZONA_ADC_DIGITAL_VOLUME_2R, ARIZONA_IN2L_MUTE_SHIFT, 1, 1), 83SOC_SINGLE("IN1L Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_1L,
69SOC_DOUBLE_R("IN3 Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_3L, 84 ARIZONA_IN1L_MUTE_SHIFT, 1, 1),
70 ARIZONA_ADC_DIGITAL_VOLUME_3R, ARIZONA_IN3L_MUTE_SHIFT, 1, 1), 85SOC_SINGLE("IN1R Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_1R,
71SOC_DOUBLE_R("IN4 Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_4L, 86 ARIZONA_IN1R_MUTE_SHIFT, 1, 1),
72 ARIZONA_ADC_DIGITAL_VOLUME_4R, ARIZONA_IN4L_MUTE_SHIFT, 1, 1), 87SOC_SINGLE("IN2L Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_2L,
73 88 ARIZONA_IN2L_MUTE_SHIFT, 1, 1),
74SOC_DOUBLE_R_TLV("IN1 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L, 89SOC_SINGLE("IN2R Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_2R,
75 ARIZONA_ADC_DIGITAL_VOLUME_1R, ARIZONA_IN1L_DIG_VOL_SHIFT, 90 ARIZONA_IN2R_MUTE_SHIFT, 1, 1),
76 0xbf, 0, digital_tlv), 91SOC_SINGLE("IN3L Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_3L,
77SOC_DOUBLE_R_TLV("IN2 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L, 92 ARIZONA_IN3L_MUTE_SHIFT, 1, 1),
78 ARIZONA_ADC_DIGITAL_VOLUME_2R, ARIZONA_IN2L_DIG_VOL_SHIFT, 93SOC_SINGLE("IN3R Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_3R,
79 0xbf, 0, digital_tlv), 94 ARIZONA_IN3R_MUTE_SHIFT, 1, 1),
80SOC_DOUBLE_R_TLV("IN3 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3L, 95SOC_SINGLE("IN4L Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_4L,
81 ARIZONA_ADC_DIGITAL_VOLUME_3R, ARIZONA_IN3L_DIG_VOL_SHIFT, 96 ARIZONA_IN4L_MUTE_SHIFT, 1, 1),
82 0xbf, 0, digital_tlv), 97SOC_SINGLE("IN4R Digital Switch", ARIZONA_ADC_DIGITAL_VOLUME_4R,
83SOC_DOUBLE_R_TLV("IN4 Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4L, 98 ARIZONA_IN4R_MUTE_SHIFT, 1, 1),
84 ARIZONA_ADC_DIGITAL_VOLUME_4R, ARIZONA_IN4L_DIG_VOL_SHIFT, 99
85 0xbf, 0, digital_tlv), 100SOC_SINGLE_TLV("IN1L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1L,
101 ARIZONA_IN1L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
102SOC_SINGLE_TLV("IN1R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_1R,
103 ARIZONA_IN1R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
104SOC_SINGLE_TLV("IN2L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2L,
105 ARIZONA_IN2L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
106SOC_SINGLE_TLV("IN2R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_2R,
107 ARIZONA_IN2R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
108SOC_SINGLE_TLV("IN3L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3L,
109 ARIZONA_IN3L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
110SOC_SINGLE_TLV("IN3R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_3R,
111 ARIZONA_IN3R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
112SOC_SINGLE_TLV("IN4L Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4L,
113 ARIZONA_IN4L_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
114SOC_SINGLE_TLV("IN4R Digital Volume", ARIZONA_ADC_DIGITAL_VOLUME_4R,
115 ARIZONA_IN4R_DIG_VOL_SHIFT, 0xbf, 0, digital_tlv),
86 116
87SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp), 117SOC_ENUM("Input Ramp Up", arizona_in_vi_ramp),
88SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp), 118SOC_ENUM("Input Ramp Down", arizona_in_vd_ramp),
@@ -263,6 +293,25 @@ SOC_DOUBLE("SPKDAT2 Switch", ARIZONA_PDM_SPK2_CTRL_1, ARIZONA_SPK2L_MUTE_SHIFT,
263SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp), 293SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp),
264SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp), 294SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp),
265 295
296SOC_SINGLE("Noise Gate Switch", ARIZONA_NOISE_GATE_CONTROL,
297 ARIZONA_NGATE_ENA_SHIFT, 1, 0),
298SOC_SINGLE_TLV("Noise Gate Threshold Volume", ARIZONA_NOISE_GATE_CONTROL,
299 ARIZONA_NGATE_THR_SHIFT, 7, 1, ng_tlv),
300SOC_ENUM("Noise Gate Hold", arizona_ng_hold),
301
302WM5110_NG_SRC("HPOUT1L", ARIZONA_NOISE_GATE_SELECT_1L),
303WM5110_NG_SRC("HPOUT1R", ARIZONA_NOISE_GATE_SELECT_1R),
304WM5110_NG_SRC("HPOUT2L", ARIZONA_NOISE_GATE_SELECT_2L),
305WM5110_NG_SRC("HPOUT2R", ARIZONA_NOISE_GATE_SELECT_2R),
306WM5110_NG_SRC("HPOUT3L", ARIZONA_NOISE_GATE_SELECT_3L),
307WM5110_NG_SRC("HPOUT3R", ARIZONA_NOISE_GATE_SELECT_3R),
308WM5110_NG_SRC("SPKOUTL", ARIZONA_NOISE_GATE_SELECT_4L),
309WM5110_NG_SRC("SPKOUTR", ARIZONA_NOISE_GATE_SELECT_4R),
310WM5110_NG_SRC("SPKDAT1L", ARIZONA_NOISE_GATE_SELECT_5L),
311WM5110_NG_SRC("SPKDAT1R", ARIZONA_NOISE_GATE_SELECT_5R),
312WM5110_NG_SRC("SPKDAT2L", ARIZONA_NOISE_GATE_SELECT_6L),
313WM5110_NG_SRC("SPKDAT2R", ARIZONA_NOISE_GATE_SELECT_6R),
314
266ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE), 315ARIZONA_MIXER_CONTROLS("AIF1TX1", ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE),
267ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE), 316ARIZONA_MIXER_CONTROLS("AIF1TX2", ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE),
268ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE), 317ARIZONA_MIXER_CONTROLS("AIF1TX3", ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE),
diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c
index fb92fb47d636..ec0efc1443ba 100644
--- a/sound/soc/codecs/wm8350.c
+++ b/sound/soc/codecs/wm8350.c
@@ -283,18 +283,16 @@ static int pga_event(struct snd_soc_dapm_widget *w,
283 out->ramp = WM8350_RAMP_UP; 283 out->ramp = WM8350_RAMP_UP;
284 out->active = 1; 284 out->active = 1;
285 285
286 if (!delayed_work_pending(&codec->dapm.delayed_work)) 286 schedule_delayed_work(&codec->dapm.delayed_work,
287 schedule_delayed_work(&codec->dapm.delayed_work, 287 msecs_to_jiffies(1));
288 msecs_to_jiffies(1));
289 break; 288 break;
290 289
291 case SND_SOC_DAPM_PRE_PMD: 290 case SND_SOC_DAPM_PRE_PMD:
292 out->ramp = WM8350_RAMP_DOWN; 291 out->ramp = WM8350_RAMP_DOWN;
293 out->active = 0; 292 out->active = 0;
294 293
295 if (!delayed_work_pending(&codec->dapm.delayed_work)) 294 schedule_delayed_work(&codec->dapm.delayed_work,
296 schedule_delayed_work(&codec->dapm.delayed_work, 295 msecs_to_jiffies(1));
297 msecs_to_jiffies(1));
298 break; 296 break;
299 } 297 }
300 298
diff --git a/sound/soc/codecs/wm8804.c b/sound/soc/codecs/wm8804.c
index d321a875b029..1704b1e119cb 100644
--- a/sound/soc/codecs/wm8804.c
+++ b/sound/soc/codecs/wm8804.c
@@ -395,9 +395,6 @@ static int wm8804_set_pll(struct snd_soc_dai *dai, int pll_id,
395 /* power down the PLL before reprogramming it */ 395 /* power down the PLL before reprogramming it */
396 snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1); 396 snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1);
397 397
398 if (!freq_in || !freq_out)
399 return 0;
400
401 /* set PLLN and PRESCALE */ 398 /* set PLLN and PRESCALE */
402 snd_soc_update_bits(codec, WM8804_PLL4, 0xf | 0x10, 399 snd_soc_update_bits(codec, WM8804_PLL4, 0xf | 0x10,
403 pll_div.n | (pll_div.prescale << 4)); 400 pll_div.n | (pll_div.prescale << 4));
diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c
index bd4b0db4cdaa..e9710280e5e1 100644
--- a/sound/soc/codecs/wm8962.c
+++ b/sound/soc/codecs/wm8962.c
@@ -2873,22 +2873,20 @@ static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2873 2873
2874 ret = 0; 2874 ret = 0;
2875 2875
2876 if (fll1 & WM8962_FLL_ENA) { 2876 /* This should be a massive overestimate but go even
2877 /* This should be a massive overestimate but go even 2877 * higher if we'll error out
2878 * higher if we'll error out 2878 */
2879 */ 2879 if (wm8962->irq)
2880 if (wm8962->irq) 2880 timeout = msecs_to_jiffies(5);
2881 timeout = msecs_to_jiffies(5); 2881 else
2882 else 2882 timeout = msecs_to_jiffies(1);
2883 timeout = msecs_to_jiffies(1);
2884 2883
2885 timeout = wait_for_completion_timeout(&wm8962->fll_lock, 2884 timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2886 timeout); 2885 timeout);
2887 2886
2888 if (timeout == 0 && wm8962->irq) { 2887 if (timeout == 0 && wm8962->irq) {
2889 dev_err(codec->dev, "FLL lock timed out"); 2888 dev_err(codec->dev, "FLL lock timed out");
2890 ret = -ETIMEDOUT; 2889 ret = -ETIMEDOUT;
2891 }
2892 } 2890 }
2893 2891
2894 wm8962->fll_fref = Fref; 2892 wm8962->fll_fref = Fref;
@@ -3189,7 +3187,7 @@ static void wm8962_init_beep(struct snd_soc_codec *codec)
3189 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3187 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3190 int ret; 3188 int ret;
3191 3189
3192 wm8962->beep = input_allocate_device(); 3190 wm8962->beep = devm_input_allocate_device(codec->dev);
3193 if (!wm8962->beep) { 3191 if (!wm8962->beep) {
3194 dev_err(codec->dev, "Failed to allocate beep device\n"); 3192 dev_err(codec->dev, "Failed to allocate beep device\n");
3195 return; 3193 return;
@@ -3210,7 +3208,6 @@ static void wm8962_init_beep(struct snd_soc_codec *codec)
3210 3208
3211 ret = input_register_device(wm8962->beep); 3209 ret = input_register_device(wm8962->beep);
3212 if (ret != 0) { 3210 if (ret != 0) {
3213 input_free_device(wm8962->beep);
3214 wm8962->beep = NULL; 3211 wm8962->beep = NULL;
3215 dev_err(codec->dev, "Failed to register beep device\n"); 3212 dev_err(codec->dev, "Failed to register beep device\n");
3216 } 3213 }
@@ -3227,7 +3224,6 @@ static void wm8962_free_beep(struct snd_soc_codec *codec)
3227 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3224 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3228 3225
3229 device_remove_file(codec->dev, &dev_attr_beep); 3226 device_remove_file(codec->dev, &dev_attr_beep);
3230 input_unregister_device(wm8962->beep);
3231 cancel_work_sync(&wm8962->beep_work); 3227 cancel_work_sync(&wm8962->beep_work);
3232 wm8962->beep = NULL; 3228 wm8962->beep = NULL;
3233 3229
@@ -3758,10 +3754,17 @@ static const struct i2c_device_id wm8962_i2c_id[] = {
3758}; 3754};
3759MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id); 3755MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3760 3756
3757static const struct of_device_id wm8962_of_match[] = {
3758 { .compatible = "wlf,wm8962", },
3759 { }
3760};
3761MODULE_DEVICE_TABLE(of, wm8962_of_match);
3762
3761static struct i2c_driver wm8962_i2c_driver = { 3763static struct i2c_driver wm8962_i2c_driver = {
3762 .driver = { 3764 .driver = {
3763 .name = "wm8962", 3765 .name = "wm8962",
3764 .owner = THIS_MODULE, 3766 .owner = THIS_MODULE,
3767 .of_match_table = wm8962_of_match,
3765 .pm = &wm8962_pm, 3768 .pm = &wm8962_pm,
3766 }, 3769 },
3767 .probe = wm8962_i2c_probe, 3770 .probe = wm8962_i2c_probe,
diff --git a/sound/soc/codecs/wm8983.c b/sound/soc/codecs/wm8983.c
index 9fe1e041da49..c9c707b8698f 100644
--- a/sound/soc/codecs/wm8983.c
+++ b/sound/soc/codecs/wm8983.c
@@ -851,30 +851,33 @@ static int wm8983_set_pll(struct snd_soc_dai *dai, int pll_id,
851 struct pll_div pll_div; 851 struct pll_div pll_div;
852 852
853 codec = dai->codec; 853 codec = dai->codec;
854 if (freq_in && freq_out) { 854 if (!freq_in || !freq_out) {
855 /* disable the PLL */
856 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
857 WM8983_PLLEN_MASK, 0);
858 return 0;
859 } else {
855 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in); 860 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
856 if (ret) 861 if (ret)
857 return ret; 862 return ret;
858 }
859
860 /* disable the PLL before re-programming it */
861 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
862 WM8983_PLLEN_MASK, 0);
863 863
864 if (!freq_in || !freq_out) 864 /* disable the PLL before re-programming it */
865 return 0; 865 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
866 WM8983_PLLEN_MASK, 0);
867
868 /* set PLLN and PRESCALE */
869 snd_soc_write(codec, WM8983_PLL_N,
870 (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT)
871 | pll_div.n);
872 /* set PLLK */
873 snd_soc_write(codec, WM8983_PLL_K_3, pll_div.k & 0x1ff);
874 snd_soc_write(codec, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
875 snd_soc_write(codec, WM8983_PLL_K_1, (pll_div.k >> 18));
876 /* enable the PLL */
877 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
878 WM8983_PLLEN_MASK, WM8983_PLLEN);
879 }
866 880
867 /* set PLLN and PRESCALE */
868 snd_soc_write(codec, WM8983_PLL_N,
869 (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT)
870 | pll_div.n);
871 /* set PLLK */
872 snd_soc_write(codec, WM8983_PLL_K_3, pll_div.k & 0x1ff);
873 snd_soc_write(codec, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
874 snd_soc_write(codec, WM8983_PLL_K_1, (pll_div.k >> 18));
875 /* enable the PLL */
876 snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
877 WM8983_PLLEN_MASK, WM8983_PLLEN);
878 return 0; 881 return 0;
879} 882}
880 883
diff --git a/sound/soc/codecs/wm8985.c b/sound/soc/codecs/wm8985.c
index ab3782657ac8..dd6ce3bc01cf 100644
--- a/sound/soc/codecs/wm8985.c
+++ b/sound/soc/codecs/wm8985.c
@@ -830,33 +830,30 @@ static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id,
830 struct pll_div pll_div; 830 struct pll_div pll_div;
831 831
832 codec = dai->codec; 832 codec = dai->codec;
833 if (freq_in && freq_out) { 833 if (!freq_in || !freq_out) {
834 /* disable the PLL */
835 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
836 WM8985_PLLEN_MASK, 0);
837 } else {
834 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in); 838 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
835 if (ret) 839 if (ret)
836 return ret; 840 return ret;
837 }
838 841
839 /* disable the PLL before reprogramming it */ 842 /* set PLLN and PRESCALE */
840 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1, 843 snd_soc_write(codec, WM8985_PLL_N,
841 WM8985_PLLEN_MASK, 0); 844 (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT)
842 845 | pll_div.n);
843 if (!freq_in || !freq_out) 846 /* set PLLK */
844 return 0; 847 snd_soc_write(codec, WM8985_PLL_K_3, pll_div.k & 0x1ff);
845 848 snd_soc_write(codec, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
846 /* set PLLN and PRESCALE */ 849 snd_soc_write(codec, WM8985_PLL_K_1, (pll_div.k >> 18));
847 snd_soc_write(codec, WM8985_PLL_N, 850 /* set the source of the clock to be the PLL */
848 (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT) 851 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
849 | pll_div.n); 852 WM8985_CLKSEL_MASK, WM8985_CLKSEL);
850 /* set PLLK */ 853 /* enable the PLL */
851 snd_soc_write(codec, WM8985_PLL_K_3, pll_div.k & 0x1ff); 854 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
852 snd_soc_write(codec, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff); 855 WM8985_PLLEN_MASK, WM8985_PLLEN);
853 snd_soc_write(codec, WM8985_PLL_K_1, (pll_div.k >> 18)); 856 }
854 /* set the source of the clock to be the PLL */
855 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
856 WM8985_CLKSEL_MASK, WM8985_CLKSEL);
857 /* enable the PLL */
858 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
859 WM8985_PLLEN_MASK, WM8985_PLLEN);
860 return 0; 857 return 0;
861} 858}
862 859
diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c
index b6b654837585..f3f7e75f8628 100644
--- a/sound/soc/codecs/wm_adsp.c
+++ b/sound/soc/codecs/wm_adsp.c
@@ -15,6 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/delay.h> 16#include <linux/delay.h>
17#include <linux/firmware.h> 17#include <linux/firmware.h>
18#include <linux/list.h>
18#include <linux/pm.h> 19#include <linux/pm.h>
19#include <linux/pm_runtime.h> 20#include <linux/pm_runtime.h>
20#include <linux/regmap.h> 21#include <linux/regmap.h>
@@ -103,9 +104,19 @@
103#define ADSP1_START_SHIFT 0 /* DSP1_START */ 104#define ADSP1_START_SHIFT 0 /* DSP1_START */
104#define ADSP1_START_WIDTH 1 /* DSP1_START */ 105#define ADSP1_START_WIDTH 1 /* DSP1_START */
105 106
106#define ADSP2_CONTROL 0 107/*
107#define ADSP2_CLOCKING 1 108 * ADSP1 Control 31
108#define ADSP2_STATUS1 4 109 */
110#define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
111#define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
112#define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
113
114#define ADSP2_CONTROL 0x0
115#define ADSP2_CLOCKING 0x1
116#define ADSP2_STATUS1 0x4
117#define ADSP2_WDMA_CONFIG_1 0x30
118#define ADSP2_WDMA_CONFIG_2 0x31
119#define ADSP2_RDMA_CONFIG_1 0x34
109 120
110/* 121/*
111 * ADSP2 Control 122 * ADSP2 Control
@@ -143,6 +154,109 @@
143#define ADSP2_RAM_RDY_SHIFT 0 154#define ADSP2_RAM_RDY_SHIFT 0
144#define ADSP2_RAM_RDY_WIDTH 1 155#define ADSP2_RAM_RDY_WIDTH 1
145 156
157struct wm_adsp_buf {
158 struct list_head list;
159 void *buf;
160};
161
162static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
163 struct list_head *list)
164{
165 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
166
167 if (buf == NULL)
168 return NULL;
169
170 buf->buf = kmemdup(src, len, GFP_KERNEL | GFP_DMA);
171 if (!buf->buf) {
172 kfree(buf);
173 return NULL;
174 }
175
176 if (list)
177 list_add_tail(&buf->list, list);
178
179 return buf;
180}
181
182static void wm_adsp_buf_free(struct list_head *list)
183{
184 while (!list_empty(list)) {
185 struct wm_adsp_buf *buf = list_first_entry(list,
186 struct wm_adsp_buf,
187 list);
188 list_del(&buf->list);
189 kfree(buf->buf);
190 kfree(buf);
191 }
192}
193
194#define WM_ADSP_NUM_FW 4
195
196static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
197 "MBC/VSS", "Tx", "Tx Speaker", "Rx ANC"
198};
199
200static struct {
201 const char *file;
202} wm_adsp_fw[WM_ADSP_NUM_FW] = {
203 { .file = "mbc-vss" },
204 { .file = "tx" },
205 { .file = "tx-spk" },
206 { .file = "rx-anc" },
207};
208
209static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
210 struct snd_ctl_elem_value *ucontrol)
211{
212 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
213 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
214 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
215
216 ucontrol->value.integer.value[0] = adsp[e->shift_l].fw;
217
218 return 0;
219}
220
221static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
222 struct snd_ctl_elem_value *ucontrol)
223{
224 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
225 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
226 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
227
228 if (ucontrol->value.integer.value[0] == adsp[e->shift_l].fw)
229 return 0;
230
231 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
232 return -EINVAL;
233
234 if (adsp[e->shift_l].running)
235 return -EBUSY;
236
237 adsp[e->shift_l].fw = ucontrol->value.integer.value[0];
238
239 return 0;
240}
241
242static const struct soc_enum wm_adsp_fw_enum[] = {
243 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
244 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
245 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
246 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
247};
248
249const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
250 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
251 wm_adsp_fw_get, wm_adsp_fw_put),
252 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
253 wm_adsp_fw_get, wm_adsp_fw_put),
254 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
255 wm_adsp_fw_get, wm_adsp_fw_put),
256 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
257 wm_adsp_fw_get, wm_adsp_fw_put),
258};
259EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
146 260
147static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp, 261static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
148 int type) 262 int type)
@@ -156,8 +270,29 @@ static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
156 return NULL; 270 return NULL;
157} 271}
158 272
273static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *region,
274 unsigned int offset)
275{
276 switch (region->type) {
277 case WMFW_ADSP1_PM:
278 return region->base + (offset * 3);
279 case WMFW_ADSP1_DM:
280 return region->base + (offset * 2);
281 case WMFW_ADSP2_XM:
282 return region->base + (offset * 2);
283 case WMFW_ADSP2_YM:
284 return region->base + (offset * 2);
285 case WMFW_ADSP1_ZM:
286 return region->base + (offset * 2);
287 default:
288 WARN_ON(NULL != "Unknown memory region type");
289 return offset;
290 }
291}
292
159static int wm_adsp_load(struct wm_adsp *dsp) 293static int wm_adsp_load(struct wm_adsp *dsp)
160{ 294{
295 LIST_HEAD(buf_list);
161 const struct firmware *firmware; 296 const struct firmware *firmware;
162 struct regmap *regmap = dsp->regmap; 297 struct regmap *regmap = dsp->regmap;
163 unsigned int pos = 0; 298 unsigned int pos = 0;
@@ -169,7 +304,7 @@ static int wm_adsp_load(struct wm_adsp *dsp)
169 const struct wm_adsp_region *mem; 304 const struct wm_adsp_region *mem;
170 const char *region_name; 305 const char *region_name;
171 char *file, *text; 306 char *file, *text;
172 void *buf; 307 struct wm_adsp_buf *buf;
173 unsigned int reg; 308 unsigned int reg;
174 int regions = 0; 309 int regions = 0;
175 int ret, offset, type, sizes; 310 int ret, offset, type, sizes;
@@ -178,7 +313,8 @@ static int wm_adsp_load(struct wm_adsp *dsp)
178 if (file == NULL) 313 if (file == NULL)
179 return -ENOMEM; 314 return -ENOMEM;
180 315
181 snprintf(file, PAGE_SIZE, "%s-dsp%d.wmfw", dsp->part, dsp->num); 316 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
317 wm_adsp_fw[dsp->fw].file);
182 file[PAGE_SIZE - 1] = '\0'; 318 file[PAGE_SIZE - 1] = '\0';
183 319
184 ret = request_firmware(&firmware, file, dsp->dev); 320 ret = request_firmware(&firmware, file, dsp->dev);
@@ -283,27 +419,27 @@ static int wm_adsp_load(struct wm_adsp *dsp)
283 case WMFW_ADSP1_PM: 419 case WMFW_ADSP1_PM:
284 BUG_ON(!mem); 420 BUG_ON(!mem);
285 region_name = "PM"; 421 region_name = "PM";
286 reg = mem->base + (offset * 3); 422 reg = wm_adsp_region_to_reg(mem, offset);
287 break; 423 break;
288 case WMFW_ADSP1_DM: 424 case WMFW_ADSP1_DM:
289 BUG_ON(!mem); 425 BUG_ON(!mem);
290 region_name = "DM"; 426 region_name = "DM";
291 reg = mem->base + (offset * 2); 427 reg = wm_adsp_region_to_reg(mem, offset);
292 break; 428 break;
293 case WMFW_ADSP2_XM: 429 case WMFW_ADSP2_XM:
294 BUG_ON(!mem); 430 BUG_ON(!mem);
295 region_name = "XM"; 431 region_name = "XM";
296 reg = mem->base + (offset * 2); 432 reg = wm_adsp_region_to_reg(mem, offset);
297 break; 433 break;
298 case WMFW_ADSP2_YM: 434 case WMFW_ADSP2_YM:
299 BUG_ON(!mem); 435 BUG_ON(!mem);
300 region_name = "YM"; 436 region_name = "YM";
301 reg = mem->base + (offset * 2); 437 reg = wm_adsp_region_to_reg(mem, offset);
302 break; 438 break;
303 case WMFW_ADSP1_ZM: 439 case WMFW_ADSP1_ZM:
304 BUG_ON(!mem); 440 BUG_ON(!mem);
305 region_name = "ZM"; 441 region_name = "ZM";
306 reg = mem->base + (offset * 2); 442 reg = wm_adsp_region_to_reg(mem, offset);
307 break; 443 break;
308 default: 444 default:
309 adsp_warn(dsp, 445 adsp_warn(dsp,
@@ -323,18 +459,16 @@ static int wm_adsp_load(struct wm_adsp *dsp)
323 } 459 }
324 460
325 if (reg) { 461 if (reg) {
326 buf = kmemdup(region->data, le32_to_cpu(region->len), 462 buf = wm_adsp_buf_alloc(region->data,
327 GFP_KERNEL | GFP_DMA); 463 le32_to_cpu(region->len),
464 &buf_list);
328 if (!buf) { 465 if (!buf) {
329 adsp_err(dsp, "Out of memory\n"); 466 adsp_err(dsp, "Out of memory\n");
330 return -ENOMEM; 467 return -ENOMEM;
331 } 468 }
332 469
333 ret = regmap_raw_write(regmap, reg, buf, 470 ret = regmap_raw_write_async(regmap, reg, buf->buf,
334 le32_to_cpu(region->len)); 471 le32_to_cpu(region->len));
335
336 kfree(buf);
337
338 if (ret != 0) { 472 if (ret != 0) {
339 adsp_err(dsp, 473 adsp_err(dsp,
340 "%s.%d: Failed to write %d bytes at %d in %s: %d\n", 474 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
@@ -348,12 +482,20 @@ static int wm_adsp_load(struct wm_adsp *dsp)
348 pos += le32_to_cpu(region->len) + sizeof(*region); 482 pos += le32_to_cpu(region->len) + sizeof(*region);
349 regions++; 483 regions++;
350 } 484 }
351 485
486 ret = regmap_async_complete(regmap);
487 if (ret != 0) {
488 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
489 goto out_fw;
490 }
491
352 if (pos > firmware->size) 492 if (pos > firmware->size)
353 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", 493 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
354 file, regions, pos - firmware->size); 494 file, regions, pos - firmware->size);
355 495
356out_fw: 496out_fw:
497 regmap_async_complete(regmap);
498 wm_adsp_buf_free(&buf_list);
357 release_firmware(firmware); 499 release_firmware(firmware);
358out: 500out:
359 kfree(file); 501 kfree(file);
@@ -361,22 +503,222 @@ out:
361 return ret; 503 return ret;
362} 504}
363 505
506static int wm_adsp_setup_algs(struct wm_adsp *dsp)
507{
508 struct regmap *regmap = dsp->regmap;
509 struct wmfw_adsp1_id_hdr adsp1_id;
510 struct wmfw_adsp2_id_hdr adsp2_id;
511 struct wmfw_adsp1_alg_hdr *adsp1_alg;
512 struct wmfw_adsp2_alg_hdr *adsp2_alg;
513 void *alg, *buf;
514 struct wm_adsp_alg_region *region;
515 const struct wm_adsp_region *mem;
516 unsigned int pos, term;
517 size_t algs, buf_size;
518 __be32 val;
519 int i, ret;
520
521 switch (dsp->type) {
522 case WMFW_ADSP1:
523 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
524 break;
525 case WMFW_ADSP2:
526 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
527 break;
528 default:
529 mem = NULL;
530 break;
531 }
532
533 if (mem == NULL) {
534 BUG_ON(mem != NULL);
535 return -EINVAL;
536 }
537
538 switch (dsp->type) {
539 case WMFW_ADSP1:
540 ret = regmap_raw_read(regmap, mem->base, &adsp1_id,
541 sizeof(adsp1_id));
542 if (ret != 0) {
543 adsp_err(dsp, "Failed to read algorithm info: %d\n",
544 ret);
545 return ret;
546 }
547
548 buf = &adsp1_id;
549 buf_size = sizeof(adsp1_id);
550
551 algs = be32_to_cpu(adsp1_id.algs);
552 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
553 be32_to_cpu(adsp1_id.fw.id),
554 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
555 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
556 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
557 algs);
558
559 pos = sizeof(adsp1_id) / 2;
560 term = pos + ((sizeof(*adsp1_alg) * algs) / 2);
561 break;
562
563 case WMFW_ADSP2:
564 ret = regmap_raw_read(regmap, mem->base, &adsp2_id,
565 sizeof(adsp2_id));
566 if (ret != 0) {
567 adsp_err(dsp, "Failed to read algorithm info: %d\n",
568 ret);
569 return ret;
570 }
571
572 buf = &adsp2_id;
573 buf_size = sizeof(adsp2_id);
574
575 algs = be32_to_cpu(adsp2_id.algs);
576 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
577 be32_to_cpu(adsp2_id.fw.id),
578 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
579 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
580 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
581 algs);
582
583 pos = sizeof(adsp2_id) / 2;
584 term = pos + ((sizeof(*adsp2_alg) * algs) / 2);
585 break;
586
587 default:
588 BUG_ON(NULL == "Unknown DSP type");
589 return -EINVAL;
590 }
591
592 if (algs == 0) {
593 adsp_err(dsp, "No algorithms\n");
594 return -EINVAL;
595 }
596
597 if (algs > 1024) {
598 adsp_err(dsp, "Algorithm count %zx excessive\n", algs);
599 print_hex_dump_bytes(dev_name(dsp->dev), DUMP_PREFIX_OFFSET,
600 buf, buf_size);
601 return -EINVAL;
602 }
603
604 /* Read the terminator first to validate the length */
605 ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val));
606 if (ret != 0) {
607 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
608 ret);
609 return ret;
610 }
611
612 if (be32_to_cpu(val) != 0xbedead)
613 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
614 term, be32_to_cpu(val));
615
616 alg = kzalloc((term - pos) * 2, GFP_KERNEL | GFP_DMA);
617 if (!alg)
618 return -ENOMEM;
619
620 ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2);
621 if (ret != 0) {
622 adsp_err(dsp, "Failed to read algorithm list: %d\n",
623 ret);
624 goto out;
625 }
626
627 adsp1_alg = alg;
628 adsp2_alg = alg;
629
630 for (i = 0; i < algs; i++) {
631 switch (dsp->type) {
632 case WMFW_ADSP1:
633 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
634 i, be32_to_cpu(adsp1_alg[i].alg.id),
635 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
636 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
637 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
638 be32_to_cpu(adsp1_alg[i].dm),
639 be32_to_cpu(adsp1_alg[i].zm));
640
641 region = kzalloc(sizeof(*region), GFP_KERNEL);
642 if (!region)
643 return -ENOMEM;
644 region->type = WMFW_ADSP1_DM;
645 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
646 region->base = be32_to_cpu(adsp1_alg[i].dm);
647 list_add_tail(&region->list, &dsp->alg_regions);
648
649 region = kzalloc(sizeof(*region), GFP_KERNEL);
650 if (!region)
651 return -ENOMEM;
652 region->type = WMFW_ADSP1_ZM;
653 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
654 region->base = be32_to_cpu(adsp1_alg[i].zm);
655 list_add_tail(&region->list, &dsp->alg_regions);
656 break;
657
658 case WMFW_ADSP2:
659 adsp_info(dsp,
660 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
661 i, be32_to_cpu(adsp2_alg[i].alg.id),
662 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
663 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
664 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
665 be32_to_cpu(adsp2_alg[i].xm),
666 be32_to_cpu(adsp2_alg[i].ym),
667 be32_to_cpu(adsp2_alg[i].zm));
668
669 region = kzalloc(sizeof(*region), GFP_KERNEL);
670 if (!region)
671 return -ENOMEM;
672 region->type = WMFW_ADSP2_XM;
673 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
674 region->base = be32_to_cpu(adsp2_alg[i].xm);
675 list_add_tail(&region->list, &dsp->alg_regions);
676
677 region = kzalloc(sizeof(*region), GFP_KERNEL);
678 if (!region)
679 return -ENOMEM;
680 region->type = WMFW_ADSP2_YM;
681 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
682 region->base = be32_to_cpu(adsp2_alg[i].ym);
683 list_add_tail(&region->list, &dsp->alg_regions);
684
685 region = kzalloc(sizeof(*region), GFP_KERNEL);
686 if (!region)
687 return -ENOMEM;
688 region->type = WMFW_ADSP2_ZM;
689 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
690 region->base = be32_to_cpu(adsp2_alg[i].zm);
691 list_add_tail(&region->list, &dsp->alg_regions);
692 break;
693 }
694 }
695
696out:
697 kfree(alg);
698 return ret;
699}
700
364static int wm_adsp_load_coeff(struct wm_adsp *dsp) 701static int wm_adsp_load_coeff(struct wm_adsp *dsp)
365{ 702{
703 LIST_HEAD(buf_list);
366 struct regmap *regmap = dsp->regmap; 704 struct regmap *regmap = dsp->regmap;
367 struct wmfw_coeff_hdr *hdr; 705 struct wmfw_coeff_hdr *hdr;
368 struct wmfw_coeff_item *blk; 706 struct wmfw_coeff_item *blk;
369 const struct firmware *firmware; 707 const struct firmware *firmware;
708 const struct wm_adsp_region *mem;
709 struct wm_adsp_alg_region *alg_region;
370 const char *region_name; 710 const char *region_name;
371 int ret, pos, blocks, type, offset, reg; 711 int ret, pos, blocks, type, offset, reg;
372 char *file; 712 char *file;
373 void *buf; 713 struct wm_adsp_buf *buf;
714 int tmp;
374 715
375 file = kzalloc(PAGE_SIZE, GFP_KERNEL); 716 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
376 if (file == NULL) 717 if (file == NULL)
377 return -ENOMEM; 718 return -ENOMEM;
378 719
379 snprintf(file, PAGE_SIZE, "%s-dsp%d.bin", dsp->part, dsp->num); 720 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
721 wm_adsp_fw[dsp->fw].file);
380 file[PAGE_SIZE - 1] = '\0'; 722 file[PAGE_SIZE - 1] = '\0';
381 723
382 ret = request_firmware(&firmware, file, dsp->dev); 724 ret = request_firmware(&firmware, file, dsp->dev);
@@ -399,6 +741,16 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp)
399 goto out_fw; 741 goto out_fw;
400 } 742 }
401 743
744 switch (be32_to_cpu(hdr->rev) & 0xff) {
745 case 1:
746 break;
747 default:
748 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
749 file, be32_to_cpu(hdr->rev) & 0xff);
750 ret = -EINVAL;
751 goto out_fw;
752 }
753
402 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file, 754 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
403 (le32_to_cpu(hdr->ver) >> 16) & 0xff, 755 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
404 (le32_to_cpu(hdr->ver) >> 8) & 0xff, 756 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
@@ -411,8 +763,8 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp)
411 pos - firmware->size > sizeof(*blk)) { 763 pos - firmware->size > sizeof(*blk)) {
412 blk = (void*)(&firmware->data[pos]); 764 blk = (void*)(&firmware->data[pos]);
413 765
414 type = be32_to_cpu(blk->type) & 0xff; 766 type = le16_to_cpu(blk->type);
415 offset = le32_to_cpu(blk->offset) & 0xffffff; 767 offset = le16_to_cpu(blk->offset);
416 768
417 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", 769 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
418 file, blocks, le32_to_cpu(blk->id), 770 file, blocks, le32_to_cpu(blk->id),
@@ -425,52 +777,105 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp)
425 reg = 0; 777 reg = 0;
426 region_name = "Unknown"; 778 region_name = "Unknown";
427 switch (type) { 779 switch (type) {
428 case WMFW_NAME_TEXT: 780 case (WMFW_NAME_TEXT << 8):
429 case WMFW_INFO_TEXT: 781 case (WMFW_INFO_TEXT << 8):
430 break; 782 break;
431 case WMFW_ABSOLUTE: 783 case (WMFW_ABSOLUTE << 8):
432 region_name = "register"; 784 region_name = "register";
433 reg = offset; 785 reg = offset;
434 break; 786 break;
787
788 case WMFW_ADSP1_DM:
789 case WMFW_ADSP1_ZM:
790 case WMFW_ADSP2_XM:
791 case WMFW_ADSP2_YM:
792 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
793 file, blocks, le32_to_cpu(blk->len),
794 type, le32_to_cpu(blk->id));
795
796 mem = wm_adsp_find_region(dsp, type);
797 if (!mem) {
798 adsp_err(dsp, "No base for region %x\n", type);
799 break;
800 }
801
802 reg = 0;
803 list_for_each_entry(alg_region,
804 &dsp->alg_regions, list) {
805 if (le32_to_cpu(blk->id) == alg_region->alg &&
806 type == alg_region->type) {
807 reg = alg_region->base;
808 reg = wm_adsp_region_to_reg(mem,
809 reg);
810 reg += offset;
811 }
812 }
813
814 if (reg == 0)
815 adsp_err(dsp, "No %x for algorithm %x\n",
816 type, le32_to_cpu(blk->id));
817 break;
818
435 default: 819 default:
436 adsp_err(dsp, "Unknown region type %x\n", type); 820 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
821 file, blocks, type, pos);
437 break; 822 break;
438 } 823 }
439 824
440 if (reg) { 825 if (reg) {
441 buf = kmemdup(blk->data, le32_to_cpu(blk->len), 826 buf = wm_adsp_buf_alloc(blk->data,
442 GFP_KERNEL | GFP_DMA); 827 le32_to_cpu(blk->len),
828 &buf_list);
443 if (!buf) { 829 if (!buf) {
444 adsp_err(dsp, "Out of memory\n"); 830 adsp_err(dsp, "Out of memory\n");
445 return -ENOMEM; 831 return -ENOMEM;
446 } 832 }
447 833
448 ret = regmap_raw_write(regmap, reg, blk->data, 834 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
449 le32_to_cpu(blk->len)); 835 file, blocks, le32_to_cpu(blk->len),
836 reg);
837 ret = regmap_raw_write_async(regmap, reg, buf->buf,
838 le32_to_cpu(blk->len));
450 if (ret != 0) { 839 if (ret != 0) {
451 adsp_err(dsp, 840 adsp_err(dsp,
452 "%s.%d: Failed to write to %x in %s\n", 841 "%s.%d: Failed to write to %x in %s\n",
453 file, blocks, reg, region_name); 842 file, blocks, reg, region_name);
454 } 843 }
455
456 kfree(buf);
457 } 844 }
458 845
459 pos += le32_to_cpu(blk->len) + sizeof(*blk); 846 tmp = le32_to_cpu(blk->len) % 4;
847 if (tmp)
848 pos += le32_to_cpu(blk->len) + (4 - tmp) + sizeof(*blk);
849 else
850 pos += le32_to_cpu(blk->len) + sizeof(*blk);
851
460 blocks++; 852 blocks++;
461 } 853 }
462 854
855 ret = regmap_async_complete(regmap);
856 if (ret != 0)
857 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
858
463 if (pos > firmware->size) 859 if (pos > firmware->size)
464 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", 860 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
465 file, blocks, pos - firmware->size); 861 file, blocks, pos - firmware->size);
466 862
467out_fw: 863out_fw:
468 release_firmware(firmware); 864 release_firmware(firmware);
865 wm_adsp_buf_free(&buf_list);
469out: 866out:
470 kfree(file); 867 kfree(file);
471 return 0; 868 return 0;
472} 869}
473 870
871int wm_adsp1_init(struct wm_adsp *adsp)
872{
873 INIT_LIST_HEAD(&adsp->alg_regions);
874
875 return 0;
876}
877EXPORT_SYMBOL_GPL(wm_adsp1_init);
878
474int wm_adsp1_event(struct snd_soc_dapm_widget *w, 879int wm_adsp1_event(struct snd_soc_dapm_widget *w,
475 struct snd_kcontrol *kcontrol, 880 struct snd_kcontrol *kcontrol,
476 int event) 881 int event)
@@ -479,16 +884,46 @@ int wm_adsp1_event(struct snd_soc_dapm_widget *w,
479 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); 884 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
480 struct wm_adsp *dsp = &dsps[w->shift]; 885 struct wm_adsp *dsp = &dsps[w->shift];
481 int ret; 886 int ret;
887 int val;
482 888
483 switch (event) { 889 switch (event) {
484 case SND_SOC_DAPM_POST_PMU: 890 case SND_SOC_DAPM_POST_PMU:
485 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 891 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
486 ADSP1_SYS_ENA, ADSP1_SYS_ENA); 892 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
487 893
894 /*
895 * For simplicity set the DSP clock rate to be the
896 * SYSCLK rate rather than making it configurable.
897 */
898 if(dsp->sysclk_reg) {
899 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
900 if (ret != 0) {
901 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
902 ret);
903 return ret;
904 }
905
906 val = (val & dsp->sysclk_mask)
907 >> dsp->sysclk_shift;
908
909 ret = regmap_update_bits(dsp->regmap,
910 dsp->base + ADSP1_CONTROL_31,
911 ADSP1_CLK_SEL_MASK, val);
912 if (ret != 0) {
913 adsp_err(dsp, "Failed to set clock rate: %d\n",
914 ret);
915 return ret;
916 }
917 }
918
488 ret = wm_adsp_load(dsp); 919 ret = wm_adsp_load(dsp);
489 if (ret != 0) 920 if (ret != 0)
490 goto err; 921 goto err;
491 922
923 ret = wm_adsp_setup_algs(dsp);
924 if (ret != 0)
925 goto err;
926
492 ret = wm_adsp_load_coeff(dsp); 927 ret = wm_adsp_load_coeff(dsp);
493 if (ret != 0) 928 if (ret != 0)
494 goto err; 929 goto err;
@@ -560,6 +995,7 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w,
560 struct snd_soc_codec *codec = w->codec; 995 struct snd_soc_codec *codec = w->codec;
561 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); 996 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
562 struct wm_adsp *dsp = &dsps[w->shift]; 997 struct wm_adsp *dsp = &dsps[w->shift];
998 struct wm_adsp_alg_region *alg_region;
563 unsigned int val; 999 unsigned int val;
564 int ret; 1000 int ret;
565 1001
@@ -625,6 +1061,10 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w,
625 if (ret != 0) 1061 if (ret != 0)
626 goto err; 1062 goto err;
627 1063
1064 ret = wm_adsp_setup_algs(dsp);
1065 if (ret != 0)
1066 goto err;
1067
628 ret = wm_adsp_load_coeff(dsp); 1068 ret = wm_adsp_load_coeff(dsp);
629 if (ret != 0) 1069 if (ret != 0)
630 goto err; 1070 goto err;
@@ -635,13 +1075,22 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w,
635 ADSP2_CORE_ENA | ADSP2_START); 1075 ADSP2_CORE_ENA | ADSP2_START);
636 if (ret != 0) 1076 if (ret != 0)
637 goto err; 1077 goto err;
1078
1079 dsp->running = true;
638 break; 1080 break;
639 1081
640 case SND_SOC_DAPM_PRE_PMD: 1082 case SND_SOC_DAPM_PRE_PMD:
1083 dsp->running = false;
1084
641 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 1085 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
642 ADSP2_SYS_ENA | ADSP2_CORE_ENA | 1086 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
643 ADSP2_START, 0); 1087 ADSP2_START, 0);
644 1088
1089 /* Make sure DMAs are quiesced */
1090 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
1091 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
1092 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
1093
645 if (dsp->dvfs) { 1094 if (dsp->dvfs) {
646 ret = regulator_set_voltage(dsp->dvfs, 1200000, 1095 ret = regulator_set_voltage(dsp->dvfs, 1200000,
647 1800000); 1096 1800000);
@@ -656,6 +1105,14 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w,
656 "Failed to enable supply: %d\n", 1105 "Failed to enable supply: %d\n",
657 ret); 1106 ret);
658 } 1107 }
1108
1109 while (!list_empty(&dsp->alg_regions)) {
1110 alg_region = list_first_entry(&dsp->alg_regions,
1111 struct wm_adsp_alg_region,
1112 list);
1113 list_del(&alg_region->list);
1114 kfree(alg_region);
1115 }
659 break; 1116 break;
660 1117
661 default: 1118 default:
@@ -685,6 +1142,8 @@ int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)
685 return ret; 1142 return ret;
686 } 1143 }
687 1144
1145 INIT_LIST_HEAD(&adsp->alg_regions);
1146
688 if (dvfs) { 1147 if (dvfs) {
689 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD"); 1148 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
690 if (IS_ERR(adsp->dvfs)) { 1149 if (IS_ERR(adsp->dvfs)) {
diff --git a/sound/soc/codecs/wm_adsp.h b/sound/soc/codecs/wm_adsp.h
index ffd29a4609e2..cb8871a3ec00 100644
--- a/sound/soc/codecs/wm_adsp.h
+++ b/sound/soc/codecs/wm_adsp.h
@@ -25,6 +25,13 @@ struct wm_adsp_region {
25 unsigned int base; 25 unsigned int base;
26}; 26};
27 27
28struct wm_adsp_alg_region {
29 struct list_head list;
30 unsigned int alg;
31 int type;
32 unsigned int base;
33};
34
28struct wm_adsp { 35struct wm_adsp {
29 const char *part; 36 const char *part;
30 int num; 37 int num;
@@ -33,10 +40,18 @@ struct wm_adsp {
33 struct regmap *regmap; 40 struct regmap *regmap;
34 41
35 int base; 42 int base;
43 int sysclk_reg;
44 int sysclk_mask;
45 int sysclk_shift;
46
47 struct list_head alg_regions;
36 48
37 const struct wm_adsp_region *mem; 49 const struct wm_adsp_region *mem;
38 int num_mems; 50 int num_mems;
39 51
52 int fw;
53 bool running;
54
40 struct regulator *dvfs; 55 struct regulator *dvfs;
41}; 56};
42 57
@@ -50,6 +65,9 @@ struct wm_adsp {
50 .shift = num, .event = wm_adsp2_event, \ 65 .shift = num, .event = wm_adsp2_event, \
51 .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD } 66 .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD }
52 67
68extern const struct snd_kcontrol_new wm_adsp_fw_controls[];
69
70int wm_adsp1_init(struct wm_adsp *adsp);
53int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs); 71int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs);
54int wm_adsp1_event(struct snd_soc_dapm_widget *w, 72int wm_adsp1_event(struct snd_soc_dapm_widget *w,
55 struct snd_kcontrol *kcontrol, int event); 73 struct snd_kcontrol *kcontrol, int event);
diff --git a/sound/soc/codecs/wmfw.h b/sound/soc/codecs/wmfw.h
index 5632ded67fdd..ef163360a745 100644
--- a/sound/soc/codecs/wmfw.h
+++ b/sound/soc/codecs/wmfw.h
@@ -93,15 +93,20 @@ struct wmfw_adsp2_alg_hdr {
93struct wmfw_coeff_hdr { 93struct wmfw_coeff_hdr {
94 u8 magic[4]; 94 u8 magic[4];
95 __le32 len; 95 __le32 len;
96 __le32 ver; 96 union {
97 __be32 rev;
98 __le32 ver;
99 };
100 union {
101 __be32 core;
102 __le32 core_ver;
103 };
97 u8 data[]; 104 u8 data[];
98} __packed; 105} __packed;
99 106
100struct wmfw_coeff_item { 107struct wmfw_coeff_item {
101 union { 108 __le16 offset;
102 __be32 type; 109 __le16 type;
103 __le32 offset;
104 };
105 __le32 id; 110 __le32 id;
106 __le32 ver; 111 __le32 ver;
107 __le32 sr; 112 __le32 sr;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 13:16:14 -0500