diff options
Diffstat (limited to 'sound/soc/codecs/sta32x.c')
-rw-r--r-- | sound/soc/codecs/sta32x.c | 534 |
1 files changed, 338 insertions, 196 deletions
diff --git a/sound/soc/codecs/sta32x.c b/sound/soc/codecs/sta32x.c index 7e18200dd6a9..3a1343fa109b 100644 --- a/sound/soc/codecs/sta32x.c +++ b/sound/soc/codecs/sta32x.c | |||
@@ -24,8 +24,11 @@ | |||
24 | #include <linux/delay.h> | 24 | #include <linux/delay.h> |
25 | #include <linux/pm.h> | 25 | #include <linux/pm.h> |
26 | #include <linux/i2c.h> | 26 | #include <linux/i2c.h> |
27 | #include <linux/of_device.h> | ||
28 | #include <linux/of_gpio.h> | ||
27 | #include <linux/regmap.h> | 29 | #include <linux/regmap.h> |
28 | #include <linux/regulator/consumer.h> | 30 | #include <linux/regulator/consumer.h> |
31 | #include <linux/gpio/consumer.h> | ||
29 | #include <linux/slab.h> | 32 | #include <linux/slab.h> |
30 | #include <linux/workqueue.h> | 33 | #include <linux/workqueue.h> |
31 | #include <sound/core.h> | 34 | #include <sound/core.h> |
@@ -102,6 +105,35 @@ static const struct reg_default sta32x_regs[] = { | |||
102 | { 0x2c, 0x0c }, | 105 | { 0x2c, 0x0c }, |
103 | }; | 106 | }; |
104 | 107 | ||
108 | static const struct regmap_range sta32x_write_regs_range[] = { | ||
109 | regmap_reg_range(STA32X_CONFA, STA32X_AUTO2), | ||
110 | regmap_reg_range(STA32X_C1CFG, STA32X_FDRC2), | ||
111 | }; | ||
112 | |||
113 | static const struct regmap_range sta32x_read_regs_range[] = { | ||
114 | regmap_reg_range(STA32X_CONFA, STA32X_AUTO2), | ||
115 | regmap_reg_range(STA32X_C1CFG, STA32X_FDRC2), | ||
116 | }; | ||
117 | |||
118 | static const struct regmap_range sta32x_volatile_regs_range[] = { | ||
119 | regmap_reg_range(STA32X_CFADDR2, STA32X_CFUD), | ||
120 | }; | ||
121 | |||
122 | static const struct regmap_access_table sta32x_write_regs = { | ||
123 | .yes_ranges = sta32x_write_regs_range, | ||
124 | .n_yes_ranges = ARRAY_SIZE(sta32x_write_regs_range), | ||
125 | }; | ||
126 | |||
127 | static const struct regmap_access_table sta32x_read_regs = { | ||
128 | .yes_ranges = sta32x_read_regs_range, | ||
129 | .n_yes_ranges = ARRAY_SIZE(sta32x_read_regs_range), | ||
130 | }; | ||
131 | |||
132 | static const struct regmap_access_table sta32x_volatile_regs = { | ||
133 | .yes_ranges = sta32x_volatile_regs_range, | ||
134 | .n_yes_ranges = ARRAY_SIZE(sta32x_volatile_regs_range), | ||
135 | }; | ||
136 | |||
105 | /* regulator power supply names */ | 137 | /* regulator power supply names */ |
106 | static const char *sta32x_supply_names[] = { | 138 | static const char *sta32x_supply_names[] = { |
107 | "Vdda", /* analog supply, 3.3VV */ | 139 | "Vdda", /* analog supply, 3.3VV */ |
@@ -122,6 +154,8 @@ struct sta32x_priv { | |||
122 | u32 coef_shadow[STA32X_COEF_COUNT]; | 154 | u32 coef_shadow[STA32X_COEF_COUNT]; |
123 | struct delayed_work watchdog_work; | 155 | struct delayed_work watchdog_work; |
124 | int shutdown; | 156 | int shutdown; |
157 | struct gpio_desc *gpiod_nreset; | ||
158 | struct mutex coeff_lock; | ||
125 | }; | 159 | }; |
126 | 160 | ||
127 | static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1); | 161 | static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1); |
@@ -155,37 +189,32 @@ static const char *sta32x_limiter_release_rate[] = { | |||
155 | "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299", | 189 | "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299", |
156 | "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137", | 190 | "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137", |
157 | "0.0134", "0.0117", "0.0110", "0.0104" }; | 191 | "0.0134", "0.0117", "0.0110", "0.0104" }; |
158 | 192 | static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_attack_tlv, | |
159 | static const unsigned int sta32x_limiter_ac_attack_tlv[] = { | ||
160 | TLV_DB_RANGE_HEAD(2), | ||
161 | 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0), | 193 | 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0), |
162 | 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0), | 194 | 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0), |
163 | }; | 195 | ); |
164 | 196 | ||
165 | static const unsigned int sta32x_limiter_ac_release_tlv[] = { | 197 | static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_release_tlv, |
166 | TLV_DB_RANGE_HEAD(5), | ||
167 | 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), | 198 | 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), |
168 | 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0), | 199 | 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0), |
169 | 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0), | 200 | 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0), |
170 | 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0), | 201 | 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0), |
171 | 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0), | 202 | 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0), |
172 | }; | 203 | ); |
173 | 204 | ||
174 | static const unsigned int sta32x_limiter_drc_attack_tlv[] = { | 205 | static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_attack_tlv, |
175 | TLV_DB_RANGE_HEAD(3), | ||
176 | 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0), | 206 | 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0), |
177 | 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0), | 207 | 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0), |
178 | 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0), | 208 | 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0), |
179 | }; | 209 | ); |
180 | 210 | ||
181 | static const unsigned int sta32x_limiter_drc_release_tlv[] = { | 211 | static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_release_tlv, |
182 | TLV_DB_RANGE_HEAD(5), | ||
183 | 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), | 212 | 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0), |
184 | 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0), | 213 | 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0), |
185 | 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0), | 214 | 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0), |
186 | 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0), | 215 | 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0), |
187 | 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0), | 216 | 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0), |
188 | }; | 217 | ); |
189 | 218 | ||
190 | static SOC_ENUM_SINGLE_DECL(sta32x_drc_ac_enum, | 219 | static SOC_ENUM_SINGLE_DECL(sta32x_drc_ac_enum, |
191 | STA32X_CONFD, STA32X_CONFD_DRC_SHIFT, | 220 | STA32X_CONFD, STA32X_CONFD_DRC_SHIFT, |
@@ -244,29 +273,42 @@ static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol, | |||
244 | struct snd_ctl_elem_value *ucontrol) | 273 | struct snd_ctl_elem_value *ucontrol) |
245 | { | 274 | { |
246 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); | 275 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
276 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | ||
247 | int numcoef = kcontrol->private_value >> 16; | 277 | int numcoef = kcontrol->private_value >> 16; |
248 | int index = kcontrol->private_value & 0xffff; | 278 | int index = kcontrol->private_value & 0xffff; |
249 | unsigned int cfud; | 279 | unsigned int cfud, val; |
250 | int i; | 280 | int i, ret = 0; |
281 | |||
282 | mutex_lock(&sta32x->coeff_lock); | ||
251 | 283 | ||
252 | /* preserve reserved bits in STA32X_CFUD */ | 284 | /* preserve reserved bits in STA32X_CFUD */ |
253 | cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0; | 285 | regmap_read(sta32x->regmap, STA32X_CFUD, &cfud); |
254 | /* chip documentation does not say if the bits are self clearing, | 286 | cfud &= 0xf0; |
255 | * so do it explicitly */ | 287 | /* |
256 | snd_soc_write(codec, STA32X_CFUD, cfud); | 288 | * chip documentation does not say if the bits are self clearing, |
289 | * so do it explicitly | ||
290 | */ | ||
291 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud); | ||
257 | 292 | ||
258 | snd_soc_write(codec, STA32X_CFADDR2, index); | 293 | regmap_write(sta32x->regmap, STA32X_CFADDR2, index); |
259 | if (numcoef == 1) | 294 | if (numcoef == 1) { |
260 | snd_soc_write(codec, STA32X_CFUD, cfud | 0x04); | 295 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x04); |
261 | else if (numcoef == 5) | 296 | } else if (numcoef == 5) { |
262 | snd_soc_write(codec, STA32X_CFUD, cfud | 0x08); | 297 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x08); |
263 | else | 298 | } else { |
264 | return -EINVAL; | 299 | ret = -EINVAL; |
265 | for (i = 0; i < 3 * numcoef; i++) | 300 | goto exit_unlock; |
266 | ucontrol->value.bytes.data[i] = | 301 | } |
267 | snd_soc_read(codec, STA32X_B1CF1 + i); | ||
268 | 302 | ||
269 | return 0; | 303 | for (i = 0; i < 3 * numcoef; i++) { |
304 | regmap_read(sta32x->regmap, STA32X_B1CF1 + i, &val); | ||
305 | ucontrol->value.bytes.data[i] = val; | ||
306 | } | ||
307 | |||
308 | exit_unlock: | ||
309 | mutex_unlock(&sta32x->coeff_lock); | ||
310 | |||
311 | return ret; | ||
270 | } | 312 | } |
271 | 313 | ||
272 | static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol, | 314 | static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol, |
@@ -280,24 +322,27 @@ static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol, | |||
280 | int i; | 322 | int i; |
281 | 323 | ||
282 | /* preserve reserved bits in STA32X_CFUD */ | 324 | /* preserve reserved bits in STA32X_CFUD */ |
283 | cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0; | 325 | regmap_read(sta32x->regmap, STA32X_CFUD, &cfud); |
284 | /* chip documentation does not say if the bits are self clearing, | 326 | cfud &= 0xf0; |
285 | * so do it explicitly */ | 327 | /* |
286 | snd_soc_write(codec, STA32X_CFUD, cfud); | 328 | * chip documentation does not say if the bits are self clearing, |
329 | * so do it explicitly | ||
330 | */ | ||
331 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud); | ||
287 | 332 | ||
288 | snd_soc_write(codec, STA32X_CFADDR2, index); | 333 | regmap_write(sta32x->regmap, STA32X_CFADDR2, index); |
289 | for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++) | 334 | for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++) |
290 | sta32x->coef_shadow[index + i] = | 335 | sta32x->coef_shadow[index + i] = |
291 | (ucontrol->value.bytes.data[3 * i] << 16) | 336 | (ucontrol->value.bytes.data[3 * i] << 16) |
292 | | (ucontrol->value.bytes.data[3 * i + 1] << 8) | 337 | | (ucontrol->value.bytes.data[3 * i + 1] << 8) |
293 | | (ucontrol->value.bytes.data[3 * i + 2]); | 338 | | (ucontrol->value.bytes.data[3 * i + 2]); |
294 | for (i = 0; i < 3 * numcoef; i++) | 339 | for (i = 0; i < 3 * numcoef; i++) |
295 | snd_soc_write(codec, STA32X_B1CF1 + i, | 340 | regmap_write(sta32x->regmap, STA32X_B1CF1 + i, |
296 | ucontrol->value.bytes.data[i]); | 341 | ucontrol->value.bytes.data[i]); |
297 | if (numcoef == 1) | 342 | if (numcoef == 1) |
298 | snd_soc_write(codec, STA32X_CFUD, cfud | 0x01); | 343 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01); |
299 | else if (numcoef == 5) | 344 | else if (numcoef == 5) |
300 | snd_soc_write(codec, STA32X_CFUD, cfud | 0x02); | 345 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x02); |
301 | else | 346 | else |
302 | return -EINVAL; | 347 | return -EINVAL; |
303 | 348 | ||
@@ -311,20 +356,23 @@ static int sta32x_sync_coef_shadow(struct snd_soc_codec *codec) | |||
311 | int i; | 356 | int i; |
312 | 357 | ||
313 | /* preserve reserved bits in STA32X_CFUD */ | 358 | /* preserve reserved bits in STA32X_CFUD */ |
314 | cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0; | 359 | regmap_read(sta32x->regmap, STA32X_CFUD, &cfud); |
360 | cfud &= 0xf0; | ||
315 | 361 | ||
316 | for (i = 0; i < STA32X_COEF_COUNT; i++) { | 362 | for (i = 0; i < STA32X_COEF_COUNT; i++) { |
317 | snd_soc_write(codec, STA32X_CFADDR2, i); | 363 | regmap_write(sta32x->regmap, STA32X_CFADDR2, i); |
318 | snd_soc_write(codec, STA32X_B1CF1, | 364 | regmap_write(sta32x->regmap, STA32X_B1CF1, |
319 | (sta32x->coef_shadow[i] >> 16) & 0xff); | 365 | (sta32x->coef_shadow[i] >> 16) & 0xff); |
320 | snd_soc_write(codec, STA32X_B1CF2, | 366 | regmap_write(sta32x->regmap, STA32X_B1CF2, |
321 | (sta32x->coef_shadow[i] >> 8) & 0xff); | 367 | (sta32x->coef_shadow[i] >> 8) & 0xff); |
322 | snd_soc_write(codec, STA32X_B1CF3, | 368 | regmap_write(sta32x->regmap, STA32X_B1CF3, |
323 | (sta32x->coef_shadow[i]) & 0xff); | 369 | (sta32x->coef_shadow[i]) & 0xff); |
324 | /* chip documentation does not say if the bits are | 370 | /* |
325 | * self-clearing, so do it explicitly */ | 371 | * chip documentation does not say if the bits are |
326 | snd_soc_write(codec, STA32X_CFUD, cfud); | 372 | * self-clearing, so do it explicitly |
327 | snd_soc_write(codec, STA32X_CFUD, cfud | 0x01); | 373 | */ |
374 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud); | ||
375 | regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01); | ||
328 | } | 376 | } |
329 | return 0; | 377 | return 0; |
330 | } | 378 | } |
@@ -336,11 +384,11 @@ static int sta32x_cache_sync(struct snd_soc_codec *codec) | |||
336 | int rc; | 384 | int rc; |
337 | 385 | ||
338 | /* mute during register sync */ | 386 | /* mute during register sync */ |
339 | mute = snd_soc_read(codec, STA32X_MMUTE); | 387 | regmap_read(sta32x->regmap, STA32X_MMUTE, &mute); |
340 | snd_soc_write(codec, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE); | 388 | regmap_write(sta32x->regmap, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE); |
341 | sta32x_sync_coef_shadow(codec); | 389 | sta32x_sync_coef_shadow(codec); |
342 | rc = regcache_sync(sta32x->regmap); | 390 | rc = regcache_sync(sta32x->regmap); |
343 | snd_soc_write(codec, STA32X_MMUTE, mute); | 391 | regmap_write(sta32x->regmap, STA32X_MMUTE, mute); |
344 | return rc; | 392 | return rc; |
345 | } | 393 | } |
346 | 394 | ||
@@ -508,17 +556,12 @@ static struct { | |||
508 | }; | 556 | }; |
509 | 557 | ||
510 | /* MCLK to fs clock ratios */ | 558 | /* MCLK to fs clock ratios */ |
511 | static struct { | 559 | static int mcs_ratio_table[3][7] = { |
512 | int ratio; | 560 | { 768, 512, 384, 256, 128, 576, 0 }, |
513 | int mcs; | 561 | { 384, 256, 192, 128, 64, 0 }, |
514 | } mclk_ratios[3][7] = { | 562 | { 384, 256, 192, 128, 64, 0 }, |
515 | { { 768, 0 }, { 512, 1 }, { 384, 2 }, { 256, 3 }, | ||
516 | { 128, 4 }, { 576, 5 }, { 0, 0 } }, | ||
517 | { { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } }, | ||
518 | { { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } }, | ||
519 | }; | 563 | }; |
520 | 564 | ||
521 | |||
522 | /** | 565 | /** |
523 | * sta32x_set_dai_sysclk - configure MCLK | 566 | * sta32x_set_dai_sysclk - configure MCLK |
524 | * @codec_dai: the codec DAI | 567 | * @codec_dai: the codec DAI |
@@ -543,46 +586,10 @@ static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |||
543 | { | 586 | { |
544 | struct snd_soc_codec *codec = codec_dai->codec; | 587 | struct snd_soc_codec *codec = codec_dai->codec; |
545 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | 588 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); |
546 | int i, j, ir, fs; | ||
547 | unsigned int rates = 0; | ||
548 | unsigned int rate_min = -1; | ||
549 | unsigned int rate_max = 0; | ||
550 | 589 | ||
551 | pr_debug("mclk=%u\n", freq); | 590 | dev_dbg(codec->dev, "mclk=%u\n", freq); |
552 | sta32x->mclk = freq; | 591 | sta32x->mclk = freq; |
553 | 592 | ||
554 | if (sta32x->mclk) { | ||
555 | for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) { | ||
556 | ir = interpolation_ratios[i].ir; | ||
557 | fs = interpolation_ratios[i].fs; | ||
558 | for (j = 0; mclk_ratios[ir][j].ratio; j++) { | ||
559 | if (mclk_ratios[ir][j].ratio * fs == freq) { | ||
560 | rates |= snd_pcm_rate_to_rate_bit(fs); | ||
561 | if (fs < rate_min) | ||
562 | rate_min = fs; | ||
563 | if (fs > rate_max) | ||
564 | rate_max = fs; | ||
565 | break; | ||
566 | } | ||
567 | } | ||
568 | } | ||
569 | /* FIXME: soc should support a rate list */ | ||
570 | rates &= ~SNDRV_PCM_RATE_KNOT; | ||
571 | |||
572 | if (!rates) { | ||
573 | dev_err(codec->dev, "could not find a valid sample rate\n"); | ||
574 | return -EINVAL; | ||
575 | } | ||
576 | } else { | ||
577 | /* enable all possible rates */ | ||
578 | rates = STA32X_RATES; | ||
579 | rate_min = 32000; | ||
580 | rate_max = 192000; | ||
581 | } | ||
582 | |||
583 | codec_dai->driver->playback.rates = rates; | ||
584 | codec_dai->driver->playback.rate_min = rate_min; | ||
585 | codec_dai->driver->playback.rate_max = rate_max; | ||
586 | return 0; | 593 | return 0; |
587 | } | 594 | } |
588 | 595 | ||
@@ -599,10 +606,7 @@ static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai, | |||
599 | { | 606 | { |
600 | struct snd_soc_codec *codec = codec_dai->codec; | 607 | struct snd_soc_codec *codec = codec_dai->codec; |
601 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | 608 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); |
602 | u8 confb = snd_soc_read(codec, STA32X_CONFB); | 609 | u8 confb = 0; |
603 | |||
604 | pr_debug("\n"); | ||
605 | confb &= ~(STA32X_CONFB_C1IM | STA32X_CONFB_C2IM); | ||
606 | 610 | ||
607 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | 611 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
608 | case SND_SOC_DAIFMT_CBS_CFS: | 612 | case SND_SOC_DAIFMT_CBS_CFS: |
@@ -632,8 +636,8 @@ static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai, | |||
632 | return -EINVAL; | 636 | return -EINVAL; |
633 | } | 637 | } |
634 | 638 | ||
635 | snd_soc_write(codec, STA32X_CONFB, confb); | 639 | return regmap_update_bits(sta32x->regmap, STA32X_CONFB, |
636 | return 0; | 640 | STA32X_CONFB_C1IM | STA32X_CONFB_C2IM, confb); |
637 | } | 641 | } |
638 | 642 | ||
639 | /** | 643 | /** |
@@ -651,39 +655,55 @@ static int sta32x_hw_params(struct snd_pcm_substream *substream, | |||
651 | { | 655 | { |
652 | struct snd_soc_codec *codec = dai->codec; | 656 | struct snd_soc_codec *codec = dai->codec; |
653 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | 657 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); |
654 | unsigned int rate; | 658 | int i, mcs = -EINVAL, ir = -EINVAL; |
655 | int i, mcs = -1, ir = -1; | 659 | unsigned int confa, confb; |
656 | u8 confa, confb; | 660 | unsigned int rate, ratio; |
661 | int ret; | ||
662 | |||
663 | if (!sta32x->mclk) { | ||
664 | dev_err(codec->dev, | ||
665 | "sta32x->mclk is unset. Unable to determine ratio\n"); | ||
666 | return -EIO; | ||
667 | } | ||
657 | 668 | ||
658 | rate = params_rate(params); | 669 | rate = params_rate(params); |
659 | pr_debug("rate: %u\n", rate); | 670 | ratio = sta32x->mclk / rate; |
660 | for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) | 671 | dev_dbg(codec->dev, "rate: %u, ratio: %u\n", rate, ratio); |
672 | |||
673 | for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) { | ||
661 | if (interpolation_ratios[i].fs == rate) { | 674 | if (interpolation_ratios[i].fs == rate) { |
662 | ir = interpolation_ratios[i].ir; | 675 | ir = interpolation_ratios[i].ir; |
663 | break; | 676 | break; |
664 | } | 677 | } |
665 | if (ir < 0) | 678 | } |
679 | |||
680 | if (ir < 0) { | ||
681 | dev_err(codec->dev, "Unsupported samplerate: %u\n", rate); | ||
666 | return -EINVAL; | 682 | return -EINVAL; |
667 | for (i = 0; mclk_ratios[ir][i].ratio; i++) | 683 | } |
668 | if (mclk_ratios[ir][i].ratio * rate == sta32x->mclk) { | 684 | |
669 | mcs = mclk_ratios[ir][i].mcs; | 685 | for (i = 0; i < 6; i++) { |
686 | if (mcs_ratio_table[ir][i] == ratio) { | ||
687 | mcs = i; | ||
670 | break; | 688 | break; |
671 | } | 689 | } |
672 | if (mcs < 0) | 690 | } |
691 | |||
692 | if (mcs < 0) { | ||
693 | dev_err(codec->dev, "Unresolvable ratio: %u\n", ratio); | ||
673 | return -EINVAL; | 694 | return -EINVAL; |
695 | } | ||
674 | 696 | ||
675 | confa = snd_soc_read(codec, STA32X_CONFA); | 697 | confa = (ir << STA32X_CONFA_IR_SHIFT) | |
676 | confa &= ~(STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK); | 698 | (mcs << STA32X_CONFA_MCS_SHIFT); |
677 | confa |= (ir << STA32X_CONFA_IR_SHIFT) | (mcs << STA32X_CONFA_MCS_SHIFT); | 699 | confb = 0; |
678 | 700 | ||
679 | confb = snd_soc_read(codec, STA32X_CONFB); | ||
680 | confb &= ~(STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB); | ||
681 | switch (params_width(params)) { | 701 | switch (params_width(params)) { |
682 | case 24: | 702 | case 24: |
683 | pr_debug("24bit\n"); | 703 | dev_dbg(codec->dev, "24bit\n"); |
684 | /* fall through */ | 704 | /* fall through */ |
685 | case 32: | 705 | case 32: |
686 | pr_debug("24bit or 32bit\n"); | 706 | dev_dbg(codec->dev, "24bit or 32bit\n"); |
687 | switch (sta32x->format) { | 707 | switch (sta32x->format) { |
688 | case SND_SOC_DAIFMT_I2S: | 708 | case SND_SOC_DAIFMT_I2S: |
689 | confb |= 0x0; | 709 | confb |= 0x0; |
@@ -698,7 +718,7 @@ static int sta32x_hw_params(struct snd_pcm_substream *substream, | |||
698 | 718 | ||
699 | break; | 719 | break; |
700 | case 20: | 720 | case 20: |
701 | pr_debug("20bit\n"); | 721 | dev_dbg(codec->dev, "20bit\n"); |
702 | switch (sta32x->format) { | 722 | switch (sta32x->format) { |
703 | case SND_SOC_DAIFMT_I2S: | 723 | case SND_SOC_DAIFMT_I2S: |
704 | confb |= 0x4; | 724 | confb |= 0x4; |
@@ -713,7 +733,7 @@ static int sta32x_hw_params(struct snd_pcm_substream *substream, | |||
713 | 733 | ||
714 | break; | 734 | break; |
715 | case 18: | 735 | case 18: |
716 | pr_debug("18bit\n"); | 736 | dev_dbg(codec->dev, "18bit\n"); |
717 | switch (sta32x->format) { | 737 | switch (sta32x->format) { |
718 | case SND_SOC_DAIFMT_I2S: | 738 | case SND_SOC_DAIFMT_I2S: |
719 | confb |= 0x8; | 739 | confb |= 0x8; |
@@ -728,7 +748,7 @@ static int sta32x_hw_params(struct snd_pcm_substream *substream, | |||
728 | 748 | ||
729 | break; | 749 | break; |
730 | case 16: | 750 | case 16: |
731 | pr_debug("16bit\n"); | 751 | dev_dbg(codec->dev, "16bit\n"); |
732 | switch (sta32x->format) { | 752 | switch (sta32x->format) { |
733 | case SND_SOC_DAIFMT_I2S: | 753 | case SND_SOC_DAIFMT_I2S: |
734 | confb |= 0x0; | 754 | confb |= 0x0; |
@@ -746,8 +766,30 @@ static int sta32x_hw_params(struct snd_pcm_substream *substream, | |||
746 | return -EINVAL; | 766 | return -EINVAL; |
747 | } | 767 | } |
748 | 768 | ||
749 | snd_soc_write(codec, STA32X_CONFA, confa); | 769 | ret = regmap_update_bits(sta32x->regmap, STA32X_CONFA, |
750 | snd_soc_write(codec, STA32X_CONFB, confb); | 770 | STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK, |
771 | confa); | ||
772 | if (ret < 0) | ||
773 | return ret; | ||
774 | |||
775 | ret = regmap_update_bits(sta32x->regmap, STA32X_CONFB, | ||
776 | STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB, | ||
777 | confb); | ||
778 | if (ret < 0) | ||
779 | return ret; | ||
780 | |||
781 | return 0; | ||
782 | } | ||
783 | |||
784 | static int sta32x_startup_sequence(struct sta32x_priv *sta32x) | ||
785 | { | ||
786 | if (sta32x->gpiod_nreset) { | ||
787 | gpiod_set_value(sta32x->gpiod_nreset, 0); | ||
788 | mdelay(1); | ||
789 | gpiod_set_value(sta32x->gpiod_nreset, 1); | ||
790 | mdelay(1); | ||
791 | } | ||
792 | |||
751 | return 0; | 793 | return 0; |
752 | } | 794 | } |
753 | 795 | ||
@@ -766,14 +808,14 @@ static int sta32x_set_bias_level(struct snd_soc_codec *codec, | |||
766 | int ret; | 808 | int ret; |
767 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | 809 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); |
768 | 810 | ||
769 | pr_debug("level = %d\n", level); | 811 | dev_dbg(codec->dev, "level = %d\n", level); |
770 | switch (level) { | 812 | switch (level) { |
771 | case SND_SOC_BIAS_ON: | 813 | case SND_SOC_BIAS_ON: |
772 | break; | 814 | break; |
773 | 815 | ||
774 | case SND_SOC_BIAS_PREPARE: | 816 | case SND_SOC_BIAS_PREPARE: |
775 | /* Full power on */ | 817 | /* Full power on */ |
776 | snd_soc_update_bits(codec, STA32X_CONFF, | 818 | regmap_update_bits(sta32x->regmap, STA32X_CONFF, |
777 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, | 819 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, |
778 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD); | 820 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD); |
779 | break; | 821 | break; |
@@ -788,25 +830,28 @@ static int sta32x_set_bias_level(struct snd_soc_codec *codec, | |||
788 | return ret; | 830 | return ret; |
789 | } | 831 | } |
790 | 832 | ||
833 | sta32x_startup_sequence(sta32x); | ||
791 | sta32x_cache_sync(codec); | 834 | sta32x_cache_sync(codec); |
792 | sta32x_watchdog_start(sta32x); | 835 | sta32x_watchdog_start(sta32x); |
793 | } | 836 | } |
794 | 837 | ||
795 | /* Power up to mute */ | 838 | /* Power down */ |
796 | /* FIXME */ | 839 | regmap_update_bits(sta32x->regmap, STA32X_CONFF, |
797 | snd_soc_update_bits(codec, STA32X_CONFF, | 840 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, |
798 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, | 841 | 0); |
799 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD); | ||
800 | 842 | ||
801 | break; | 843 | break; |
802 | 844 | ||
803 | case SND_SOC_BIAS_OFF: | 845 | case SND_SOC_BIAS_OFF: |
804 | /* The chip runs through the power down sequence for us. */ | 846 | /* The chip runs through the power down sequence for us. */ |
805 | snd_soc_update_bits(codec, STA32X_CONFF, | 847 | regmap_update_bits(sta32x->regmap, STA32X_CONFF, |
806 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, | 848 | STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 0); |
807 | STA32X_CONFF_PWDN); | ||
808 | msleep(300); | 849 | msleep(300); |
809 | sta32x_watchdog_stop(sta32x); | 850 | sta32x_watchdog_stop(sta32x); |
851 | |||
852 | if (sta32x->gpiod_nreset) | ||
853 | gpiod_set_value(sta32x->gpiod_nreset, 0); | ||
854 | |||
810 | regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), | 855 | regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), |
811 | sta32x->supplies); | 856 | sta32x->supplies); |
812 | break; | 857 | break; |
@@ -822,7 +867,7 @@ static const struct snd_soc_dai_ops sta32x_dai_ops = { | |||
822 | }; | 867 | }; |
823 | 868 | ||
824 | static struct snd_soc_dai_driver sta32x_dai = { | 869 | static struct snd_soc_dai_driver sta32x_dai = { |
825 | .name = "STA32X", | 870 | .name = "sta32x-hifi", |
826 | .playback = { | 871 | .playback = { |
827 | .stream_name = "Playback", | 872 | .stream_name = "Playback", |
828 | .channels_min = 2, | 873 | .channels_min = 2, |
@@ -836,11 +881,8 @@ static struct snd_soc_dai_driver sta32x_dai = { | |||
836 | static int sta32x_probe(struct snd_soc_codec *codec) | 881 | static int sta32x_probe(struct snd_soc_codec *codec) |
837 | { | 882 | { |
838 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); | 883 | struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); |
884 | struct sta32x_platform_data *pdata = sta32x->pdata; | ||
839 | int i, ret = 0, thermal = 0; | 885 | int i, ret = 0, thermal = 0; |
840 | |||
841 | sta32x->codec = codec; | ||
842 | sta32x->pdata = dev_get_platdata(codec->dev); | ||
843 | |||
844 | ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies), | 886 | ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies), |
845 | sta32x->supplies); | 887 | sta32x->supplies); |
846 | if (ret != 0) { | 888 | if (ret != 0) { |
@@ -848,50 +890,73 @@ static int sta32x_probe(struct snd_soc_codec *codec) | |||
848 | return ret; | 890 | return ret; |
849 | } | 891 | } |
850 | 892 | ||
851 | /* Chip documentation explicitly requires that the reset values | 893 | ret = sta32x_startup_sequence(sta32x); |
852 | * of reserved register bits are left untouched. | 894 | if (ret < 0) { |
853 | * Write the register default value to cache for reserved registers, | 895 | dev_err(codec->dev, "Failed to startup device\n"); |
854 | * so the write to the these registers are suppressed by the cache | 896 | return ret; |
855 | * restore code when it skips writes of default registers. | 897 | } |
856 | */ | 898 | |
857 | regcache_cache_only(sta32x->regmap, true); | 899 | /* CONFA */ |
858 | snd_soc_write(codec, STA32X_CONFC, 0xc2); | 900 | if (!pdata->thermal_warning_recovery) |
859 | snd_soc_write(codec, STA32X_CONFE, 0xc2); | ||
860 | snd_soc_write(codec, STA32X_CONFF, 0x5c); | ||
861 | snd_soc_write(codec, STA32X_MMUTE, 0x10); | ||
862 | snd_soc_write(codec, STA32X_AUTO1, 0x60); | ||
863 | snd_soc_write(codec, STA32X_AUTO3, 0x00); | ||
864 | snd_soc_write(codec, STA32X_C3CFG, 0x40); | ||
865 | regcache_cache_only(sta32x->regmap, false); | ||
866 | |||
867 | /* set thermal warning adjustment and recovery */ | ||
868 | if (!(sta32x->pdata->thermal_conf & STA32X_THERMAL_ADJUSTMENT_ENABLE)) | ||
869 | thermal |= STA32X_CONFA_TWAB; | 901 | thermal |= STA32X_CONFA_TWAB; |
870 | if (!(sta32x->pdata->thermal_conf & STA32X_THERMAL_RECOVERY_ENABLE)) | 902 | if (!pdata->thermal_warning_adjustment) |
871 | thermal |= STA32X_CONFA_TWRB; | 903 | thermal |= STA32X_CONFA_TWRB; |
872 | snd_soc_update_bits(codec, STA32X_CONFA, | 904 | if (!pdata->fault_detect_recovery) |
873 | STA32X_CONFA_TWAB | STA32X_CONFA_TWRB, | 905 | thermal |= STA32X_CONFA_FDRB; |
874 | thermal); | 906 | regmap_update_bits(sta32x->regmap, STA32X_CONFA, |
907 | STA32X_CONFA_TWAB | STA32X_CONFA_TWRB | | ||
908 | STA32X_CONFA_FDRB, | ||
909 | thermal); | ||
910 | |||
911 | /* CONFC */ | ||
912 | regmap_update_bits(sta32x->regmap, STA32X_CONFC, | ||
913 | STA32X_CONFC_CSZ_MASK, | ||
914 | pdata->drop_compensation_ns | ||
915 | << STA32X_CONFC_CSZ_SHIFT); | ||
916 | |||
917 | /* CONFE */ | ||
918 | regmap_update_bits(sta32x->regmap, STA32X_CONFE, | ||
919 | STA32X_CONFE_MPCV, | ||
920 | pdata->max_power_use_mpcc ? | ||
921 | STA32X_CONFE_MPCV : 0); | ||
922 | regmap_update_bits(sta32x->regmap, STA32X_CONFE, | ||
923 | STA32X_CONFE_MPC, | ||
924 | pdata->max_power_correction ? | ||
925 | STA32X_CONFE_MPC : 0); | ||
926 | regmap_update_bits(sta32x->regmap, STA32X_CONFE, | ||
927 | STA32X_CONFE_AME, | ||
928 | pdata->am_reduction_mode ? | ||
929 | STA32X_CONFE_AME : 0); | ||
930 | regmap_update_bits(sta32x->regmap, STA32X_CONFE, | ||
931 | STA32X_CONFE_PWMS, | ||
932 | pdata->odd_pwm_speed_mode ? | ||
933 | STA32X_CONFE_PWMS : 0); | ||
934 | |||
935 | /* CONFF */ | ||
936 | regmap_update_bits(sta32x->regmap, STA32X_CONFF, | ||
937 | STA32X_CONFF_IDE, | ||
938 | pdata->invalid_input_detect_mute ? | ||
939 | STA32X_CONFF_IDE : 0); | ||
875 | 940 | ||
876 | /* select output configuration */ | 941 | /* select output configuration */ |
877 | snd_soc_update_bits(codec, STA32X_CONFF, | 942 | regmap_update_bits(sta32x->regmap, STA32X_CONFF, |
878 | STA32X_CONFF_OCFG_MASK, | 943 | STA32X_CONFF_OCFG_MASK, |
879 | sta32x->pdata->output_conf | 944 | pdata->output_conf |
880 | << STA32X_CONFF_OCFG_SHIFT); | 945 | << STA32X_CONFF_OCFG_SHIFT); |
881 | 946 | ||
882 | /* channel to output mapping */ | 947 | /* channel to output mapping */ |
883 | snd_soc_update_bits(codec, STA32X_C1CFG, | 948 | regmap_update_bits(sta32x->regmap, STA32X_C1CFG, |
884 | STA32X_CxCFG_OM_MASK, | 949 | STA32X_CxCFG_OM_MASK, |
885 | sta32x->pdata->ch1_output_mapping | 950 | pdata->ch1_output_mapping |
886 | << STA32X_CxCFG_OM_SHIFT); | 951 | << STA32X_CxCFG_OM_SHIFT); |
887 | snd_soc_update_bits(codec, STA32X_C2CFG, | 952 | regmap_update_bits(sta32x->regmap, STA32X_C2CFG, |
888 | STA32X_CxCFG_OM_MASK, | 953 | STA32X_CxCFG_OM_MASK, |
889 | sta32x->pdata->ch2_output_mapping | 954 | pdata->ch2_output_mapping |
890 | << STA32X_CxCFG_OM_SHIFT); | 955 | << STA32X_CxCFG_OM_SHIFT); |
891 | snd_soc_update_bits(codec, STA32X_C3CFG, | 956 | regmap_update_bits(sta32x->regmap, STA32X_C3CFG, |
892 | STA32X_CxCFG_OM_MASK, | 957 | STA32X_CxCFG_OM_MASK, |
893 | sta32x->pdata->ch3_output_mapping | 958 | pdata->ch3_output_mapping |
894 | << STA32X_CxCFG_OM_SHIFT); | 959 | << STA32X_CxCFG_OM_SHIFT); |
895 | 960 | ||
896 | /* initialize coefficient shadow RAM with reset values */ | 961 | /* initialize coefficient shadow RAM with reset values */ |
897 | for (i = 4; i <= 49; i += 5) | 962 | for (i = 4; i <= 49; i += 5) |
@@ -924,16 +989,6 @@ static int sta32x_remove(struct snd_soc_codec *codec) | |||
924 | return 0; | 989 | return 0; |
925 | } | 990 | } |
926 | 991 | ||
927 | static bool sta32x_reg_is_volatile(struct device *dev, unsigned int reg) | ||
928 | { | ||
929 | switch (reg) { | ||
930 | case STA32X_CONFA ... STA32X_L2ATRT: | ||
931 | case STA32X_MPCC1 ... STA32X_FDRC2: | ||
932 | return 0; | ||
933 | } | ||
934 | return 1; | ||
935 | } | ||
936 | |||
937 | static const struct snd_soc_codec_driver sta32x_codec = { | 992 | static const struct snd_soc_codec_driver sta32x_codec = { |
938 | .probe = sta32x_probe, | 993 | .probe = sta32x_probe, |
939 | .remove = sta32x_remove, | 994 | .remove = sta32x_remove, |
@@ -954,12 +1009,75 @@ static const struct regmap_config sta32x_regmap = { | |||
954 | .reg_defaults = sta32x_regs, | 1009 | .reg_defaults = sta32x_regs, |
955 | .num_reg_defaults = ARRAY_SIZE(sta32x_regs), | 1010 | .num_reg_defaults = ARRAY_SIZE(sta32x_regs), |
956 | .cache_type = REGCACHE_RBTREE, | 1011 | .cache_type = REGCACHE_RBTREE, |
957 | .volatile_reg = sta32x_reg_is_volatile, | 1012 | .wr_table = &sta32x_write_regs, |
1013 | .rd_table = &sta32x_read_regs, | ||
1014 | .volatile_table = &sta32x_volatile_regs, | ||
958 | }; | 1015 | }; |
959 | 1016 | ||
1017 | #ifdef CONFIG_OF | ||
1018 | static const struct of_device_id st32x_dt_ids[] = { | ||
1019 | { .compatible = "st,sta32x", }, | ||
1020 | { } | ||
1021 | }; | ||
1022 | MODULE_DEVICE_TABLE(of, st32x_dt_ids); | ||
1023 | |||
1024 | static int sta32x_probe_dt(struct device *dev, struct sta32x_priv *sta32x) | ||
1025 | { | ||
1026 | struct device_node *np = dev->of_node; | ||
1027 | struct sta32x_platform_data *pdata; | ||
1028 | u16 tmp; | ||
1029 | |||
1030 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | ||
1031 | if (!pdata) | ||
1032 | return -ENOMEM; | ||
1033 | |||
1034 | of_property_read_u8(np, "st,output-conf", | ||
1035 | &pdata->output_conf); | ||
1036 | of_property_read_u8(np, "st,ch1-output-mapping", | ||
1037 | &pdata->ch1_output_mapping); | ||
1038 | of_property_read_u8(np, "st,ch2-output-mapping", | ||
1039 | &pdata->ch2_output_mapping); | ||
1040 | of_property_read_u8(np, "st,ch3-output-mapping", | ||
1041 | &pdata->ch3_output_mapping); | ||
1042 | |||
1043 | if (of_get_property(np, "st,thermal-warning-recovery", NULL)) | ||
1044 | pdata->thermal_warning_recovery = 1; | ||
1045 | if (of_get_property(np, "st,thermal-warning-adjustment", NULL)) | ||
1046 | pdata->thermal_warning_adjustment = 1; | ||
1047 | if (of_get_property(np, "st,needs_esd_watchdog", NULL)) | ||
1048 | pdata->needs_esd_watchdog = 1; | ||
1049 | |||
1050 | tmp = 140; | ||
1051 | of_property_read_u16(np, "st,drop-compensation-ns", &tmp); | ||
1052 | pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20; | ||
1053 | |||
1054 | /* CONFE */ | ||
1055 | if (of_get_property(np, "st,max-power-use-mpcc", NULL)) | ||
1056 | pdata->max_power_use_mpcc = 1; | ||
1057 | |||
1058 | if (of_get_property(np, "st,max-power-correction", NULL)) | ||
1059 | pdata->max_power_correction = 1; | ||
1060 | |||
1061 | if (of_get_property(np, "st,am-reduction-mode", NULL)) | ||
1062 | pdata->am_reduction_mode = 1; | ||
1063 | |||
1064 | if (of_get_property(np, "st,odd-pwm-speed-mode", NULL)) | ||
1065 | pdata->odd_pwm_speed_mode = 1; | ||
1066 | |||
1067 | /* CONFF */ | ||
1068 | if (of_get_property(np, "st,invalid-input-detect-mute", NULL)) | ||
1069 | pdata->invalid_input_detect_mute = 1; | ||
1070 | |||
1071 | sta32x->pdata = pdata; | ||
1072 | |||
1073 | return 0; | ||
1074 | } | ||
1075 | #endif | ||
1076 | |||
960 | static int sta32x_i2c_probe(struct i2c_client *i2c, | 1077 | static int sta32x_i2c_probe(struct i2c_client *i2c, |
961 | const struct i2c_device_id *id) | 1078 | const struct i2c_device_id *id) |
962 | { | 1079 | { |
1080 | struct device *dev = &i2c->dev; | ||
963 | struct sta32x_priv *sta32x; | 1081 | struct sta32x_priv *sta32x; |
964 | int ret, i; | 1082 | int ret, i; |
965 | 1083 | ||
@@ -968,6 +1086,29 @@ static int sta32x_i2c_probe(struct i2c_client *i2c, | |||
968 | if (!sta32x) | 1086 | if (!sta32x) |
969 | return -ENOMEM; | 1087 | return -ENOMEM; |
970 | 1088 | ||
1089 | mutex_init(&sta32x->coeff_lock); | ||
1090 | sta32x->pdata = dev_get_platdata(dev); | ||
1091 | |||
1092 | #ifdef CONFIG_OF | ||
1093 | if (dev->of_node) { | ||
1094 | ret = sta32x_probe_dt(dev, sta32x); | ||
1095 | if (ret < 0) | ||
1096 | return ret; | ||
1097 | } | ||
1098 | #endif | ||
1099 | |||
1100 | /* GPIOs */ | ||
1101 | sta32x->gpiod_nreset = devm_gpiod_get(dev, "reset"); | ||
1102 | if (IS_ERR(sta32x->gpiod_nreset)) { | ||
1103 | ret = PTR_ERR(sta32x->gpiod_nreset); | ||
1104 | if (ret != -ENOENT && ret != -ENOSYS) | ||
1105 | return ret; | ||
1106 | |||
1107 | sta32x->gpiod_nreset = NULL; | ||
1108 | } else { | ||
1109 | gpiod_direction_output(sta32x->gpiod_nreset, 0); | ||
1110 | } | ||
1111 | |||
971 | /* regulators */ | 1112 | /* regulators */ |
972 | for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++) | 1113 | for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++) |
973 | sta32x->supplies[i].supply = sta32x_supply_names[i]; | 1114 | sta32x->supplies[i].supply = sta32x_supply_names[i]; |
@@ -982,15 +1123,15 @@ static int sta32x_i2c_probe(struct i2c_client *i2c, | |||
982 | sta32x->regmap = devm_regmap_init_i2c(i2c, &sta32x_regmap); | 1123 | sta32x->regmap = devm_regmap_init_i2c(i2c, &sta32x_regmap); |
983 | if (IS_ERR(sta32x->regmap)) { | 1124 | if (IS_ERR(sta32x->regmap)) { |
984 | ret = PTR_ERR(sta32x->regmap); | 1125 | ret = PTR_ERR(sta32x->regmap); |
985 | dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret); | 1126 | dev_err(dev, "Failed to init regmap: %d\n", ret); |
986 | return ret; | 1127 | return ret; |
987 | } | 1128 | } |
988 | 1129 | ||
989 | i2c_set_clientdata(i2c, sta32x); | 1130 | i2c_set_clientdata(i2c, sta32x); |
990 | 1131 | ||
991 | ret = snd_soc_register_codec(&i2c->dev, &sta32x_codec, &sta32x_dai, 1); | 1132 | ret = snd_soc_register_codec(dev, &sta32x_codec, &sta32x_dai, 1); |
992 | if (ret != 0) | 1133 | if (ret < 0) |
993 | dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret); | 1134 | dev_err(dev, "Failed to register codec (%d)\n", ret); |
994 | 1135 | ||
995 | return ret; | 1136 | return ret; |
996 | } | 1137 | } |
@@ -1013,6 +1154,7 @@ static struct i2c_driver sta32x_i2c_driver = { | |||
1013 | .driver = { | 1154 | .driver = { |
1014 | .name = "sta32x", | 1155 | .name = "sta32x", |
1015 | .owner = THIS_MODULE, | 1156 | .owner = THIS_MODULE, |
1157 | .of_match_table = of_match_ptr(st32x_dt_ids), | ||
1016 | }, | 1158 | }, |
1017 | .probe = sta32x_i2c_probe, | 1159 | .probe = sta32x_i2c_probe, |
1018 | .remove = sta32x_i2c_remove, | 1160 | .remove = sta32x_i2c_remove, |