aboutsummaryrefslogtreecommitdiffstats
path: root/sound/soc/codecs/sgtl5000.c
diff options
context:
space:
mode:
Diffstat (limited to 'sound/soc/codecs/sgtl5000.c')
-rw-r--r--sound/soc/codecs/sgtl5000.c21
1 files changed, 15 insertions, 6 deletions
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index fc9b127206e2..7f4ba819a9f6 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -832,7 +832,7 @@ static int ldo_regulator_register(struct snd_soc_codec *codec,
832 ldo->voltage = voltage; 832 ldo->voltage = voltage;
833 833
834 ldo->dev = regulator_register(&ldo->desc, codec->dev, 834 ldo->dev = regulator_register(&ldo->desc, codec->dev,
835 init_data, ldo); 835 init_data, ldo, NULL);
836 if (IS_ERR(ldo->dev)) { 836 if (IS_ERR(ldo->dev)) {
837 int ret = PTR_ERR(ldo->dev); 837 int ret = PTR_ERR(ldo->dev);
838 838
@@ -987,12 +987,12 @@ static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
987 /* restore regular registers */ 987 /* restore regular registers */
988 for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) { 988 for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
989 989
990 /* this regs depends on the others */ 990 /* These regs should restore in particular order */
991 if (reg == SGTL5000_CHIP_ANA_POWER || 991 if (reg == SGTL5000_CHIP_ANA_POWER ||
992 reg == SGTL5000_CHIP_CLK_CTRL || 992 reg == SGTL5000_CHIP_CLK_CTRL ||
993 reg == SGTL5000_CHIP_LINREG_CTRL || 993 reg == SGTL5000_CHIP_LINREG_CTRL ||
994 reg == SGTL5000_CHIP_LINE_OUT_CTRL || 994 reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
995 reg == SGTL5000_CHIP_CLK_CTRL) 995 reg == SGTL5000_CHIP_REF_CTRL)
996 continue; 996 continue;
997 997
998 snd_soc_write(codec, reg, cache[reg]); 998 snd_soc_write(codec, reg, cache[reg]);
@@ -1003,8 +1003,17 @@ static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
1003 snd_soc_write(codec, reg, cache[reg]); 1003 snd_soc_write(codec, reg, cache[reg]);
1004 1004
1005 /* 1005 /*
1006 * restore power and other regs according 1006 * restore these regs according to the power setting sequence in
1007 * to set_power() and set_clock() 1007 * sgtl5000_set_power_regs() and clock setting sequence in
1008 * sgtl5000_set_clock().
1009 *
1010 * The order of restore is:
1011 * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after
1012 * SGTL5000_CHIP_ANA_POWER PLL bits set
1013 * 2. SGTL5000_CHIP_LINREG_CTRL should be set before
1014 * SGTL5000_CHIP_ANA_POWER LINREG_D restored
1015 * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage,
1016 * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored
1008 */ 1017 */
1009 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, 1018 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
1010 cache[SGTL5000_CHIP_LINREG_CTRL]); 1019 cache[SGTL5000_CHIP_LINREG_CTRL]);
@@ -1457,5 +1466,5 @@ static void __exit sgtl5000_exit(void)
1457module_exit(sgtl5000_exit); 1466module_exit(sgtl5000_exit);
1458 1467
1459MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); 1468MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1460MODULE_AUTHOR("Zeng Zhaoming <zhaoming.zeng@freescale.com>"); 1469MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1461MODULE_LICENSE("GPL"); 1470MODULE_LICENSE("GPL");