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-rw-r--r--sound/pci/hda/hda_priv.h406
1 files changed, 0 insertions, 406 deletions
diff --git a/sound/pci/hda/hda_priv.h b/sound/pci/hda/hda_priv.h
deleted file mode 100644
index daf458299753..000000000000
--- a/sound/pci/hda/hda_priv.h
+++ /dev/null
@@ -1,406 +0,0 @@
1/*
2 * Common defines for the alsa driver code base for HD Audio.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef __SOUND_HDA_PRIV_H
16#define __SOUND_HDA_PRIV_H
17
18#include <linux/timecounter.h>
19#include <sound/core.h>
20#include <sound/pcm.h>
21
22/*
23 * registers
24 */
25#define AZX_REG_GCAP 0x00
26#define AZX_GCAP_64OK (1 << 0) /* 64bit address support */
27#define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */
28#define AZX_GCAP_BSS (31 << 3) /* # of bidirectional streams */
29#define AZX_GCAP_ISS (15 << 8) /* # of input streams */
30#define AZX_GCAP_OSS (15 << 12) /* # of output streams */
31#define AZX_REG_VMIN 0x02
32#define AZX_REG_VMAJ 0x03
33#define AZX_REG_OUTPAY 0x04
34#define AZX_REG_INPAY 0x06
35#define AZX_REG_GCTL 0x08
36#define AZX_GCTL_RESET (1 << 0) /* controller reset */
37#define AZX_GCTL_FCNTRL (1 << 1) /* flush control */
38#define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
39#define AZX_REG_WAKEEN 0x0c
40#define AZX_REG_STATESTS 0x0e
41#define AZX_REG_GSTS 0x10
42#define AZX_GSTS_FSTS (1 << 1) /* flush status */
43#define AZX_REG_INTCTL 0x20
44#define AZX_REG_INTSTS 0x24
45#define AZX_REG_WALLCLK 0x30 /* 24Mhz source */
46#define AZX_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
47#define AZX_REG_SSYNC 0x38
48#define AZX_REG_CORBLBASE 0x40
49#define AZX_REG_CORBUBASE 0x44
50#define AZX_REG_CORBWP 0x48
51#define AZX_REG_CORBRP 0x4a
52#define AZX_CORBRP_RST (1 << 15) /* read pointer reset */
53#define AZX_REG_CORBCTL 0x4c
54#define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */
55#define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
56#define AZX_REG_CORBSTS 0x4d
57#define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */
58#define AZX_REG_CORBSIZE 0x4e
59
60#define AZX_REG_RIRBLBASE 0x50
61#define AZX_REG_RIRBUBASE 0x54
62#define AZX_REG_RIRBWP 0x58
63#define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */
64#define AZX_REG_RINTCNT 0x5a
65#define AZX_REG_RIRBCTL 0x5c
66#define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
67#define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */
68#define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
69#define AZX_REG_RIRBSTS 0x5d
70#define AZX_RBSTS_IRQ (1 << 0) /* response irq */
71#define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */
72#define AZX_REG_RIRBSIZE 0x5e
73
74#define AZX_REG_IC 0x60
75#define AZX_REG_IR 0x64
76#define AZX_REG_IRS 0x68
77#define AZX_IRS_VALID (1<<1)
78#define AZX_IRS_BUSY (1<<0)
79
80#define AZX_REG_DPLBASE 0x70
81#define AZX_REG_DPUBASE 0x74
82#define AZX_DPLBASE_ENABLE 0x1 /* Enable position buffer */
83
84/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
85enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
86
87/* stream register offsets from stream base */
88#define AZX_REG_SD_CTL 0x00
89#define AZX_REG_SD_STS 0x03
90#define AZX_REG_SD_LPIB 0x04
91#define AZX_REG_SD_CBL 0x08
92#define AZX_REG_SD_LVI 0x0c
93#define AZX_REG_SD_FIFOW 0x0e
94#define AZX_REG_SD_FIFOSIZE 0x10
95#define AZX_REG_SD_FORMAT 0x12
96#define AZX_REG_SD_BDLPL 0x18
97#define AZX_REG_SD_BDLPU 0x1c
98
99/* PCI space */
100#define AZX_PCIREG_TCSEL 0x44
101
102/*
103 * other constants
104 */
105
106/* max number of fragments - we may use more if allocating more pages for BDL */
107#define BDL_SIZE 4096
108#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
109#define AZX_MAX_FRAG 32
110/* max buffer size - no h/w limit, you can increase as you like */
111#define AZX_MAX_BUF_SIZE (1024*1024*1024)
112
113/* RIRB int mask: overrun[2], response[0] */
114#define RIRB_INT_RESPONSE 0x01
115#define RIRB_INT_OVERRUN 0x04
116#define RIRB_INT_MASK 0x05
117
118/* STATESTS int mask: S3,SD2,SD1,SD0 */
119#define AZX_MAX_CODECS 8
120#define AZX_DEFAULT_CODECS 4
121#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
122
123/* SD_CTL bits */
124#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
125#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
126#define SD_CTL_STRIPE (3 << 16) /* stripe control */
127#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
128#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
129#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
130#define SD_CTL_STREAM_TAG_SHIFT 20
131
132/* SD_CTL and SD_STS */
133#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
134#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
135#define SD_INT_COMPLETE 0x04 /* completion interrupt */
136#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
137 SD_INT_COMPLETE)
138
139/* SD_STS */
140#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
141
142/* INTCTL and INTSTS */
143#define AZX_INT_ALL_STREAM 0xff /* all stream interrupts */
144#define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
145#define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
146
147/* below are so far hardcoded - should read registers in future */
148#define AZX_MAX_CORB_ENTRIES 256
149#define AZX_MAX_RIRB_ENTRIES 256
150
151/* driver quirks (capabilities) */
152/* bits 0-7 are used for indicating driver type */
153#define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
154#define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
155#define AZX_DCAPS_SNOOP_MASK (3 << 10) /* snoop type mask */
156#define AZX_DCAPS_SNOOP_OFF (1 << 12) /* snoop default off */
157#define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
158#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
159#define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
160#define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
161#define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
162#define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
163#define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
164#define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
165#define AZX_DCAPS_NO_ALIGN_BUFSIZE (1 << 21) /* no buffer size alignment */
166/* 22 unused */
167#define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
168#define AZX_DCAPS_REVERSE_ASSIGN (1 << 24) /* Assign devices in reverse order */
169#define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
170#define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
171#define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */
172#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */
173#define AZX_DCAPS_NO_MSI64 (1 << 29) /* Stick to 32-bit MSIs */
174#define AZX_DCAPS_SEPARATE_STREAM_TAG (1 << 30) /* capture and playback use separate stream tag */
175
176enum {
177 AZX_SNOOP_TYPE_NONE ,
178 AZX_SNOOP_TYPE_SCH,
179 AZX_SNOOP_TYPE_ATI,
180 AZX_SNOOP_TYPE_NVIDIA,
181};
182
183/* HD Audio class code */
184#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
185
186struct azx_dev {
187 struct snd_dma_buffer bdl; /* BDL buffer */
188 u32 *posbuf; /* position buffer pointer */
189
190 unsigned int bufsize; /* size of the play buffer in bytes */
191 unsigned int period_bytes; /* size of the period in bytes */
192 unsigned int frags; /* number for period in the play buffer */
193 unsigned int fifo_size; /* FIFO size */
194 unsigned long start_wallclk; /* start + minimum wallclk */
195 unsigned long period_wallclk; /* wallclk for period */
196
197 void __iomem *sd_addr; /* stream descriptor pointer */
198
199 u32 sd_int_sta_mask; /* stream int status mask */
200
201 /* pcm support */
202 struct snd_pcm_substream *substream; /* assigned substream,
203 * set in PCM open
204 */
205 unsigned int format_val; /* format value to be set in the
206 * controller and the codec
207 */
208 unsigned char stream_tag; /* assigned stream */
209 unsigned char index; /* stream index */
210 int assigned_key; /* last device# key assigned to */
211
212 unsigned int opened:1;
213 unsigned int running:1;
214 unsigned int irq_pending:1;
215 unsigned int prepared:1;
216 unsigned int locked:1;
217 /*
218 * For VIA:
219 * A flag to ensure DMA position is 0
220 * when link position is not greater than FIFO size
221 */
222 unsigned int insufficient:1;
223 unsigned int wc_marked:1;
224 unsigned int no_period_wakeup:1;
225
226 struct timecounter azx_tc;
227 struct cyclecounter azx_cc;
228
229 int delay_negative_threshold;
230
231#ifdef CONFIG_SND_HDA_DSP_LOADER
232 /* Allows dsp load to have sole access to the playback stream. */
233 struct mutex dsp_mutex;
234#endif
235};
236
237/* CORB/RIRB */
238struct azx_rb {
239 u32 *buf; /* CORB/RIRB buffer
240 * Each CORB entry is 4byte, RIRB is 8byte
241 */
242 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
243 /* for RIRB */
244 unsigned short rp, wp; /* read/write pointers */
245 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
246 u32 res[AZX_MAX_CODECS]; /* last read value */
247};
248
249struct azx;
250
251/* Functions to read/write to hda registers. */
252struct hda_controller_ops {
253 /* Register Access */
254 void (*reg_writel)(u32 value, u32 __iomem *addr);
255 u32 (*reg_readl)(u32 __iomem *addr);
256 void (*reg_writew)(u16 value, u16 __iomem *addr);
257 u16 (*reg_readw)(u16 __iomem *addr);
258 void (*reg_writeb)(u8 value, u8 __iomem *addr);
259 u8 (*reg_readb)(u8 __iomem *addr);
260 /* Disable msi if supported, PCI only */
261 int (*disable_msi_reset_irq)(struct azx *);
262 /* Allocation ops */
263 int (*dma_alloc_pages)(struct azx *chip,
264 int type,
265 size_t size,
266 struct snd_dma_buffer *buf);
267 void (*dma_free_pages)(struct azx *chip, struct snd_dma_buffer *buf);
268 int (*substream_alloc_pages)(struct azx *chip,
269 struct snd_pcm_substream *substream,
270 size_t size);
271 int (*substream_free_pages)(struct azx *chip,
272 struct snd_pcm_substream *substream);
273 void (*pcm_mmap_prepare)(struct snd_pcm_substream *substream,
274 struct vm_area_struct *area);
275 /* Check if current position is acceptable */
276 int (*position_check)(struct azx *chip, struct azx_dev *azx_dev);
277};
278
279struct azx_pcm {
280 struct azx *chip;
281 struct snd_pcm *pcm;
282 struct hda_codec *codec;
283 struct hda_pcm_stream *hinfo[2];
284 struct list_head list;
285};
286
287typedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *);
288typedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int pos);
289
290struct azx {
291 struct snd_card *card;
292 struct pci_dev *pci;
293 int dev_index;
294
295 /* chip type specific */
296 int driver_type;
297 unsigned int driver_caps;
298 int playback_streams;
299 int playback_index_offset;
300 int capture_streams;
301 int capture_index_offset;
302 int num_streams;
303 const int *jackpoll_ms; /* per-card jack poll interval */
304
305 /* Register interaction. */
306 const struct hda_controller_ops *ops;
307
308 /* position adjustment callbacks */
309 azx_get_pos_callback_t get_position[2];
310 azx_get_delay_callback_t get_delay[2];
311
312 /* pci resources */
313 unsigned long addr;
314 void __iomem *remap_addr;
315 int irq;
316
317 /* locks */
318 spinlock_t reg_lock;
319 struct mutex open_mutex; /* Prevents concurrent open/close operations */
320
321 /* streams (x num_streams) */
322 struct azx_dev *azx_dev;
323
324 /* PCM */
325 struct list_head pcm_list; /* azx_pcm list */
326
327 /* HD codec */
328 unsigned short codec_mask;
329 int codec_probe_mask; /* copied from probe_mask option */
330 struct hda_bus *bus;
331 unsigned int beep_mode;
332
333 /* CORB/RIRB */
334 struct azx_rb corb;
335 struct azx_rb rirb;
336
337 /* CORB/RIRB and position buffers */
338 struct snd_dma_buffer rb;
339 struct snd_dma_buffer posbuf;
340
341#ifdef CONFIG_SND_HDA_PATCH_LOADER
342 const struct firmware *fw;
343#endif
344
345 /* flags */
346 const int *bdl_pos_adj;
347 int poll_count;
348 unsigned int running:1;
349 unsigned int initialized:1;
350 unsigned int single_cmd:1;
351 unsigned int polling_mode:1;
352 unsigned int msi:1;
353 unsigned int probing:1; /* codec probing phase */
354 unsigned int snoop:1;
355 unsigned int align_buffer_size:1;
356 unsigned int region_requested:1;
357 unsigned int disabled:1; /* disabled by VGA-switcher */
358
359 /* for debugging */
360 unsigned int last_cmd[AZX_MAX_CODECS];
361
362 /* reboot notifier (for mysterious hangup problem at power-down) */
363 struct notifier_block reboot_notifier;
364
365#ifdef CONFIG_SND_HDA_DSP_LOADER
366 struct azx_dev saved_azx_dev;
367#endif
368};
369
370#ifdef CONFIG_X86
371#define azx_snoop(chip) ((chip)->snoop)
372#else
373#define azx_snoop(chip) true
374#endif
375
376/*
377 * macros for easy use
378 */
379
380#define azx_writel(chip, reg, value) \
381 ((chip)->ops->reg_writel(value, (chip)->remap_addr + AZX_REG_##reg))
382#define azx_readl(chip, reg) \
383 ((chip)->ops->reg_readl((chip)->remap_addr + AZX_REG_##reg))
384#define azx_writew(chip, reg, value) \
385 ((chip)->ops->reg_writew(value, (chip)->remap_addr + AZX_REG_##reg))
386#define azx_readw(chip, reg) \
387 ((chip)->ops->reg_readw((chip)->remap_addr + AZX_REG_##reg))
388#define azx_writeb(chip, reg, value) \
389 ((chip)->ops->reg_writeb(value, (chip)->remap_addr + AZX_REG_##reg))
390#define azx_readb(chip, reg) \
391 ((chip)->ops->reg_readb((chip)->remap_addr + AZX_REG_##reg))
392
393#define azx_sd_writel(chip, dev, reg, value) \
394 ((chip)->ops->reg_writel(value, (dev)->sd_addr + AZX_REG_##reg))
395#define azx_sd_readl(chip, dev, reg) \
396 ((chip)->ops->reg_readl((dev)->sd_addr + AZX_REG_##reg))
397#define azx_sd_writew(chip, dev, reg, value) \
398 ((chip)->ops->reg_writew(value, (dev)->sd_addr + AZX_REG_##reg))
399#define azx_sd_readw(chip, dev, reg) \
400 ((chip)->ops->reg_readw((dev)->sd_addr + AZX_REG_##reg))
401#define azx_sd_writeb(chip, dev, reg, value) \
402 ((chip)->ops->reg_writeb(value, (dev)->sd_addr + AZX_REG_##reg))
403#define azx_sd_readb(chip, dev, reg) \
404 ((chip)->ops->reg_readb((dev)->sd_addr + AZX_REG_##reg))
405
406#endif /* __SOUND_HDA_PRIV_H */
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