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diff --git a/sound/oss/au1000.c b/sound/oss/au1000.c
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1/*
2 * au1000.c -- Sound driver for Alchemy Au1000 MIPS Internet Edge
3 * Processor.
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * stevel@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 *
30 * Module command line parameters:
31 *
32 * Supported devices:
33 * /dev/dsp standard OSS /dev/dsp device
34 * /dev/mixer standard OSS /dev/mixer device
35 *
36 * Notes:
37 *
38 * 1. Much of the OSS buffer allocation, ioctl's, and mmap'ing are
39 * taken, slightly modified or not at all, from the ES1371 driver,
40 * so refer to the credits in es1371.c for those. The rest of the
41 * code (probe, open, read, write, the ISR, etc.) is new.
42 *
43 * Revision history
44 * 06.27.2001 Initial version
45 * 03.20.2002 Added mutex locks around read/write methods, to prevent
46 * simultaneous access on SMP or preemptible kernels. Also
47 * removed the counter/pointer fragment aligning at the end
48 * of read/write methods [stevel].
49 * 03.21.2002 Add support for coherent DMA on the audio read/write DMA
50 * channels [stevel].
51 *
52 */
53#include <linux/module.h>
54#include <linux/string.h>
55#include <linux/ioport.h>
56#include <linux/sched.h>
57#include <linux/delay.h>
58#include <linux/sound.h>
59#include <linux/slab.h>
60#include <linux/soundcard.h>
61#include <linux/init.h>
62#include <linux/page-flags.h>
63#include <linux/poll.h>
64#include <linux/pci.h>
65#include <linux/bitops.h>
66#include <linux/proc_fs.h>
67#include <linux/spinlock.h>
68#include <linux/smp_lock.h>
69#include <linux/ac97_codec.h>
70#include <linux/interrupt.h>
71#include <linux/mutex.h>
72
73#include <asm/io.h>
74#include <asm/uaccess.h>
75#include <asm/mach-au1x00/au1000.h>
76#include <asm/mach-au1x00/au1000_dma.h>
77
78/* --------------------------------------------------------------------- */
79
80#undef OSS_DOCUMENTED_MIXER_SEMANTICS
81#undef AU1000_DEBUG
82#undef AU1000_VERBOSE_DEBUG
83
84#define AU1000_MODULE_NAME "Au1000 audio"
85#define PFX AU1000_MODULE_NAME
86
87#ifdef AU1000_DEBUG
88#define dbg(format, arg...) printk(KERN_DEBUG PFX ": " format "\n" , ## arg)
89#else
90#define dbg(format, arg...) do {} while (0)
91#endif
92#define err(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
93#define info(format, arg...) printk(KERN_INFO PFX ": " format "\n" , ## arg)
94#define warn(format, arg...) printk(KERN_WARNING PFX ": " format "\n" , ## arg)
95
96
97/* misc stuff */
98#define POLL_COUNT 0x5000
99#define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
100
101/* Boot options */
102static int vra = 0; // 0 = no VRA, 1 = use VRA if codec supports it
103module_param(vra, bool, 0);
104MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
105
106
107/* --------------------------------------------------------------------- */
108
109struct au1000_state {
110 /* soundcore stuff */
111 int dev_audio;
112
113#ifdef AU1000_DEBUG
114 /* debug /proc entry */
115 struct proc_dir_entry *ps;
116 struct proc_dir_entry *ac97_ps;
117#endif /* AU1000_DEBUG */
118
119 struct ac97_codec codec;
120 unsigned codec_base_caps;// AC'97 reg 00h, "Reset Register"
121 unsigned codec_ext_caps; // AC'97 reg 28h, "Extended Audio ID"
122 int no_vra; // do not use VRA
123
124 spinlock_t lock;
125 struct mutex open_mutex;
126 struct mutex sem;
127 mode_t open_mode;
128 wait_queue_head_t open_wait;
129
130 struct dmabuf {
131 unsigned int dmanr; // DMA Channel number
132 unsigned sample_rate; // Hz
133 unsigned src_factor; // SRC interp/decimation (no vra)
134 unsigned sample_size; // 8 or 16
135 int num_channels; // 1 = mono, 2 = stereo, 4, 6
136 int dma_bytes_per_sample;// DMA bytes per audio sample frame
137 int user_bytes_per_sample;// User bytes per audio sample frame
138 int cnt_factor; // user-to-DMA bytes per audio
139 // sample frame
140 void *rawbuf;
141 dma_addr_t dmaaddr;
142 unsigned buforder;
143 unsigned numfrag; // # of DMA fragments in DMA buffer
144 unsigned fragshift;
145 void *nextIn; // ptr to next-in to DMA buffer
146 void *nextOut;// ptr to next-out from DMA buffer
147 int count; // current byte count in DMA buffer
148 unsigned total_bytes; // total bytes written or read
149 unsigned error; // over/underrun
150 wait_queue_head_t wait;
151 /* redundant, but makes calculations easier */
152 unsigned fragsize; // user perception of fragment size
153 unsigned dma_fragsize; // DMA (real) fragment size
154 unsigned dmasize; // Total DMA buffer size
155 // (mult. of DMA fragsize)
156 /* OSS stuff */
157 unsigned mapped:1;
158 unsigned ready:1;
159 unsigned stopped:1;
160 unsigned ossfragshift;
161 int ossmaxfrags;
162 unsigned subdivision;
163 } dma_dac , dma_adc;
164} au1000_state;
165
166/* --------------------------------------------------------------------- */
167
168
169static inline unsigned ld2(unsigned int x)
170{
171 unsigned r = 0;
172
173 if (x >= 0x10000) {
174 x >>= 16;
175 r += 16;
176 }
177 if (x >= 0x100) {
178 x >>= 8;
179 r += 8;
180 }
181 if (x >= 0x10) {
182 x >>= 4;
183 r += 4;
184 }
185 if (x >= 4) {
186 x >>= 2;
187 r += 2;
188 }
189 if (x >= 2)
190 r++;
191 return r;
192}
193
194/* --------------------------------------------------------------------- */
195
196static void au1000_delay(int msec)
197{
198 unsigned long tmo;
199 signed long tmo2;
200
201 if (in_interrupt())
202 return;
203
204 tmo = jiffies + (msec * HZ) / 1000;
205 for (;;) {
206 tmo2 = tmo - jiffies;
207 if (tmo2 <= 0)
208 break;
209 schedule_timeout(tmo2);
210 }
211}
212
213
214/* --------------------------------------------------------------------- */
215
216static u16 rdcodec(struct ac97_codec *codec, u8 addr)
217{
218 struct au1000_state *s = (struct au1000_state *)codec->private_data;
219 unsigned long flags;
220 u32 cmd;
221 u16 data;
222 int i;
223
224 spin_lock_irqsave(&s->lock, flags);
225
226 for (i = 0; i < POLL_COUNT; i++)
227 if (!(au_readl(AC97C_STATUS) & AC97C_CP))
228 break;
229 if (i == POLL_COUNT)
230 err("rdcodec: codec cmd pending expired!");
231
232 cmd = (u32) addr & AC97C_INDEX_MASK;
233 cmd |= AC97C_READ; // read command
234 au_writel(cmd, AC97C_CMD);
235
236 /* now wait for the data */
237 for (i = 0; i < POLL_COUNT; i++)
238 if (!(au_readl(AC97C_STATUS) & AC97C_CP))
239 break;
240 if (i == POLL_COUNT) {
241 err("rdcodec: read poll expired!");
242 return 0;
243 }
244
245 data = au_readl(AC97C_CMD) & 0xffff;
246
247 spin_unlock_irqrestore(&s->lock, flags);
248
249 return data;
250}
251
252
253static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
254{
255 struct au1000_state *s = (struct au1000_state *)codec->private_data;
256 unsigned long flags;
257 u32 cmd;
258 int i;
259
260 spin_lock_irqsave(&s->lock, flags);
261
262 for (i = 0; i < POLL_COUNT; i++)
263 if (!(au_readl(AC97C_STATUS) & AC97C_CP))
264 break;
265 if (i == POLL_COUNT)
266 err("wrcodec: codec cmd pending expired!");
267
268 cmd = (u32) addr & AC97C_INDEX_MASK;
269 cmd &= ~AC97C_READ; // write command
270 cmd |= ((u32) data << AC97C_WD_BIT); // OR in the data word
271 au_writel(cmd, AC97C_CMD);
272
273 spin_unlock_irqrestore(&s->lock, flags);
274}
275
276static void waitcodec(struct ac97_codec *codec)
277{
278 u16 temp;
279 int i;
280
281 /* codec_wait is used to wait for a ready state after
282 an AC97C_RESET. */
283 au1000_delay(10);
284
285 // first poll the CODEC_READY tag bit
286 for (i = 0; i < POLL_COUNT; i++)
287 if (au_readl(AC97C_STATUS) & AC97C_READY)
288 break;
289 if (i == POLL_COUNT) {
290 err("waitcodec: CODEC_READY poll expired!");
291 return;
292 }
293 // get AC'97 powerdown control/status register
294 temp = rdcodec(codec, AC97_POWER_CONTROL);
295
296 // If anything is powered down, power'em up
297 if (temp & 0x7f00) {
298 // Power on
299 wrcodec(codec, AC97_POWER_CONTROL, 0);
300 au1000_delay(100);
301 // Reread
302 temp = rdcodec(codec, AC97_POWER_CONTROL);
303 }
304
305 // Check if Codec REF,ANL,DAC,ADC ready
306 if ((temp & 0x7f0f) != 0x000f)
307 err("codec reg 26 status (0x%x) not ready!!", temp);
308}
309
310
311/* --------------------------------------------------------------------- */
312
313/* stop the ADC before calling */
314static void set_adc_rate(struct au1000_state *s, unsigned rate)
315{
316 struct dmabuf *adc = &s->dma_adc;
317 struct dmabuf *dac = &s->dma_dac;
318 unsigned adc_rate, dac_rate;
319 u16 ac97_extstat;
320
321 if (s->no_vra) {
322 // calc SRC factor
323 adc->src_factor = ((96000 / rate) + 1) >> 1;
324 adc->sample_rate = 48000 / adc->src_factor;
325 return;
326 }
327
328 adc->src_factor = 1;
329
330 ac97_extstat = rdcodec(&s->codec, AC97_EXTENDED_STATUS);
331
332 rate = rate > 48000 ? 48000 : rate;
333
334 // enable VRA
335 wrcodec(&s->codec, AC97_EXTENDED_STATUS,
336 ac97_extstat | AC97_EXTSTAT_VRA);
337 // now write the sample rate
338 wrcodec(&s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
339 // read it back for actual supported rate
340 adc_rate = rdcodec(&s->codec, AC97_PCM_LR_ADC_RATE);
341
342#ifdef AU1000_VERBOSE_DEBUG
343 dbg("%s: set to %d Hz", __FUNCTION__, adc_rate);
344#endif
345
346 // some codec's don't allow unequal DAC and ADC rates, in which case
347 // writing one rate reg actually changes both.
348 dac_rate = rdcodec(&s->codec, AC97_PCM_FRONT_DAC_RATE);
349 if (dac->num_channels > 2)
350 wrcodec(&s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
351 if (dac->num_channels > 4)
352 wrcodec(&s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
353
354 adc->sample_rate = adc_rate;
355 dac->sample_rate = dac_rate;
356}
357
358/* stop the DAC before calling */
359static void set_dac_rate(struct au1000_state *s, unsigned rate)
360{
361 struct dmabuf *dac = &s->dma_dac;
362 struct dmabuf *adc = &s->dma_adc;
363 unsigned adc_rate, dac_rate;
364 u16 ac97_extstat;
365
366 if (s->no_vra) {
367 // calc SRC factor
368 dac->src_factor = ((96000 / rate) + 1) >> 1;
369 dac->sample_rate = 48000 / dac->src_factor;
370 return;
371 }
372
373 dac->src_factor = 1;
374
375 ac97_extstat = rdcodec(&s->codec, AC97_EXTENDED_STATUS);
376
377 rate = rate > 48000 ? 48000 : rate;
378
379 // enable VRA
380 wrcodec(&s->codec, AC97_EXTENDED_STATUS,
381 ac97_extstat | AC97_EXTSTAT_VRA);
382 // now write the sample rate
383 wrcodec(&s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
384 // I don't support different sample rates for multichannel,
385 // so make these channels the same.
386 if (dac->num_channels > 2)
387 wrcodec(&s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
388 if (dac->num_channels > 4)
389 wrcodec(&s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
390 // read it back for actual supported rate
391 dac_rate = rdcodec(&s->codec, AC97_PCM_FRONT_DAC_RATE);
392
393#ifdef AU1000_VERBOSE_DEBUG
394 dbg("%s: set to %d Hz", __FUNCTION__, dac_rate);
395#endif
396
397 // some codec's don't allow unequal DAC and ADC rates, in which case
398 // writing one rate reg actually changes both.
399 adc_rate = rdcodec(&s->codec, AC97_PCM_LR_ADC_RATE);
400
401 dac->sample_rate = dac_rate;
402 adc->sample_rate = adc_rate;
403}
404
405static void stop_dac(struct au1000_state *s)
406{
407 struct dmabuf *db = &s->dma_dac;
408 unsigned long flags;
409
410 if (db->stopped)
411 return;
412
413 spin_lock_irqsave(&s->lock, flags);
414
415 disable_dma(db->dmanr);
416
417 db->stopped = 1;
418
419 spin_unlock_irqrestore(&s->lock, flags);
420}
421
422static void stop_adc(struct au1000_state *s)
423{
424 struct dmabuf *db = &s->dma_adc;
425 unsigned long flags;
426
427 if (db->stopped)
428 return;
429
430 spin_lock_irqsave(&s->lock, flags);
431
432 disable_dma(db->dmanr);
433
434 db->stopped = 1;
435
436 spin_unlock_irqrestore(&s->lock, flags);
437}
438
439
440static void set_xmit_slots(int num_channels)
441{
442 u32 ac97_config = au_readl(AC97C_CONFIG) & ~AC97C_XMIT_SLOTS_MASK;
443
444 switch (num_channels) {
445 case 1: // mono
446 case 2: // stereo, slots 3,4
447 ac97_config |= (0x3 << AC97C_XMIT_SLOTS_BIT);
448 break;
449 case 4: // stereo with surround, slots 3,4,7,8
450 ac97_config |= (0x33 << AC97C_XMIT_SLOTS_BIT);
451 break;
452 case 6: // stereo with surround and center/LFE, slots 3,4,6,7,8,9
453 ac97_config |= (0x7b << AC97C_XMIT_SLOTS_BIT);
454 break;
455 }
456
457 au_writel(ac97_config, AC97C_CONFIG);
458}
459
460static void set_recv_slots(int num_channels)
461{
462 u32 ac97_config = au_readl(AC97C_CONFIG) & ~AC97C_RECV_SLOTS_MASK;
463
464 /*
465 * Always enable slots 3 and 4 (stereo). Slot 6 is
466 * optional Mic ADC, which I don't support yet.
467 */
468 ac97_config |= (0x3 << AC97C_RECV_SLOTS_BIT);
469
470 au_writel(ac97_config, AC97C_CONFIG);
471}
472
473static void start_dac(struct au1000_state *s)
474{
475 struct dmabuf *db = &s->dma_dac;
476 unsigned long flags;
477 unsigned long buf1, buf2;
478
479 if (!db->stopped)
480 return;
481
482 spin_lock_irqsave(&s->lock, flags);
483
484 au_readl(AC97C_STATUS); // read status to clear sticky bits
485
486 // reset Buffer 1 and 2 pointers to nextOut and nextOut+dma_fragsize
487 buf1 = virt_to_phys(db->nextOut);
488 buf2 = buf1 + db->dma_fragsize;
489 if (buf2 >= db->dmaaddr + db->dmasize)
490 buf2 -= db->dmasize;
491
492 set_xmit_slots(db->num_channels);
493
494 init_dma(db->dmanr);
495 if (get_dma_active_buffer(db->dmanr) == 0) {
496 clear_dma_done0(db->dmanr); // clear DMA done bit
497 set_dma_addr0(db->dmanr, buf1);
498 set_dma_addr1(db->dmanr, buf2);
499 } else {
500 clear_dma_done1(db->dmanr); // clear DMA done bit
501 set_dma_addr1(db->dmanr, buf1);
502 set_dma_addr0(db->dmanr, buf2);
503 }
504 set_dma_count(db->dmanr, db->dma_fragsize>>1);
505 enable_dma_buffers(db->dmanr);
506
507 start_dma(db->dmanr);
508
509#ifdef AU1000_VERBOSE_DEBUG
510 dump_au1000_dma_channel(db->dmanr);
511#endif
512
513 db->stopped = 0;
514
515 spin_unlock_irqrestore(&s->lock, flags);
516}
517
518static void start_adc(struct au1000_state *s)
519{
520 struct dmabuf *db = &s->dma_adc;
521 unsigned long flags;
522 unsigned long buf1, buf2;
523
524 if (!db->stopped)
525 return;
526
527 spin_lock_irqsave(&s->lock, flags);
528
529 au_readl(AC97C_STATUS); // read status to clear sticky bits
530
531 // reset Buffer 1 and 2 pointers to nextIn and nextIn+dma_fragsize
532 buf1 = virt_to_phys(db->nextIn);
533 buf2 = buf1 + db->dma_fragsize;
534 if (buf2 >= db->dmaaddr + db->dmasize)
535 buf2 -= db->dmasize;
536
537 set_recv_slots(db->num_channels);
538
539 init_dma(db->dmanr);
540 if (get_dma_active_buffer(db->dmanr) == 0) {
541 clear_dma_done0(db->dmanr); // clear DMA done bit
542 set_dma_addr0(db->dmanr, buf1);
543 set_dma_addr1(db->dmanr, buf2);
544 } else {
545 clear_dma_done1(db->dmanr); // clear DMA done bit
546 set_dma_addr1(db->dmanr, buf1);
547 set_dma_addr0(db->dmanr, buf2);
548 }
549 set_dma_count(db->dmanr, db->dma_fragsize>>1);
550 enable_dma_buffers(db->dmanr);
551
552 start_dma(db->dmanr);
553
554#ifdef AU1000_VERBOSE_DEBUG
555 dump_au1000_dma_channel(db->dmanr);
556#endif
557
558 db->stopped = 0;
559
560 spin_unlock_irqrestore(&s->lock, flags);
561}
562
563/* --------------------------------------------------------------------- */
564
565#define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
566#define DMABUF_MINORDER 1
567
568static inline void dealloc_dmabuf(struct au1000_state *s, struct dmabuf *db)
569{
570 struct page *page, *pend;
571
572 if (db->rawbuf) {
573 /* undo marking the pages as reserved */
574 pend = virt_to_page(db->rawbuf +
575 (PAGE_SIZE << db->buforder) - 1);
576 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
577 ClearPageReserved(page);
578 dma_free_noncoherent(NULL,
579 PAGE_SIZE << db->buforder,
580 db->rawbuf,
581 db->dmaaddr);
582 }
583 db->rawbuf = db->nextIn = db->nextOut = NULL;
584 db->mapped = db->ready = 0;
585}
586
587static int prog_dmabuf(struct au1000_state *s, struct dmabuf *db)
588{
589 int order;
590 unsigned user_bytes_per_sec;
591 unsigned bufs;
592 struct page *page, *pend;
593 unsigned rate = db->sample_rate;
594
595 if (!db->rawbuf) {
596 db->ready = db->mapped = 0;
597 for (order = DMABUF_DEFAULTORDER;
598 order >= DMABUF_MINORDER; order--)
599 if ((db->rawbuf = dma_alloc_noncoherent(NULL,
600 PAGE_SIZE << order,
601 &db->dmaaddr,
602 0)))
603 break;
604 if (!db->rawbuf)
605 return -ENOMEM;
606 db->buforder = order;
607 /* now mark the pages as reserved;
608 otherwise remap_pfn_range doesn't do what we want */
609 pend = virt_to_page(db->rawbuf +
610 (PAGE_SIZE << db->buforder) - 1);
611 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
612 SetPageReserved(page);
613 }
614
615 db->cnt_factor = 1;
616 if (db->sample_size == 8)
617 db->cnt_factor *= 2;
618 if (db->num_channels == 1)
619 db->cnt_factor *= 2;
620 db->cnt_factor *= db->src_factor;
621
622 db->count = 0;
623 db->nextIn = db->nextOut = db->rawbuf;
624
625 db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
626 db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
627 2 : db->num_channels);
628
629 user_bytes_per_sec = rate * db->user_bytes_per_sample;
630 bufs = PAGE_SIZE << db->buforder;
631 if (db->ossfragshift) {
632 if ((1000 << db->ossfragshift) < user_bytes_per_sec)
633 db->fragshift = ld2(user_bytes_per_sec/1000);
634 else
635 db->fragshift = db->ossfragshift;
636 } else {
637 db->fragshift = ld2(user_bytes_per_sec / 100 /
638 (db->subdivision ? db->subdivision : 1));
639 if (db->fragshift < 3)
640 db->fragshift = 3;
641 }
642
643 db->fragsize = 1 << db->fragshift;
644 db->dma_fragsize = db->fragsize * db->cnt_factor;
645 db->numfrag = bufs / db->dma_fragsize;
646
647 while (db->numfrag < 4 && db->fragshift > 3) {
648 db->fragshift--;
649 db->fragsize = 1 << db->fragshift;
650 db->dma_fragsize = db->fragsize * db->cnt_factor;
651 db->numfrag = bufs / db->dma_fragsize;
652 }
653
654 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
655 db->numfrag = db->ossmaxfrags;
656
657 db->dmasize = db->dma_fragsize * db->numfrag;
658 memset(db->rawbuf, 0, bufs);
659
660#ifdef AU1000_VERBOSE_DEBUG
661 dbg("rate=%d, samplesize=%d, channels=%d",
662 rate, db->sample_size, db->num_channels);
663 dbg("fragsize=%d, cnt_factor=%d, dma_fragsize=%d",
664 db->fragsize, db->cnt_factor, db->dma_fragsize);
665 dbg("numfrag=%d, dmasize=%d", db->numfrag, db->dmasize);
666#endif
667
668 db->ready = 1;
669 return 0;
670}
671
672static inline int prog_dmabuf_adc(struct au1000_state *s)
673{
674 stop_adc(s);
675 return prog_dmabuf(s, &s->dma_adc);
676
677}
678
679static inline int prog_dmabuf_dac(struct au1000_state *s)
680{
681 stop_dac(s);
682 return prog_dmabuf(s, &s->dma_dac);
683}
684
685
686/* hold spinlock for the following */
687static irqreturn_t dac_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
688{
689 struct au1000_state *s = (struct au1000_state *) dev_id;
690 struct dmabuf *dac = &s->dma_dac;
691 unsigned long newptr;
692 u32 ac97c_stat, buff_done;
693
694 ac97c_stat = au_readl(AC97C_STATUS);
695#ifdef AU1000_VERBOSE_DEBUG
696 if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
697 dbg("AC97C status = 0x%08x", ac97c_stat);
698#endif
699
700 if ((buff_done = get_dma_buffer_done(dac->dmanr)) == 0) {
701 /* fastpath out, to ease interrupt sharing */
702 return IRQ_HANDLED;
703 }
704
705 spin_lock(&s->lock);
706
707 if (buff_done != (DMA_D0 | DMA_D1)) {
708 dac->nextOut += dac->dma_fragsize;
709 if (dac->nextOut >= dac->rawbuf + dac->dmasize)
710 dac->nextOut -= dac->dmasize;
711
712 /* update playback pointers */
713 newptr = virt_to_phys(dac->nextOut) + dac->dma_fragsize;
714 if (newptr >= dac->dmaaddr + dac->dmasize)
715 newptr -= dac->dmasize;
716
717 dac->count -= dac->dma_fragsize;
718 dac->total_bytes += dac->dma_fragsize;
719
720 if (dac->count <= 0) {
721#ifdef AU1000_VERBOSE_DEBUG
722 dbg("dac underrun");
723#endif
724 spin_unlock(&s->lock);
725 stop_dac(s);
726 spin_lock(&s->lock);
727 dac->count = 0;
728 dac->nextIn = dac->nextOut;
729 } else if (buff_done == DMA_D0) {
730 clear_dma_done0(dac->dmanr); // clear DMA done bit
731 set_dma_count0(dac->dmanr, dac->dma_fragsize>>1);
732 set_dma_addr0(dac->dmanr, newptr);
733 enable_dma_buffer0(dac->dmanr); // reenable
734 } else {
735 clear_dma_done1(dac->dmanr); // clear DMA done bit
736 set_dma_count1(dac->dmanr, dac->dma_fragsize>>1);
737 set_dma_addr1(dac->dmanr, newptr);
738 enable_dma_buffer1(dac->dmanr); // reenable
739 }
740 } else {
741 // both done bits set, we missed an interrupt
742 spin_unlock(&s->lock);
743 stop_dac(s);
744 spin_lock(&s->lock);
745
746 dac->nextOut += 2*dac->dma_fragsize;
747 if (dac->nextOut >= dac->rawbuf + dac->dmasize)
748 dac->nextOut -= dac->dmasize;
749
750 dac->count -= 2*dac->dma_fragsize;
751 dac->total_bytes += 2*dac->dma_fragsize;
752
753 if (dac->count > 0) {
754 spin_unlock(&s->lock);
755 start_dac(s);
756 spin_lock(&s->lock);
757 }
758 }
759
760 /* wake up anybody listening */
761 if (waitqueue_active(&dac->wait))
762 wake_up(&dac->wait);
763
764 spin_unlock(&s->lock);
765
766 return IRQ_HANDLED;
767}
768
769
770static irqreturn_t adc_dma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
771{
772 struct au1000_state *s = (struct au1000_state *) dev_id;
773 struct dmabuf *adc = &s->dma_adc;
774 unsigned long newptr;
775 u32 ac97c_stat, buff_done;
776
777 ac97c_stat = au_readl(AC97C_STATUS);
778#ifdef AU1000_VERBOSE_DEBUG
779 if (ac97c_stat & (AC97C_RU | AC97C_RO))
780 dbg("AC97C status = 0x%08x", ac97c_stat);
781#endif
782
783 if ((buff_done = get_dma_buffer_done(adc->dmanr)) == 0) {
784 /* fastpath out, to ease interrupt sharing */
785 return IRQ_HANDLED;
786 }
787
788 spin_lock(&s->lock);
789
790 if (buff_done != (DMA_D0 | DMA_D1)) {
791 if (adc->count + adc->dma_fragsize > adc->dmasize) {
792 // Overrun. Stop ADC and log the error
793 spin_unlock(&s->lock);
794 stop_adc(s);
795 adc->error++;
796 err("adc overrun");
797 return IRQ_NONE;
798 }
799
800 adc->nextIn += adc->dma_fragsize;
801 if (adc->nextIn >= adc->rawbuf + adc->dmasize)
802 adc->nextIn -= adc->dmasize;
803
804 /* update capture pointers */
805 newptr = virt_to_phys(adc->nextIn) + adc->dma_fragsize;
806 if (newptr >= adc->dmaaddr + adc->dmasize)
807 newptr -= adc->dmasize;
808
809 adc->count += adc->dma_fragsize;
810 adc->total_bytes += adc->dma_fragsize;
811
812 if (buff_done == DMA_D0) {
813 clear_dma_done0(adc->dmanr); // clear DMA done bit
814 set_dma_count0(adc->dmanr, adc->dma_fragsize>>1);
815 set_dma_addr0(adc->dmanr, newptr);
816 enable_dma_buffer0(adc->dmanr); // reenable
817 } else {
818 clear_dma_done1(adc->dmanr); // clear DMA done bit
819 set_dma_count1(adc->dmanr, adc->dma_fragsize>>1);
820 set_dma_addr1(adc->dmanr, newptr);
821 enable_dma_buffer1(adc->dmanr); // reenable
822 }
823 } else {
824 // both done bits set, we missed an interrupt
825 spin_unlock(&s->lock);
826 stop_adc(s);
827 spin_lock(&s->lock);
828
829 if (adc->count + 2*adc->dma_fragsize > adc->dmasize) {
830 // Overrun. Log the error
831 adc->error++;
832 err("adc overrun");
833 spin_unlock(&s->lock);
834 return IRQ_NONE;
835 }
836
837 adc->nextIn += 2*adc->dma_fragsize;
838 if (adc->nextIn >= adc->rawbuf + adc->dmasize)
839 adc->nextIn -= adc->dmasize;
840
841 adc->count += 2*adc->dma_fragsize;
842 adc->total_bytes += 2*adc->dma_fragsize;
843
844 spin_unlock(&s->lock);
845 start_adc(s);
846 spin_lock(&s->lock);
847 }
848
849 /* wake up anybody listening */
850 if (waitqueue_active(&adc->wait))
851 wake_up(&adc->wait);
852
853 spin_unlock(&s->lock);
854
855 return IRQ_HANDLED;
856}
857
858/* --------------------------------------------------------------------- */
859
860static loff_t au1000_llseek(struct file *file, loff_t offset, int origin)
861{
862 return -ESPIPE;
863}
864
865
866static int au1000_open_mixdev(struct inode *inode, struct file *file)
867{
868 file->private_data = &au1000_state;
869 return nonseekable_open(inode, file);
870}
871
872static int au1000_release_mixdev(struct inode *inode, struct file *file)
873{
874 return 0;
875}
876
877static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
878 unsigned long arg)
879{
880 return codec->mixer_ioctl(codec, cmd, arg);
881}
882
883static int au1000_ioctl_mixdev(struct inode *inode, struct file *file,
884 unsigned int cmd, unsigned long arg)
885{
886 struct au1000_state *s = (struct au1000_state *)file->private_data;
887 struct ac97_codec *codec = &s->codec;
888
889 return mixdev_ioctl(codec, cmd, arg);
890}
891
892static /*const */ struct file_operations au1000_mixer_fops = {
893 .owner = THIS_MODULE,
894 .llseek = au1000_llseek,
895 .ioctl = au1000_ioctl_mixdev,
896 .open = au1000_open_mixdev,
897 .release = au1000_release_mixdev,
898};
899
900/* --------------------------------------------------------------------- */
901
902static int drain_dac(struct au1000_state *s, int nonblock)
903{
904 unsigned long flags;
905 int count, tmo;
906
907 if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
908 return 0;
909
910 for (;;) {
911 spin_lock_irqsave(&s->lock, flags);
912 count = s->dma_dac.count;
913 spin_unlock_irqrestore(&s->lock, flags);
914 if (count <= 0)
915 break;
916 if (signal_pending(current))
917 break;
918 if (nonblock)
919 return -EBUSY;
920 tmo = 1000 * count / (s->no_vra ?
921 48000 : s->dma_dac.sample_rate);
922 tmo /= s->dma_dac.dma_bytes_per_sample;
923 au1000_delay(tmo);
924 }
925 if (signal_pending(current))
926 return -ERESTARTSYS;
927 return 0;
928}
929
930/* --------------------------------------------------------------------- */
931
932static inline u8 S16_TO_U8(s16 ch)
933{
934 return (u8) (ch >> 8) + 0x80;
935}
936static inline s16 U8_TO_S16(u8 ch)
937{
938 return (s16) (ch - 0x80) << 8;
939}
940
941/*
942 * Translates user samples to dma buffer suitable for AC'97 DAC data:
943 * If mono, copy left channel to right channel in dma buffer.
944 * If 8 bit samples, cvt to 16-bit before writing to dma buffer.
945 * If interpolating (no VRA), duplicate every audio frame src_factor times.
946 */
947static int translate_from_user(struct dmabuf *db,
948 char* dmabuf,
949 char* userbuf,
950 int dmacount)
951{
952 int sample, i;
953 int interp_bytes_per_sample;
954 int num_samples;
955 int mono = (db->num_channels == 1);
956 char usersample[12];
957 s16 ch, dmasample[6];
958
959 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
960 // no translation necessary, just copy
961 if (copy_from_user(dmabuf, userbuf, dmacount))
962 return -EFAULT;
963 return dmacount;
964 }
965
966 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
967 num_samples = dmacount / interp_bytes_per_sample;
968
969 for (sample = 0; sample < num_samples; sample++) {
970 if (copy_from_user(usersample, userbuf,
971 db->user_bytes_per_sample)) {
972 dbg("%s: fault", __FUNCTION__);
973 return -EFAULT;
974 }
975
976 for (i = 0; i < db->num_channels; i++) {
977 if (db->sample_size == 8)
978 ch = U8_TO_S16(usersample[i]);
979 else
980 ch = *((s16 *) (&usersample[i * 2]));
981 dmasample[i] = ch;
982 if (mono)
983 dmasample[i + 1] = ch; // right channel
984 }
985
986 // duplicate every audio frame src_factor times
987 for (i = 0; i < db->src_factor; i++)
988 memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
989
990 userbuf += db->user_bytes_per_sample;
991 dmabuf += interp_bytes_per_sample;
992 }
993
994 return num_samples * interp_bytes_per_sample;
995}
996
997/*
998 * Translates AC'97 ADC samples to user buffer:
999 * If mono, send only left channel to user buffer.
1000 * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
1001 * If decimating (no VRA), skip over src_factor audio frames.
1002 */
1003static int translate_to_user(struct dmabuf *db,
1004 char* userbuf,
1005 char* dmabuf,
1006 int dmacount)
1007{
1008 int sample, i;
1009 int interp_bytes_per_sample;
1010 int num_samples;
1011 int mono = (db->num_channels == 1);
1012 char usersample[12];
1013
1014 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
1015 // no translation necessary, just copy
1016 if (copy_to_user(userbuf, dmabuf, dmacount))
1017 return -EFAULT;
1018 return dmacount;
1019 }
1020
1021 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
1022 num_samples = dmacount / interp_bytes_per_sample;
1023
1024 for (sample = 0; sample < num_samples; sample++) {
1025 for (i = 0; i < db->num_channels; i++) {
1026 if (db->sample_size == 8)
1027 usersample[i] =
1028 S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
1029 else
1030 *((s16 *) (&usersample[i * 2])) =
1031 *((s16 *) (&dmabuf[i * 2]));
1032 }
1033
1034 if (copy_to_user(userbuf, usersample,
1035 db->user_bytes_per_sample)) {
1036 dbg("%s: fault", __FUNCTION__);
1037 return -EFAULT;
1038 }
1039
1040 userbuf += db->user_bytes_per_sample;
1041 dmabuf += interp_bytes_per_sample;
1042 }
1043
1044 return num_samples * interp_bytes_per_sample;
1045}
1046
1047/*
1048 * Copy audio data to/from user buffer from/to dma buffer, taking care
1049 * that we wrap when reading/writing the dma buffer. Returns actual byte
1050 * count written to or read from the dma buffer.
1051 */
1052static int copy_dmabuf_user(struct dmabuf *db, char* userbuf,
1053 int count, int to_user)
1054{
1055 char *bufptr = to_user ? db->nextOut : db->nextIn;
1056 char *bufend = db->rawbuf + db->dmasize;
1057 int cnt, ret;
1058
1059 if (bufptr + count > bufend) {
1060 int partial = (int) (bufend - bufptr);
1061 if (to_user) {
1062 if ((cnt = translate_to_user(db, userbuf,
1063 bufptr, partial)) < 0)
1064 return cnt;
1065 ret = cnt;
1066 if ((cnt = translate_to_user(db, userbuf + partial,
1067 db->rawbuf,
1068 count - partial)) < 0)
1069 return cnt;
1070 ret += cnt;
1071 } else {
1072 if ((cnt = translate_from_user(db, bufptr, userbuf,
1073 partial)) < 0)
1074 return cnt;
1075 ret = cnt;
1076 if ((cnt = translate_from_user(db, db->rawbuf,
1077 userbuf + partial,
1078 count - partial)) < 0)
1079 return cnt;
1080 ret += cnt;
1081 }
1082 } else {
1083 if (to_user)
1084 ret = translate_to_user(db, userbuf, bufptr, count);
1085 else
1086 ret = translate_from_user(db, bufptr, userbuf, count);
1087 }
1088
1089 return ret;
1090}
1091
1092
1093static ssize_t au1000_read(struct file *file, char *buffer,
1094 size_t count, loff_t *ppos)
1095{
1096 struct au1000_state *s = (struct au1000_state *)file->private_data;
1097 struct dmabuf *db = &s->dma_adc;
1098 DECLARE_WAITQUEUE(wait, current);
1099 ssize_t ret;
1100 unsigned long flags;
1101 int cnt, usercnt, avail;
1102
1103 if (db->mapped)
1104 return -ENXIO;
1105 if (!access_ok(VERIFY_WRITE, buffer, count))
1106 return -EFAULT;
1107 ret = 0;
1108
1109 count *= db->cnt_factor;
1110
1111 mutex_lock(&s->sem);
1112 add_wait_queue(&db->wait, &wait);
1113
1114 while (count > 0) {
1115 // wait for samples in ADC dma buffer
1116 do {
1117 if (db->stopped)
1118 start_adc(s);
1119 spin_lock_irqsave(&s->lock, flags);
1120 avail = db->count;
1121 if (avail <= 0)
1122 __set_current_state(TASK_INTERRUPTIBLE);
1123 spin_unlock_irqrestore(&s->lock, flags);
1124 if (avail <= 0) {
1125 if (file->f_flags & O_NONBLOCK) {
1126 if (!ret)
1127 ret = -EAGAIN;
1128 goto out;
1129 }
1130 mutex_unlock(&s->sem);
1131 schedule();
1132 if (signal_pending(current)) {
1133 if (!ret)
1134 ret = -ERESTARTSYS;
1135 goto out2;
1136 }
1137 mutex_lock(&s->sem);
1138 }
1139 } while (avail <= 0);
1140
1141 // copy from nextOut to user
1142 if ((cnt = copy_dmabuf_user(db, buffer,
1143 count > avail ?
1144 avail : count, 1)) < 0) {
1145 if (!ret)
1146 ret = -EFAULT;
1147 goto out;
1148 }
1149
1150 spin_lock_irqsave(&s->lock, flags);
1151 db->count -= cnt;
1152 db->nextOut += cnt;
1153 if (db->nextOut >= db->rawbuf + db->dmasize)
1154 db->nextOut -= db->dmasize;
1155 spin_unlock_irqrestore(&s->lock, flags);
1156
1157 count -= cnt;
1158 usercnt = cnt / db->cnt_factor;
1159 buffer += usercnt;
1160 ret += usercnt;
1161 } // while (count > 0)
1162
1163out:
1164 mutex_unlock(&s->sem);
1165out2:
1166 remove_wait_queue(&db->wait, &wait);
1167 set_current_state(TASK_RUNNING);
1168 return ret;
1169}
1170
1171static ssize_t au1000_write(struct file *file, const char *buffer,
1172 size_t count, loff_t * ppos)
1173{
1174 struct au1000_state *s = (struct au1000_state *)file->private_data;
1175 struct dmabuf *db = &s->dma_dac;
1176 DECLARE_WAITQUEUE(wait, current);
1177 ssize_t ret = 0;
1178 unsigned long flags;
1179 int cnt, usercnt, avail;
1180
1181#ifdef AU1000_VERBOSE_DEBUG
1182 dbg("write: count=%d", count);
1183#endif
1184
1185 if (db->mapped)
1186 return -ENXIO;
1187 if (!access_ok(VERIFY_READ, buffer, count))
1188 return -EFAULT;
1189
1190 count *= db->cnt_factor;
1191
1192 mutex_lock(&s->sem);
1193 add_wait_queue(&db->wait, &wait);
1194
1195 while (count > 0) {
1196 // wait for space in playback buffer
1197 do {
1198 spin_lock_irqsave(&s->lock, flags);
1199 avail = (int) db->dmasize - db->count;
1200 if (avail <= 0)
1201 __set_current_state(TASK_INTERRUPTIBLE);
1202 spin_unlock_irqrestore(&s->lock, flags);
1203 if (avail <= 0) {
1204 if (file->f_flags & O_NONBLOCK) {
1205 if (!ret)
1206 ret = -EAGAIN;
1207 goto out;
1208 }
1209 mutex_unlock(&s->sem);
1210 schedule();
1211 if (signal_pending(current)) {
1212 if (!ret)
1213 ret = -ERESTARTSYS;
1214 goto out2;
1215 }
1216 mutex_lock(&s->sem);
1217 }
1218 } while (avail <= 0);
1219
1220 // copy from user to nextIn
1221 if ((cnt = copy_dmabuf_user(db, (char *) buffer,
1222 count > avail ?
1223 avail : count, 0)) < 0) {
1224 if (!ret)
1225 ret = -EFAULT;
1226 goto out;
1227 }
1228
1229 spin_lock_irqsave(&s->lock, flags);
1230 db->count += cnt;
1231 db->nextIn += cnt;
1232 if (db->nextIn >= db->rawbuf + db->dmasize)
1233 db->nextIn -= db->dmasize;
1234 spin_unlock_irqrestore(&s->lock, flags);
1235 if (db->stopped)
1236 start_dac(s);
1237
1238 count -= cnt;
1239 usercnt = cnt / db->cnt_factor;
1240 buffer += usercnt;
1241 ret += usercnt;
1242 } // while (count > 0)
1243
1244out:
1245 mutex_unlock(&s->sem);
1246out2:
1247 remove_wait_queue(&db->wait, &wait);
1248 set_current_state(TASK_RUNNING);
1249 return ret;
1250}
1251
1252
1253/* No kernel lock - we have our own spinlock */
1254static unsigned int au1000_poll(struct file *file,
1255 struct poll_table_struct *wait)
1256{
1257 struct au1000_state *s = (struct au1000_state *)file->private_data;
1258 unsigned long flags;
1259 unsigned int mask = 0;
1260
1261 if (file->f_mode & FMODE_WRITE) {
1262 if (!s->dma_dac.ready)
1263 return 0;
1264 poll_wait(file, &s->dma_dac.wait, wait);
1265 }
1266 if (file->f_mode & FMODE_READ) {
1267 if (!s->dma_adc.ready)
1268 return 0;
1269 poll_wait(file, &s->dma_adc.wait, wait);
1270 }
1271
1272 spin_lock_irqsave(&s->lock, flags);
1273
1274 if (file->f_mode & FMODE_READ) {
1275 if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
1276 mask |= POLLIN | POLLRDNORM;
1277 }
1278 if (file->f_mode & FMODE_WRITE) {
1279 if (s->dma_dac.mapped) {
1280 if (s->dma_dac.count >=
1281 (signed)s->dma_dac.dma_fragsize)
1282 mask |= POLLOUT | POLLWRNORM;
1283 } else {
1284 if ((signed) s->dma_dac.dmasize >=
1285 s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
1286 mask |= POLLOUT | POLLWRNORM;
1287 }
1288 }
1289 spin_unlock_irqrestore(&s->lock, flags);
1290 return mask;
1291}
1292
1293static int au1000_mmap(struct file *file, struct vm_area_struct *vma)
1294{
1295 struct au1000_state *s = (struct au1000_state *)file->private_data;
1296 struct dmabuf *db;
1297 unsigned long size;
1298 int ret = 0;
1299
1300 dbg("%s", __FUNCTION__);
1301
1302 lock_kernel();
1303 mutex_lock(&s->sem);
1304 if (vma->vm_flags & VM_WRITE)
1305 db = &s->dma_dac;
1306 else if (vma->vm_flags & VM_READ)
1307 db = &s->dma_adc;
1308 else {
1309 ret = -EINVAL;
1310 goto out;
1311 }
1312 if (vma->vm_pgoff != 0) {
1313 ret = -EINVAL;
1314 goto out;
1315 }
1316 size = vma->vm_end - vma->vm_start;
1317 if (size > (PAGE_SIZE << db->buforder)) {
1318 ret = -EINVAL;
1319 goto out;
1320 }
1321 if (remap_pfn_range(vma, vma->vm_start, virt_to_phys(db->rawbuf),
1322 size, vma->vm_page_prot)) {
1323 ret = -EAGAIN;
1324 goto out;
1325 }
1326 vma->vm_flags &= ~VM_IO;
1327 db->mapped = 1;
1328out:
1329 mutex_unlock(&s->sem);
1330 unlock_kernel();
1331 return ret;
1332}
1333
1334
1335#ifdef AU1000_VERBOSE_DEBUG
1336static struct ioctl_str_t {
1337 unsigned int cmd;
1338 const char *str;
1339} ioctl_str[] = {
1340 {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1341 {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1342 {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1343 {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1344 {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1345 {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1346 {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1347 {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1348 {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1349 {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1350 {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1351 {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1352 {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1353 {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1354 {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1355 {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1356 {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1357 {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1358 {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1359 {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1360 {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1361 {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1362 {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1363 {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1364 {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1365 {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1366 {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1367 {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1368 {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1369 {OSS_GETVERSION, "OSS_GETVERSION"},
1370 {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1371 {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1372 {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1373 {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1374};
1375#endif
1376
1377// Need to hold a spin-lock before calling this!
1378static int dma_count_done(struct dmabuf *db)
1379{
1380 if (db->stopped)
1381 return 0;
1382
1383 return db->dma_fragsize - get_dma_residue(db->dmanr);
1384}
1385
1386
1387static int au1000_ioctl(struct inode *inode, struct file *file,
1388 unsigned int cmd, unsigned long arg)
1389{
1390 struct au1000_state *s = (struct au1000_state *)file->private_data;
1391 unsigned long flags;
1392 audio_buf_info abinfo;
1393 count_info cinfo;
1394 int count;
1395 int val, mapped, ret, diff;
1396
1397 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1398 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1399
1400#ifdef AU1000_VERBOSE_DEBUG
1401 for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
1402 if (ioctl_str[count].cmd == cmd)
1403 break;
1404 }
1405 if (count < sizeof(ioctl_str) / sizeof(ioctl_str[0]))
1406 dbg("ioctl %s, arg=0x%lx", ioctl_str[count].str, arg);
1407 else
1408 dbg("ioctl 0x%x unknown, arg=0x%lx", cmd, arg);
1409#endif
1410
1411 switch (cmd) {
1412 case OSS_GETVERSION:
1413 return put_user(SOUND_VERSION, (int *) arg);
1414
1415 case SNDCTL_DSP_SYNC:
1416 if (file->f_mode & FMODE_WRITE)
1417 return drain_dac(s, file->f_flags & O_NONBLOCK);
1418 return 0;
1419
1420 case SNDCTL_DSP_SETDUPLEX:
1421 return 0;
1422
1423 case SNDCTL_DSP_GETCAPS:
1424 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1425 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1426
1427 case SNDCTL_DSP_RESET:
1428 if (file->f_mode & FMODE_WRITE) {
1429 stop_dac(s);
1430 synchronize_irq();
1431 s->dma_dac.count = s->dma_dac.total_bytes = 0;
1432 s->dma_dac.nextIn = s->dma_dac.nextOut =
1433 s->dma_dac.rawbuf;
1434 }
1435 if (file->f_mode & FMODE_READ) {
1436 stop_adc(s);
1437 synchronize_irq();
1438 s->dma_adc.count = s->dma_adc.total_bytes = 0;
1439 s->dma_adc.nextIn = s->dma_adc.nextOut =
1440 s->dma_adc.rawbuf;
1441 }
1442 return 0;
1443
1444 case SNDCTL_DSP_SPEED:
1445 if (get_user(val, (int *) arg))
1446 return -EFAULT;
1447 if (val >= 0) {
1448 if (file->f_mode & FMODE_READ) {
1449 stop_adc(s);
1450 set_adc_rate(s, val);
1451 }
1452 if (file->f_mode & FMODE_WRITE) {
1453 stop_dac(s);
1454 set_dac_rate(s, val);
1455 }
1456 if (s->open_mode & FMODE_READ)
1457 if ((ret = prog_dmabuf_adc(s)))
1458 return ret;
1459 if (s->open_mode & FMODE_WRITE)
1460 if ((ret = prog_dmabuf_dac(s)))
1461 return ret;
1462 }
1463 return put_user((file->f_mode & FMODE_READ) ?
1464 s->dma_adc.sample_rate :
1465 s->dma_dac.sample_rate,
1466 (int *)arg);
1467
1468 case SNDCTL_DSP_STEREO:
1469 if (get_user(val, (int *) arg))
1470 return -EFAULT;
1471 if (file->f_mode & FMODE_READ) {
1472 stop_adc(s);
1473 s->dma_adc.num_channels = val ? 2 : 1;
1474 if ((ret = prog_dmabuf_adc(s)))
1475 return ret;
1476 }
1477 if (file->f_mode & FMODE_WRITE) {
1478 stop_dac(s);
1479 s->dma_dac.num_channels = val ? 2 : 1;
1480 if (s->codec_ext_caps & AC97_EXT_DACS) {
1481 // disable surround and center/lfe in AC'97
1482 u16 ext_stat = rdcodec(&s->codec,
1483 AC97_EXTENDED_STATUS);
1484 wrcodec(&s->codec, AC97_EXTENDED_STATUS,
1485 ext_stat | (AC97_EXTSTAT_PRI |
1486 AC97_EXTSTAT_PRJ |
1487 AC97_EXTSTAT_PRK));
1488 }
1489 if ((ret = prog_dmabuf_dac(s)))
1490 return ret;
1491 }
1492 return 0;
1493
1494 case SNDCTL_DSP_CHANNELS:
1495 if (get_user(val, (int *) arg))
1496 return -EFAULT;
1497 if (val != 0) {
1498 if (file->f_mode & FMODE_READ) {
1499 if (val < 0 || val > 2)
1500 return -EINVAL;
1501 stop_adc(s);
1502 s->dma_adc.num_channels = val;
1503 if ((ret = prog_dmabuf_adc(s)))
1504 return ret;
1505 }
1506 if (file->f_mode & FMODE_WRITE) {
1507 switch (val) {
1508 case 1:
1509 case 2:
1510 break;
1511 case 3:
1512 case 5:
1513 return -EINVAL;
1514 case 4:
1515 if (!(s->codec_ext_caps &
1516 AC97_EXTID_SDAC))
1517 return -EINVAL;
1518 break;
1519 case 6:
1520 if ((s->codec_ext_caps &
1521 AC97_EXT_DACS) != AC97_EXT_DACS)
1522 return -EINVAL;
1523 break;
1524 default:
1525 return -EINVAL;
1526 }
1527
1528 stop_dac(s);
1529 if (val <= 2 &&
1530 (s->codec_ext_caps & AC97_EXT_DACS)) {
1531 // disable surround and center/lfe
1532 // channels in AC'97
1533 u16 ext_stat =
1534 rdcodec(&s->codec,
1535 AC97_EXTENDED_STATUS);
1536 wrcodec(&s->codec,
1537 AC97_EXTENDED_STATUS,
1538 ext_stat | (AC97_EXTSTAT_PRI |
1539 AC97_EXTSTAT_PRJ |
1540 AC97_EXTSTAT_PRK));
1541 } else if (val >= 4) {
1542 // enable surround, center/lfe
1543 // channels in AC'97
1544 u16 ext_stat =
1545 rdcodec(&s->codec,
1546 AC97_EXTENDED_STATUS);
1547 ext_stat &= ~AC97_EXTSTAT_PRJ;
1548 if (val == 6)
1549 ext_stat &=
1550 ~(AC97_EXTSTAT_PRI |
1551 AC97_EXTSTAT_PRK);
1552 wrcodec(&s->codec,
1553 AC97_EXTENDED_STATUS,
1554 ext_stat);
1555 }
1556
1557 s->dma_dac.num_channels = val;
1558 if ((ret = prog_dmabuf_dac(s)))
1559 return ret;
1560 }
1561 }
1562 return put_user(val, (int *) arg);
1563
1564 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1565 return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
1566
1567 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
1568 if (get_user(val, (int *) arg))
1569 return -EFAULT;
1570 if (val != AFMT_QUERY) {
1571 if (file->f_mode & FMODE_READ) {
1572 stop_adc(s);
1573 if (val == AFMT_S16_LE)
1574 s->dma_adc.sample_size = 16;
1575 else {
1576 val = AFMT_U8;
1577 s->dma_adc.sample_size = 8;
1578 }
1579 if ((ret = prog_dmabuf_adc(s)))
1580 return ret;
1581 }
1582 if (file->f_mode & FMODE_WRITE) {
1583 stop_dac(s);
1584 if (val == AFMT_S16_LE)
1585 s->dma_dac.sample_size = 16;
1586 else {
1587 val = AFMT_U8;
1588 s->dma_dac.sample_size = 8;
1589 }
1590 if ((ret = prog_dmabuf_dac(s)))
1591 return ret;
1592 }
1593 } else {
1594 if (file->f_mode & FMODE_READ)
1595 val = (s->dma_adc.sample_size == 16) ?
1596 AFMT_S16_LE : AFMT_U8;
1597 else
1598 val = (s->dma_dac.sample_size == 16) ?
1599 AFMT_S16_LE : AFMT_U8;
1600 }
1601 return put_user(val, (int *) arg);
1602
1603 case SNDCTL_DSP_POST:
1604 return 0;
1605
1606 case SNDCTL_DSP_GETTRIGGER:
1607 val = 0;
1608 spin_lock_irqsave(&s->lock, flags);
1609 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1610 val |= PCM_ENABLE_INPUT;
1611 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1612 val |= PCM_ENABLE_OUTPUT;
1613 spin_unlock_irqrestore(&s->lock, flags);
1614 return put_user(val, (int *) arg);
1615
1616 case SNDCTL_DSP_SETTRIGGER:
1617 if (get_user(val, (int *) arg))
1618 return -EFAULT;
1619 if (file->f_mode & FMODE_READ) {
1620 if (val & PCM_ENABLE_INPUT)
1621 start_adc(s);
1622 else
1623 stop_adc(s);
1624 }
1625 if (file->f_mode & FMODE_WRITE) {
1626 if (val & PCM_ENABLE_OUTPUT)
1627 start_dac(s);
1628 else
1629 stop_dac(s);
1630 }
1631 return 0;
1632
1633 case SNDCTL_DSP_GETOSPACE:
1634 if (!(file->f_mode & FMODE_WRITE))
1635 return -EINVAL;
1636 abinfo.fragsize = s->dma_dac.fragsize;
1637 spin_lock_irqsave(&s->lock, flags);
1638 count = s->dma_dac.count;
1639 count -= dma_count_done(&s->dma_dac);
1640 spin_unlock_irqrestore(&s->lock, flags);
1641 if (count < 0)
1642 count = 0;
1643 abinfo.bytes = (s->dma_dac.dmasize - count) /
1644 s->dma_dac.cnt_factor;
1645 abinfo.fragstotal = s->dma_dac.numfrag;
1646 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1647#ifdef AU1000_VERBOSE_DEBUG
1648 dbg("bytes=%d, fragments=%d", abinfo.bytes, abinfo.fragments);
1649#endif
1650 return copy_to_user((void *) arg, &abinfo,
1651 sizeof(abinfo)) ? -EFAULT : 0;
1652
1653 case SNDCTL_DSP_GETISPACE:
1654 if (!(file->f_mode & FMODE_READ))
1655 return -EINVAL;
1656 abinfo.fragsize = s->dma_adc.fragsize;
1657 spin_lock_irqsave(&s->lock, flags);
1658 count = s->dma_adc.count;
1659 count += dma_count_done(&s->dma_adc);
1660 spin_unlock_irqrestore(&s->lock, flags);
1661 if (count < 0)
1662 count = 0;
1663 abinfo.bytes = count / s->dma_adc.cnt_factor;
1664 abinfo.fragstotal = s->dma_adc.numfrag;
1665 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1666 return copy_to_user((void *) arg, &abinfo,
1667 sizeof(abinfo)) ? -EFAULT : 0;
1668
1669 case SNDCTL_DSP_NONBLOCK:
1670 file->f_flags |= O_NONBLOCK;
1671 return 0;
1672
1673 case SNDCTL_DSP_GETODELAY:
1674 if (!(file->f_mode & FMODE_WRITE))
1675 return -EINVAL;
1676 spin_lock_irqsave(&s->lock, flags);
1677 count = s->dma_dac.count;
1678 count -= dma_count_done(&s->dma_dac);
1679 spin_unlock_irqrestore(&s->lock, flags);
1680 if (count < 0)
1681 count = 0;
1682 count /= s->dma_dac.cnt_factor;
1683 return put_user(count, (int *) arg);
1684
1685 case SNDCTL_DSP_GETIPTR:
1686 if (!(file->f_mode & FMODE_READ))
1687 return -EINVAL;
1688 spin_lock_irqsave(&s->lock, flags);
1689 cinfo.bytes = s->dma_adc.total_bytes;
1690 count = s->dma_adc.count;
1691 if (!s->dma_adc.stopped) {
1692 diff = dma_count_done(&s->dma_adc);
1693 count += diff;
1694 cinfo.bytes += diff;
1695 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
1696 s->dma_adc.dmaaddr;
1697 } else
1698 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
1699 s->dma_adc.dmaaddr;
1700 if (s->dma_adc.mapped)
1701 s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
1702 spin_unlock_irqrestore(&s->lock, flags);
1703 if (count < 0)
1704 count = 0;
1705 cinfo.blocks = count >> s->dma_adc.fragshift;
1706 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
1707
1708 case SNDCTL_DSP_GETOPTR:
1709 if (!(file->f_mode & FMODE_READ))
1710 return -EINVAL;
1711 spin_lock_irqsave(&s->lock, flags);
1712 cinfo.bytes = s->dma_dac.total_bytes;
1713 count = s->dma_dac.count;
1714 if (!s->dma_dac.stopped) {
1715 diff = dma_count_done(&s->dma_dac);
1716 count -= diff;
1717 cinfo.bytes += diff;
1718 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
1719 s->dma_dac.dmaaddr;
1720 } else
1721 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
1722 s->dma_dac.dmaaddr;
1723 if (s->dma_dac.mapped)
1724 s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
1725 spin_unlock_irqrestore(&s->lock, flags);
1726 if (count < 0)
1727 count = 0;
1728 cinfo.blocks = count >> s->dma_dac.fragshift;
1729 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
1730
1731 case SNDCTL_DSP_GETBLKSIZE:
1732 if (file->f_mode & FMODE_WRITE)
1733 return put_user(s->dma_dac.fragsize, (int *) arg);
1734 else
1735 return put_user(s->dma_adc.fragsize, (int *) arg);
1736
1737 case SNDCTL_DSP_SETFRAGMENT:
1738 if (get_user(val, (int *) arg))
1739 return -EFAULT;
1740 if (file->f_mode & FMODE_READ) {
1741 stop_adc(s);
1742 s->dma_adc.ossfragshift = val & 0xffff;
1743 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1744 if (s->dma_adc.ossfragshift < 4)
1745 s->dma_adc.ossfragshift = 4;
1746 if (s->dma_adc.ossfragshift > 15)
1747 s->dma_adc.ossfragshift = 15;
1748 if (s->dma_adc.ossmaxfrags < 4)
1749 s->dma_adc.ossmaxfrags = 4;
1750 if ((ret = prog_dmabuf_adc(s)))
1751 return ret;
1752 }
1753 if (file->f_mode & FMODE_WRITE) {
1754 stop_dac(s);
1755 s->dma_dac.ossfragshift = val & 0xffff;
1756 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1757 if (s->dma_dac.ossfragshift < 4)
1758 s->dma_dac.ossfragshift = 4;
1759 if (s->dma_dac.ossfragshift > 15)
1760 s->dma_dac.ossfragshift = 15;
1761 if (s->dma_dac.ossmaxfrags < 4)
1762 s->dma_dac.ossmaxfrags = 4;
1763 if ((ret = prog_dmabuf_dac(s)))
1764 return ret;
1765 }
1766 return 0;
1767
1768 case SNDCTL_DSP_SUBDIVIDE:
1769 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1770 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1771 return -EINVAL;
1772 if (get_user(val, (int *) arg))
1773 return -EFAULT;
1774 if (val != 1 && val != 2 && val != 4)
1775 return -EINVAL;
1776 if (file->f_mode & FMODE_READ) {
1777 stop_adc(s);
1778 s->dma_adc.subdivision = val;
1779 if ((ret = prog_dmabuf_adc(s)))
1780 return ret;
1781 }
1782 if (file->f_mode & FMODE_WRITE) {
1783 stop_dac(s);
1784 s->dma_dac.subdivision = val;
1785 if ((ret = prog_dmabuf_dac(s)))
1786 return ret;
1787 }
1788 return 0;
1789
1790 case SOUND_PCM_READ_RATE:
1791 return put_user((file->f_mode & FMODE_READ) ?
1792 s->dma_adc.sample_rate :
1793 s->dma_dac.sample_rate,
1794 (int *)arg);
1795
1796 case SOUND_PCM_READ_CHANNELS:
1797 if (file->f_mode & FMODE_READ)
1798 return put_user(s->dma_adc.num_channels, (int *)arg);
1799 else
1800 return put_user(s->dma_dac.num_channels, (int *)arg);
1801
1802 case SOUND_PCM_READ_BITS:
1803 if (file->f_mode & FMODE_READ)
1804 return put_user(s->dma_adc.sample_size, (int *)arg);
1805 else
1806 return put_user(s->dma_dac.sample_size, (int *)arg);
1807
1808 case SOUND_PCM_WRITE_FILTER:
1809 case SNDCTL_DSP_SETSYNCRO:
1810 case SOUND_PCM_READ_FILTER:
1811 return -EINVAL;
1812 }
1813
1814 return mixdev_ioctl(&s->codec, cmd, arg);
1815}
1816
1817
1818static int au1000_open(struct inode *inode, struct file *file)
1819{
1820 int minor = iminor(inode);
1821 DECLARE_WAITQUEUE(wait, current);
1822 struct au1000_state *s = &au1000_state;
1823 int ret;
1824
1825#ifdef AU1000_VERBOSE_DEBUG
1826 if (file->f_flags & O_NONBLOCK)
1827 dbg("%s: non-blocking", __FUNCTION__);
1828 else
1829 dbg("%s: blocking", __FUNCTION__);
1830#endif
1831
1832 file->private_data = s;
1833 /* wait for device to become free */
1834 mutex_lock(&s->open_mutex);
1835 while (s->open_mode & file->f_mode) {
1836 if (file->f_flags & O_NONBLOCK) {
1837 mutex_unlock(&s->open_mutex);
1838 return -EBUSY;
1839 }
1840 add_wait_queue(&s->open_wait, &wait);
1841 __set_current_state(TASK_INTERRUPTIBLE);
1842 mutex_unlock(&s->open_mutex);
1843 schedule();
1844 remove_wait_queue(&s->open_wait, &wait);
1845 set_current_state(TASK_RUNNING);
1846 if (signal_pending(current))
1847 return -ERESTARTSYS;
1848 mutex_lock(&s->open_mutex);
1849 }
1850
1851 stop_dac(s);
1852 stop_adc(s);
1853
1854 if (file->f_mode & FMODE_READ) {
1855 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1856 s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1857 s->dma_adc.num_channels = 1;
1858 s->dma_adc.sample_size = 8;
1859 set_adc_rate(s, 8000);
1860 if ((minor & 0xf) == SND_DEV_DSP16)
1861 s->dma_adc.sample_size = 16;
1862 }
1863
1864 if (file->f_mode & FMODE_WRITE) {
1865 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1866 s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1867 s->dma_dac.num_channels = 1;
1868 s->dma_dac.sample_size = 8;
1869 set_dac_rate(s, 8000);
1870 if ((minor & 0xf) == SND_DEV_DSP16)
1871 s->dma_dac.sample_size = 16;
1872 }
1873
1874 if (file->f_mode & FMODE_READ) {
1875 if ((ret = prog_dmabuf_adc(s)))
1876 return ret;
1877 }
1878 if (file->f_mode & FMODE_WRITE) {
1879 if ((ret = prog_dmabuf_dac(s)))
1880 return ret;
1881 }
1882
1883 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1884 mutex_unlock(&s->open_mutex);
1885 mutex_init(&s->sem);
1886 return nonseekable_open(inode, file);
1887}
1888
1889static int au1000_release(struct inode *inode, struct file *file)
1890{
1891 struct au1000_state *s = (struct au1000_state *)file->private_data;
1892
1893 lock_kernel();
1894
1895 if (file->f_mode & FMODE_WRITE) {
1896 unlock_kernel();
1897 drain_dac(s, file->f_flags & O_NONBLOCK);
1898 lock_kernel();
1899 }
1900
1901 mutex_lock(&s->open_mutex);
1902 if (file->f_mode & FMODE_WRITE) {
1903 stop_dac(s);
1904 dealloc_dmabuf(s, &s->dma_dac);
1905 }
1906 if (file->f_mode & FMODE_READ) {
1907 stop_adc(s);
1908 dealloc_dmabuf(s, &s->dma_adc);
1909 }
1910 s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
1911 mutex_unlock(&s->open_mutex);
1912 wake_up(&s->open_wait);
1913 unlock_kernel();
1914 return 0;
1915}
1916
1917static /*const */ struct file_operations au1000_audio_fops = {
1918 .owner = THIS_MODULE,
1919 .llseek = au1000_llseek,
1920 .read = au1000_read,
1921 .write = au1000_write,
1922 .poll = au1000_poll,
1923 .ioctl = au1000_ioctl,
1924 .mmap = au1000_mmap,
1925 .open = au1000_open,
1926 .release = au1000_release,
1927};
1928
1929
1930/* --------------------------------------------------------------------- */
1931
1932
1933/* --------------------------------------------------------------------- */
1934
1935/*
1936 * for debugging purposes, we'll create a proc device that dumps the
1937 * CODEC chipstate
1938 */
1939
1940#ifdef AU1000_DEBUG
1941static int proc_au1000_dump(char *buf, char **start, off_t fpos,
1942 int length, int *eof, void *data)
1943{
1944 struct au1000_state *s = &au1000_state;
1945 int cnt, len = 0;
1946
1947 /* print out header */
1948 len += sprintf(buf + len, "\n\t\tAU1000 Audio Debug\n\n");
1949
1950 // print out digital controller state
1951 len += sprintf(buf + len, "AU1000 Audio Controller registers\n");
1952 len += sprintf(buf + len, "---------------------------------\n");
1953 len += sprintf (buf + len, "AC97C_CONFIG = %08x\n",
1954 au_readl(AC97C_CONFIG));
1955 len += sprintf (buf + len, "AC97C_STATUS = %08x\n",
1956 au_readl(AC97C_STATUS));
1957 len += sprintf (buf + len, "AC97C_CNTRL = %08x\n",
1958 au_readl(AC97C_CNTRL));
1959
1960 /* print out CODEC state */
1961 len += sprintf(buf + len, "\nAC97 CODEC registers\n");
1962 len += sprintf(buf + len, "----------------------\n");
1963 for (cnt = 0; cnt <= 0x7e; cnt += 2)
1964 len += sprintf(buf + len, "reg %02x = %04x\n",
1965 cnt, rdcodec(&s->codec, cnt));
1966
1967 if (fpos >= len) {
1968 *start = buf;
1969 *eof = 1;
1970 return 0;
1971 }
1972 *start = buf + fpos;
1973 if ((len -= fpos) > length)
1974 return length;
1975 *eof = 1;
1976 return len;
1977
1978}
1979#endif /* AU1000_DEBUG */
1980
1981/* --------------------------------------------------------------------- */
1982
1983MODULE_AUTHOR("Monta Vista Software, stevel@mvista.com");
1984MODULE_DESCRIPTION("Au1000 Audio Driver");
1985
1986/* --------------------------------------------------------------------- */
1987
1988static int __devinit au1000_probe(void)
1989{
1990 struct au1000_state *s = &au1000_state;
1991 int val;
1992#ifdef AU1000_DEBUG
1993 char proc_str[80];
1994#endif
1995
1996 memset(s, 0, sizeof(struct au1000_state));
1997
1998 init_waitqueue_head(&s->dma_adc.wait);
1999 init_waitqueue_head(&s->dma_dac.wait);
2000 init_waitqueue_head(&s->open_wait);
2001 mutex_init(&s->open_mutex);
2002 spin_lock_init(&s->lock);
2003 s->codec.private_data = s;
2004 s->codec.id = 0;
2005 s->codec.codec_read = rdcodec;
2006 s->codec.codec_write = wrcodec;
2007 s->codec.codec_wait = waitcodec;
2008
2009 if (!request_mem_region(CPHYSADDR(AC97C_CONFIG),
2010 0x14, AU1000_MODULE_NAME)) {
2011 err("AC'97 ports in use");
2012 return -1;
2013 }
2014 // Allocate the DMA Channels
2015 if ((s->dma_dac.dmanr = request_au1000_dma(DMA_ID_AC97C_TX,
2016 "audio DAC",
2017 dac_dma_interrupt,
2018 IRQF_DISABLED, s)) < 0) {
2019 err("Can't get DAC DMA");
2020 goto err_dma1;
2021 }
2022 if ((s->dma_adc.dmanr = request_au1000_dma(DMA_ID_AC97C_RX,
2023 "audio ADC",
2024 adc_dma_interrupt,
2025 IRQF_DISABLED, s)) < 0) {
2026 err("Can't get ADC DMA");
2027 goto err_dma2;
2028 }
2029
2030 info("DAC: DMA%d/IRQ%d, ADC: DMA%d/IRQ%d",
2031 s->dma_dac.dmanr, get_dma_done_irq(s->dma_dac.dmanr),
2032 s->dma_adc.dmanr, get_dma_done_irq(s->dma_adc.dmanr));
2033
2034 // enable DMA coherency in read/write DMA channels
2035 set_dma_mode(s->dma_dac.dmanr,
2036 get_dma_mode(s->dma_dac.dmanr) & ~DMA_NC);
2037 set_dma_mode(s->dma_adc.dmanr,
2038 get_dma_mode(s->dma_adc.dmanr) & ~DMA_NC);
2039
2040 /* register devices */
2041
2042 if ((s->dev_audio = register_sound_dsp(&au1000_audio_fops, -1)) < 0)
2043 goto err_dev1;
2044 if ((s->codec.dev_mixer =
2045 register_sound_mixer(&au1000_mixer_fops, -1)) < 0)
2046 goto err_dev2;
2047
2048#ifdef AU1000_DEBUG
2049 /* intialize the debug proc device */
2050 s->ps = create_proc_read_entry(AU1000_MODULE_NAME, 0, NULL,
2051 proc_au1000_dump, NULL);
2052#endif /* AU1000_DEBUG */
2053
2054 // configure pins for AC'97
2055 au_writel(au_readl(SYS_PINFUNC) & ~0x02, SYS_PINFUNC);
2056
2057 // Assert reset for 10msec to the AC'97 controller, and enable clock
2058 au_writel(AC97C_RS | AC97C_CE, AC97C_CNTRL);
2059 au1000_delay(10);
2060 au_writel(AC97C_CE, AC97C_CNTRL);
2061 au1000_delay(10); // wait for clock to stabilize
2062
2063 /* cold reset the AC'97 */
2064 au_writel(AC97C_RESET, AC97C_CONFIG);
2065 au1000_delay(10);
2066 au_writel(0, AC97C_CONFIG);
2067 /* need to delay around 500msec(bleech) to give
2068 some CODECs enough time to wakeup */
2069 au1000_delay(500);
2070
2071 /* warm reset the AC'97 to start the bitclk */
2072 au_writel(AC97C_SG | AC97C_SYNC, AC97C_CONFIG);
2073 udelay(100);
2074 au_writel(0, AC97C_CONFIG);
2075
2076 /* codec init */
2077 if (!ac97_probe_codec(&s->codec))
2078 goto err_dev3;
2079
2080 s->codec_base_caps = rdcodec(&s->codec, AC97_RESET);
2081 s->codec_ext_caps = rdcodec(&s->codec, AC97_EXTENDED_ID);
2082 info("AC'97 Base/Extended ID = %04x/%04x",
2083 s->codec_base_caps, s->codec_ext_caps);
2084
2085 /*
2086 * On the Pb1000, audio playback is on the AUX_OUT
2087 * channel (which defaults to LNLVL_OUT in AC'97
2088 * rev 2.2) so make sure this channel is listed
2089 * as supported (soundcard.h calls this channel
2090 * ALTPCM). ac97_codec.c does not handle detection
2091 * of this channel correctly.
2092 */
2093 s->codec.supported_mixers |= SOUND_MASK_ALTPCM;
2094 /*
2095 * Now set AUX_OUT's default volume.
2096 */
2097 val = 0x4343;
2098 mixdev_ioctl(&s->codec, SOUND_MIXER_WRITE_ALTPCM,
2099 (unsigned long) &val);
2100
2101 if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
2102 // codec does not support VRA
2103 s->no_vra = 1;
2104 } else if (!vra) {
2105 // Boot option says disable VRA
2106 u16 ac97_extstat = rdcodec(&s->codec, AC97_EXTENDED_STATUS);
2107 wrcodec(&s->codec, AC97_EXTENDED_STATUS,
2108 ac97_extstat & ~AC97_EXTSTAT_VRA);
2109 s->no_vra = 1;
2110 }
2111 if (s->no_vra)
2112 info("no VRA, interpolating and decimating");
2113
2114 /* set mic to be the recording source */
2115 val = SOUND_MASK_MIC;
2116 mixdev_ioctl(&s->codec, SOUND_MIXER_WRITE_RECSRC,
2117 (unsigned long) &val);
2118
2119#ifdef AU1000_DEBUG
2120 sprintf(proc_str, "driver/%s/%d/ac97", AU1000_MODULE_NAME,
2121 s->codec.id);
2122 s->ac97_ps = create_proc_read_entry (proc_str, 0, NULL,
2123 ac97_read_proc, &s->codec);
2124#endif
2125
2126#ifdef CONFIG_MIPS_XXS1500
2127 /* deassert eapd */
2128 wrcodec(&s->codec, AC97_POWER_CONTROL,
2129 rdcodec(&s->codec, AC97_POWER_CONTROL) & ~0x8000);
2130 /* mute a number of signals which seem to be causing problems
2131 * if not muted.
2132 */
2133 wrcodec(&s->codec, AC97_PCBEEP_VOL, 0x8000);
2134 wrcodec(&s->codec, AC97_PHONE_VOL, 0x8008);
2135 wrcodec(&s->codec, AC97_MIC_VOL, 0x8008);
2136 wrcodec(&s->codec, AC97_LINEIN_VOL, 0x8808);
2137 wrcodec(&s->codec, AC97_CD_VOL, 0x8808);
2138 wrcodec(&s->codec, AC97_VIDEO_VOL, 0x8808);
2139 wrcodec(&s->codec, AC97_AUX_VOL, 0x8808);
2140 wrcodec(&s->codec, AC97_PCMOUT_VOL, 0x0808);
2141 wrcodec(&s->codec, AC97_GENERAL_PURPOSE, 0x2000);
2142#endif
2143
2144 return 0;
2145
2146 err_dev3:
2147 unregister_sound_mixer(s->codec.dev_mixer);
2148 err_dev2:
2149 unregister_sound_dsp(s->dev_audio);
2150 err_dev1:
2151 free_au1000_dma(s->dma_adc.dmanr);
2152 err_dma2:
2153 free_au1000_dma(s->dma_dac.dmanr);
2154 err_dma1:
2155 release_mem_region(CPHYSADDR(AC97C_CONFIG), 0x14);
2156 return -1;
2157}
2158
2159static void au1000_remove(void)
2160{
2161 struct au1000_state *s = &au1000_state;
2162
2163 if (!s)
2164 return;
2165#ifdef AU1000_DEBUG
2166 if (s->ps)
2167 remove_proc_entry(AU1000_MODULE_NAME, NULL);
2168#endif /* AU1000_DEBUG */
2169 synchronize_irq();
2170 free_au1000_dma(s->dma_adc.dmanr);
2171 free_au1000_dma(s->dma_dac.dmanr);
2172 release_mem_region(CPHYSADDR(AC97C_CONFIG), 0x14);
2173 unregister_sound_dsp(s->dev_audio);
2174 unregister_sound_mixer(s->codec.dev_mixer);
2175}
2176
2177static int __init init_au1000(void)
2178{
2179 info("stevel@mvista.com, built " __TIME__ " on " __DATE__);
2180 return au1000_probe();
2181}
2182
2183static void __exit cleanup_au1000(void)
2184{
2185 info("unloading");
2186 au1000_remove();
2187}
2188
2189module_init(init_au1000);
2190module_exit(cleanup_au1000);
2191
2192/* --------------------------------------------------------------------- */
2193
2194#ifndef MODULE
2195
2196static int __init au1000_setup(char *options)
2197{
2198 char *this_opt;
2199
2200 if (!options || !*options)
2201 return 0;
2202
2203 while ((this_opt = strsep(&options, ","))) {
2204 if (!*this_opt)
2205 continue;
2206 if (!strncmp(this_opt, "vra", 3)) {
2207 vra = 1;
2208 }
2209 }
2210
2211 return 1;
2212}
2213
2214__setup("au1000_audio=", au1000_setup);
2215
2216#endif /* MODULE */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 01:03:25 -0500