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-rw-r--r--sound/firewire/dice/dice.c1512
1 files changed, 1512 insertions, 0 deletions
diff --git a/sound/firewire/dice/dice.c b/sound/firewire/dice/dice.c
new file mode 100644
index 000000000000..d3ec778878af
--- /dev/null
+++ b/sound/firewire/dice/dice.c
@@ -0,0 +1,1512 @@
1/*
2 * TC Applied Technologies Digital Interface Communications Engine driver
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 * Licensed under the terms of the GNU General Public License, version 2.
6 */
7
8#include <linux/compat.h>
9#include <linux/completion.h>
10#include <linux/delay.h>
11#include <linux/device.h>
12#include <linux/firewire.h>
13#include <linux/firewire-constants.h>
14#include <linux/jiffies.h>
15#include <linux/module.h>
16#include <linux/mod_devicetable.h>
17#include <linux/mutex.h>
18#include <linux/slab.h>
19#include <linux/spinlock.h>
20#include <linux/wait.h>
21#include <sound/control.h>
22#include <sound/core.h>
23#include <sound/firewire.h>
24#include <sound/hwdep.h>
25#include <sound/info.h>
26#include <sound/initval.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include "../amdtp.h"
30#include "../iso-resources.h"
31#include "../lib.h"
32#include "dice-interface.h"
33
34
35struct snd_dice {
36 struct snd_card *card;
37 struct fw_unit *unit;
38 spinlock_t lock;
39 struct mutex mutex;
40 unsigned int global_offset;
41 unsigned int rx_offset;
42 unsigned int clock_caps;
43 unsigned int rx_channels[3];
44 unsigned int rx_midi_ports[3];
45 struct fw_address_handler notification_handler;
46 int owner_generation;
47 int dev_lock_count; /* > 0 driver, < 0 userspace */
48 bool dev_lock_changed;
49 bool global_enabled;
50 struct completion clock_accepted;
51 wait_queue_head_t hwdep_wait;
52 u32 notification_bits;
53 struct fw_iso_resources rx_resources;
54 struct amdtp_stream rx_stream;
55};
56
57MODULE_DESCRIPTION("DICE driver");
58MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
59MODULE_LICENSE("GPL v2");
60
61static const unsigned int dice_rates[] = {
62 /* mode 0 */
63 [0] = 32000,
64 [1] = 44100,
65 [2] = 48000,
66 /* mode 1 */
67 [3] = 88200,
68 [4] = 96000,
69 /* mode 2 */
70 [5] = 176400,
71 [6] = 192000,
72};
73
74static unsigned int rate_to_index(unsigned int rate)
75{
76 unsigned int i;
77
78 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
79 if (dice_rates[i] == rate)
80 return i;
81
82 return 0;
83}
84
85static unsigned int rate_index_to_mode(unsigned int rate_index)
86{
87 return ((int)rate_index - 1) / 2;
88}
89
90static void dice_lock_changed(struct snd_dice *dice)
91{
92 dice->dev_lock_changed = true;
93 wake_up(&dice->hwdep_wait);
94}
95
96static int dice_try_lock(struct snd_dice *dice)
97{
98 int err;
99
100 spin_lock_irq(&dice->lock);
101
102 if (dice->dev_lock_count < 0) {
103 err = -EBUSY;
104 goto out;
105 }
106
107 if (dice->dev_lock_count++ == 0)
108 dice_lock_changed(dice);
109 err = 0;
110
111out:
112 spin_unlock_irq(&dice->lock);
113
114 return err;
115}
116
117static void dice_unlock(struct snd_dice *dice)
118{
119 spin_lock_irq(&dice->lock);
120
121 if (WARN_ON(dice->dev_lock_count <= 0))
122 goto out;
123
124 if (--dice->dev_lock_count == 0)
125 dice_lock_changed(dice);
126
127out:
128 spin_unlock_irq(&dice->lock);
129}
130
131static inline u64 global_address(struct snd_dice *dice, unsigned int offset)
132{
133 return DICE_PRIVATE_SPACE + dice->global_offset + offset;
134}
135
136/* TODO: rx index */
137static inline u64 rx_address(struct snd_dice *dice, unsigned int offset)
138{
139 return DICE_PRIVATE_SPACE + dice->rx_offset + offset;
140}
141
142static int dice_owner_set(struct snd_dice *dice)
143{
144 struct fw_device *device = fw_parent_device(dice->unit);
145 __be64 *buffer;
146 int err, errors = 0;
147
148 buffer = kmalloc(2 * 8, GFP_KERNEL);
149 if (!buffer)
150 return -ENOMEM;
151
152 for (;;) {
153 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
154 buffer[1] = cpu_to_be64(
155 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
156 dice->notification_handler.offset);
157
158 dice->owner_generation = device->generation;
159 smp_rmb(); /* node_id vs. generation */
160 err = snd_fw_transaction(dice->unit,
161 TCODE_LOCK_COMPARE_SWAP,
162 global_address(dice, GLOBAL_OWNER),
163 buffer, 2 * 8,
164 FW_FIXED_GENERATION |
165 dice->owner_generation);
166
167 if (err == 0) {
168 if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
169 dev_err(&dice->unit->device,
170 "device is already in use\n");
171 err = -EBUSY;
172 }
173 break;
174 }
175 if (err != -EAGAIN || ++errors >= 3)
176 break;
177
178 msleep(20);
179 }
180
181 kfree(buffer);
182
183 return err;
184}
185
186static int dice_owner_update(struct snd_dice *dice)
187{
188 struct fw_device *device = fw_parent_device(dice->unit);
189 __be64 *buffer;
190 int err;
191
192 if (dice->owner_generation == -1)
193 return 0;
194
195 buffer = kmalloc(2 * 8, GFP_KERNEL);
196 if (!buffer)
197 return -ENOMEM;
198
199 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
200 buffer[1] = cpu_to_be64(
201 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
202 dice->notification_handler.offset);
203
204 dice->owner_generation = device->generation;
205 smp_rmb(); /* node_id vs. generation */
206 err = snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
207 global_address(dice, GLOBAL_OWNER),
208 buffer, 2 * 8,
209 FW_FIXED_GENERATION | dice->owner_generation);
210
211 if (err == 0) {
212 if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
213 dev_err(&dice->unit->device,
214 "device is already in use\n");
215 err = -EBUSY;
216 }
217 } else if (err == -EAGAIN) {
218 err = 0; /* try again later */
219 }
220
221 kfree(buffer);
222
223 if (err < 0)
224 dice->owner_generation = -1;
225
226 return err;
227}
228
229static void dice_owner_clear(struct snd_dice *dice)
230{
231 struct fw_device *device = fw_parent_device(dice->unit);
232 __be64 *buffer;
233
234 buffer = kmalloc(2 * 8, GFP_KERNEL);
235 if (!buffer)
236 return;
237
238 buffer[0] = cpu_to_be64(
239 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
240 dice->notification_handler.offset);
241 buffer[1] = cpu_to_be64(OWNER_NO_OWNER);
242 snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
243 global_address(dice, GLOBAL_OWNER),
244 buffer, 2 * 8, FW_QUIET |
245 FW_FIXED_GENERATION | dice->owner_generation);
246
247 kfree(buffer);
248
249 dice->owner_generation = -1;
250}
251
252static int dice_enable_set(struct snd_dice *dice)
253{
254 __be32 value;
255 int err;
256
257 value = cpu_to_be32(1);
258 err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
259 global_address(dice, GLOBAL_ENABLE),
260 &value, 4,
261 FW_FIXED_GENERATION | dice->owner_generation);
262 if (err < 0)
263 return err;
264
265 dice->global_enabled = true;
266
267 return 0;
268}
269
270static void dice_enable_clear(struct snd_dice *dice)
271{
272 __be32 value;
273
274 if (!dice->global_enabled)
275 return;
276
277 value = 0;
278 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
279 global_address(dice, GLOBAL_ENABLE),
280 &value, 4, FW_QUIET |
281 FW_FIXED_GENERATION | dice->owner_generation);
282
283 dice->global_enabled = false;
284}
285
286static void dice_notification(struct fw_card *card, struct fw_request *request,
287 int tcode, int destination, int source,
288 int generation, unsigned long long offset,
289 void *data, size_t length, void *callback_data)
290{
291 struct snd_dice *dice = callback_data;
292 u32 bits;
293 unsigned long flags;
294
295 if (tcode != TCODE_WRITE_QUADLET_REQUEST) {
296 fw_send_response(card, request, RCODE_TYPE_ERROR);
297 return;
298 }
299 if ((offset & 3) != 0) {
300 fw_send_response(card, request, RCODE_ADDRESS_ERROR);
301 return;
302 }
303
304 bits = be32_to_cpup(data);
305
306 spin_lock_irqsave(&dice->lock, flags);
307 dice->notification_bits |= bits;
308 spin_unlock_irqrestore(&dice->lock, flags);
309
310 fw_send_response(card, request, RCODE_COMPLETE);
311
312 if (bits & NOTIFY_CLOCK_ACCEPTED)
313 complete(&dice->clock_accepted);
314 wake_up(&dice->hwdep_wait);
315}
316
317static int dice_rate_constraint(struct snd_pcm_hw_params *params,
318 struct snd_pcm_hw_rule *rule)
319{
320 struct snd_dice *dice = rule->private;
321 const struct snd_interval *channels =
322 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_CHANNELS);
323 struct snd_interval *rate =
324 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
325 struct snd_interval allowed_rates = {
326 .min = UINT_MAX, .max = 0, .integer = 1
327 };
328 unsigned int i, mode;
329
330 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i) {
331 mode = rate_index_to_mode(i);
332 if ((dice->clock_caps & (1 << i)) &&
333 snd_interval_test(channels, dice->rx_channels[mode])) {
334 allowed_rates.min = min(allowed_rates.min,
335 dice_rates[i]);
336 allowed_rates.max = max(allowed_rates.max,
337 dice_rates[i]);
338 }
339 }
340
341 return snd_interval_refine(rate, &allowed_rates);
342}
343
344static int dice_channels_constraint(struct snd_pcm_hw_params *params,
345 struct snd_pcm_hw_rule *rule)
346{
347 struct snd_dice *dice = rule->private;
348 const struct snd_interval *rate =
349 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
350 struct snd_interval *channels =
351 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
352 struct snd_interval allowed_channels = {
353 .min = UINT_MAX, .max = 0, .integer = 1
354 };
355 unsigned int i, mode;
356
357 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
358 if ((dice->clock_caps & (1 << i)) &&
359 snd_interval_test(rate, dice_rates[i])) {
360 mode = rate_index_to_mode(i);
361 allowed_channels.min = min(allowed_channels.min,
362 dice->rx_channels[mode]);
363 allowed_channels.max = max(allowed_channels.max,
364 dice->rx_channels[mode]);
365 }
366
367 return snd_interval_refine(channels, &allowed_channels);
368}
369
370static int dice_open(struct snd_pcm_substream *substream)
371{
372 static const struct snd_pcm_hardware hardware = {
373 .info = SNDRV_PCM_INFO_MMAP |
374 SNDRV_PCM_INFO_MMAP_VALID |
375 SNDRV_PCM_INFO_BATCH |
376 SNDRV_PCM_INFO_INTERLEAVED |
377 SNDRV_PCM_INFO_BLOCK_TRANSFER,
378 .formats = AMDTP_OUT_PCM_FORMAT_BITS,
379 .channels_min = UINT_MAX,
380 .channels_max = 0,
381 .buffer_bytes_max = 16 * 1024 * 1024,
382 .period_bytes_min = 1,
383 .period_bytes_max = UINT_MAX,
384 .periods_min = 1,
385 .periods_max = UINT_MAX,
386 };
387 struct snd_dice *dice = substream->private_data;
388 struct snd_pcm_runtime *runtime = substream->runtime;
389 unsigned int i;
390 int err;
391
392 err = dice_try_lock(dice);
393 if (err < 0)
394 goto error;
395
396 runtime->hw = hardware;
397
398 for (i = 0; i < ARRAY_SIZE(dice_rates); ++i)
399 if (dice->clock_caps & (1 << i))
400 runtime->hw.rates |=
401 snd_pcm_rate_to_rate_bit(dice_rates[i]);
402 snd_pcm_limit_hw_rates(runtime);
403
404 for (i = 0; i < 3; ++i)
405 if (dice->rx_channels[i]) {
406 runtime->hw.channels_min = min(runtime->hw.channels_min,
407 dice->rx_channels[i]);
408 runtime->hw.channels_max = max(runtime->hw.channels_max,
409 dice->rx_channels[i]);
410 }
411
412 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
413 dice_rate_constraint, dice,
414 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
415 if (err < 0)
416 goto err_lock;
417 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
418 dice_channels_constraint, dice,
419 SNDRV_PCM_HW_PARAM_RATE, -1);
420 if (err < 0)
421 goto err_lock;
422
423 err = amdtp_stream_add_pcm_hw_constraints(&dice->rx_stream, runtime);
424 if (err < 0)
425 goto err_lock;
426
427 return 0;
428
429err_lock:
430 dice_unlock(dice);
431error:
432 return err;
433}
434
435static int dice_close(struct snd_pcm_substream *substream)
436{
437 struct snd_dice *dice = substream->private_data;
438
439 dice_unlock(dice);
440
441 return 0;
442}
443
444static int dice_stream_start_packets(struct snd_dice *dice)
445{
446 int err;
447
448 if (amdtp_stream_running(&dice->rx_stream))
449 return 0;
450
451 err = amdtp_stream_start(&dice->rx_stream, dice->rx_resources.channel,
452 fw_parent_device(dice->unit)->max_speed);
453 if (err < 0)
454 return err;
455
456 err = dice_enable_set(dice);
457 if (err < 0) {
458 amdtp_stream_stop(&dice->rx_stream);
459 return err;
460 }
461
462 return 0;
463}
464
465static int dice_stream_start(struct snd_dice *dice)
466{
467 __be32 channel;
468 int err;
469
470 if (!dice->rx_resources.allocated) {
471 err = fw_iso_resources_allocate(&dice->rx_resources,
472 amdtp_stream_get_max_payload(&dice->rx_stream),
473 fw_parent_device(dice->unit)->max_speed);
474 if (err < 0)
475 goto error;
476
477 channel = cpu_to_be32(dice->rx_resources.channel);
478 err = snd_fw_transaction(dice->unit,
479 TCODE_WRITE_QUADLET_REQUEST,
480 rx_address(dice, RX_ISOCHRONOUS),
481 &channel, 4, 0);
482 if (err < 0)
483 goto err_resources;
484 }
485
486 err = dice_stream_start_packets(dice);
487 if (err < 0)
488 goto err_rx_channel;
489
490 return 0;
491
492err_rx_channel:
493 channel = cpu_to_be32((u32)-1);
494 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
495 rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
496err_resources:
497 fw_iso_resources_free(&dice->rx_resources);
498error:
499 return err;
500}
501
502static void dice_stream_stop_packets(struct snd_dice *dice)
503{
504 if (amdtp_stream_running(&dice->rx_stream)) {
505 dice_enable_clear(dice);
506 amdtp_stream_stop(&dice->rx_stream);
507 }
508}
509
510static void dice_stream_stop(struct snd_dice *dice)
511{
512 __be32 channel;
513
514 dice_stream_stop_packets(dice);
515
516 if (!dice->rx_resources.allocated)
517 return;
518
519 channel = cpu_to_be32((u32)-1);
520 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
521 rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
522
523 fw_iso_resources_free(&dice->rx_resources);
524}
525
526static int dice_change_rate(struct snd_dice *dice, unsigned int clock_rate)
527{
528 __be32 value;
529 int err;
530
531 reinit_completion(&dice->clock_accepted);
532
533 value = cpu_to_be32(clock_rate | CLOCK_SOURCE_ARX1);
534 err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
535 global_address(dice, GLOBAL_CLOCK_SELECT),
536 &value, 4, 0);
537 if (err < 0)
538 return err;
539
540 if (!wait_for_completion_timeout(&dice->clock_accepted,
541 msecs_to_jiffies(100)))
542 dev_warn(&dice->unit->device, "clock change timed out\n");
543
544 return 0;
545}
546
547static int dice_hw_params(struct snd_pcm_substream *substream,
548 struct snd_pcm_hw_params *hw_params)
549{
550 struct snd_dice *dice = substream->private_data;
551 unsigned int rate_index, mode, rate, channels, i;
552 int err;
553
554 mutex_lock(&dice->mutex);
555 dice_stream_stop(dice);
556 mutex_unlock(&dice->mutex);
557
558 err = snd_pcm_lib_alloc_vmalloc_buffer(substream,
559 params_buffer_bytes(hw_params));
560 if (err < 0)
561 return err;
562
563 rate = params_rate(hw_params);
564 rate_index = rate_to_index(rate);
565 err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
566 if (err < 0)
567 return err;
568
569 /*
570 * At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in
571 * one data block of AMDTP packet. Thus sampling transfer frequency is
572 * a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are
573 * transferred on AMDTP packets at 96 kHz. Two successive samples of a
574 * channel are stored consecutively in the packet. This quirk is called
575 * as 'Dual Wire'.
576 * For this quirk, blocking mode is required and PCM buffer size should
577 * be aligned to SYT_INTERVAL.
578 */
579 channels = params_channels(hw_params);
580 if (rate_index > 4) {
581 if (channels > AMDTP_MAX_CHANNELS_FOR_PCM / 2) {
582 err = -ENOSYS;
583 return err;
584 }
585
586 rate /= 2;
587 channels *= 2;
588 dice->rx_stream.double_pcm_frames = true;
589 } else {
590 dice->rx_stream.double_pcm_frames = false;
591 }
592
593 mode = rate_index_to_mode(rate_index);
594 amdtp_stream_set_parameters(&dice->rx_stream, rate, channels,
595 dice->rx_midi_ports[mode]);
596 if (rate_index > 4) {
597 channels /= 2;
598
599 for (i = 0; i < channels; i++) {
600 dice->rx_stream.pcm_positions[i] = i * 2;
601 dice->rx_stream.pcm_positions[i + channels] = i * 2 + 1;
602 }
603 }
604
605 amdtp_stream_set_pcm_format(&dice->rx_stream,
606 params_format(hw_params));
607
608 return 0;
609}
610
611static int dice_hw_free(struct snd_pcm_substream *substream)
612{
613 struct snd_dice *dice = substream->private_data;
614
615 mutex_lock(&dice->mutex);
616 dice_stream_stop(dice);
617 mutex_unlock(&dice->mutex);
618
619 return snd_pcm_lib_free_vmalloc_buffer(substream);
620}
621
622static int dice_prepare(struct snd_pcm_substream *substream)
623{
624 struct snd_dice *dice = substream->private_data;
625 int err;
626
627 mutex_lock(&dice->mutex);
628
629 if (amdtp_streaming_error(&dice->rx_stream))
630 dice_stream_stop_packets(dice);
631
632 err = dice_stream_start(dice);
633 if (err < 0) {
634 mutex_unlock(&dice->mutex);
635 return err;
636 }
637
638 mutex_unlock(&dice->mutex);
639
640 amdtp_stream_pcm_prepare(&dice->rx_stream);
641
642 return 0;
643}
644
645static int dice_trigger(struct snd_pcm_substream *substream, int cmd)
646{
647 struct snd_dice *dice = substream->private_data;
648 struct snd_pcm_substream *pcm;
649
650 switch (cmd) {
651 case SNDRV_PCM_TRIGGER_START:
652 pcm = substream;
653 break;
654 case SNDRV_PCM_TRIGGER_STOP:
655 pcm = NULL;
656 break;
657 default:
658 return -EINVAL;
659 }
660 amdtp_stream_pcm_trigger(&dice->rx_stream, pcm);
661
662 return 0;
663}
664
665static snd_pcm_uframes_t dice_pointer(struct snd_pcm_substream *substream)
666{
667 struct snd_dice *dice = substream->private_data;
668
669 return amdtp_stream_pcm_pointer(&dice->rx_stream);
670}
671
672static int dice_create_pcm(struct snd_dice *dice)
673{
674 static struct snd_pcm_ops ops = {
675 .open = dice_open,
676 .close = dice_close,
677 .ioctl = snd_pcm_lib_ioctl,
678 .hw_params = dice_hw_params,
679 .hw_free = dice_hw_free,
680 .prepare = dice_prepare,
681 .trigger = dice_trigger,
682 .pointer = dice_pointer,
683 .page = snd_pcm_lib_get_vmalloc_page,
684 .mmap = snd_pcm_lib_mmap_vmalloc,
685 };
686 struct snd_pcm *pcm;
687 int err;
688
689 err = snd_pcm_new(dice->card, "DICE", 0, 1, 0, &pcm);
690 if (err < 0)
691 return err;
692 pcm->private_data = dice;
693 strcpy(pcm->name, dice->card->shortname);
694 pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->ops = &ops;
695
696 return 0;
697}
698
699static long dice_hwdep_read(struct snd_hwdep *hwdep, char __user *buf,
700 long count, loff_t *offset)
701{
702 struct snd_dice *dice = hwdep->private_data;
703 DEFINE_WAIT(wait);
704 union snd_firewire_event event;
705
706 spin_lock_irq(&dice->lock);
707
708 while (!dice->dev_lock_changed && dice->notification_bits == 0) {
709 prepare_to_wait(&dice->hwdep_wait, &wait, TASK_INTERRUPTIBLE);
710 spin_unlock_irq(&dice->lock);
711 schedule();
712 finish_wait(&dice->hwdep_wait, &wait);
713 if (signal_pending(current))
714 return -ERESTARTSYS;
715 spin_lock_irq(&dice->lock);
716 }
717
718 memset(&event, 0, sizeof(event));
719 if (dice->dev_lock_changed) {
720 event.lock_status.type = SNDRV_FIREWIRE_EVENT_LOCK_STATUS;
721 event.lock_status.status = dice->dev_lock_count > 0;
722 dice->dev_lock_changed = false;
723
724 count = min_t(long, count, sizeof(event.lock_status));
725 } else {
726 event.dice_notification.type =
727 SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION;
728 event.dice_notification.notification = dice->notification_bits;
729 dice->notification_bits = 0;
730
731 count = min_t(long, count, sizeof(event.dice_notification));
732 }
733
734 spin_unlock_irq(&dice->lock);
735
736 if (copy_to_user(buf, &event, count))
737 return -EFAULT;
738
739 return count;
740}
741
742static unsigned int dice_hwdep_poll(struct snd_hwdep *hwdep, struct file *file,
743 poll_table *wait)
744{
745 struct snd_dice *dice = hwdep->private_data;
746 unsigned int events;
747
748 poll_wait(file, &dice->hwdep_wait, wait);
749
750 spin_lock_irq(&dice->lock);
751 if (dice->dev_lock_changed || dice->notification_bits != 0)
752 events = POLLIN | POLLRDNORM;
753 else
754 events = 0;
755 spin_unlock_irq(&dice->lock);
756
757 return events;
758}
759
760static int dice_hwdep_get_info(struct snd_dice *dice, void __user *arg)
761{
762 struct fw_device *dev = fw_parent_device(dice->unit);
763 struct snd_firewire_get_info info;
764
765 memset(&info, 0, sizeof(info));
766 info.type = SNDRV_FIREWIRE_TYPE_DICE;
767 info.card = dev->card->index;
768 *(__be32 *)&info.guid[0] = cpu_to_be32(dev->config_rom[3]);
769 *(__be32 *)&info.guid[4] = cpu_to_be32(dev->config_rom[4]);
770 strlcpy(info.device_name, dev_name(&dev->device),
771 sizeof(info.device_name));
772
773 if (copy_to_user(arg, &info, sizeof(info)))
774 return -EFAULT;
775
776 return 0;
777}
778
779static int dice_hwdep_lock(struct snd_dice *dice)
780{
781 int err;
782
783 spin_lock_irq(&dice->lock);
784
785 if (dice->dev_lock_count == 0) {
786 dice->dev_lock_count = -1;
787 err = 0;
788 } else {
789 err = -EBUSY;
790 }
791
792 spin_unlock_irq(&dice->lock);
793
794 return err;
795}
796
797static int dice_hwdep_unlock(struct snd_dice *dice)
798{
799 int err;
800
801 spin_lock_irq(&dice->lock);
802
803 if (dice->dev_lock_count == -1) {
804 dice->dev_lock_count = 0;
805 err = 0;
806 } else {
807 err = -EBADFD;
808 }
809
810 spin_unlock_irq(&dice->lock);
811
812 return err;
813}
814
815static int dice_hwdep_release(struct snd_hwdep *hwdep, struct file *file)
816{
817 struct snd_dice *dice = hwdep->private_data;
818
819 spin_lock_irq(&dice->lock);
820 if (dice->dev_lock_count == -1)
821 dice->dev_lock_count = 0;
822 spin_unlock_irq(&dice->lock);
823
824 return 0;
825}
826
827static int dice_hwdep_ioctl(struct snd_hwdep *hwdep, struct file *file,
828 unsigned int cmd, unsigned long arg)
829{
830 struct snd_dice *dice = hwdep->private_data;
831
832 switch (cmd) {
833 case SNDRV_FIREWIRE_IOCTL_GET_INFO:
834 return dice_hwdep_get_info(dice, (void __user *)arg);
835 case SNDRV_FIREWIRE_IOCTL_LOCK:
836 return dice_hwdep_lock(dice);
837 case SNDRV_FIREWIRE_IOCTL_UNLOCK:
838 return dice_hwdep_unlock(dice);
839 default:
840 return -ENOIOCTLCMD;
841 }
842}
843
844#ifdef CONFIG_COMPAT
845static int dice_hwdep_compat_ioctl(struct snd_hwdep *hwdep, struct file *file,
846 unsigned int cmd, unsigned long arg)
847{
848 return dice_hwdep_ioctl(hwdep, file, cmd,
849 (unsigned long)compat_ptr(arg));
850}
851#else
852#define dice_hwdep_compat_ioctl NULL
853#endif
854
855static int dice_create_hwdep(struct snd_dice *dice)
856{
857 static const struct snd_hwdep_ops ops = {
858 .read = dice_hwdep_read,
859 .release = dice_hwdep_release,
860 .poll = dice_hwdep_poll,
861 .ioctl = dice_hwdep_ioctl,
862 .ioctl_compat = dice_hwdep_compat_ioctl,
863 };
864 struct snd_hwdep *hwdep;
865 int err;
866
867 err = snd_hwdep_new(dice->card, "DICE", 0, &hwdep);
868 if (err < 0)
869 return err;
870 strcpy(hwdep->name, "DICE");
871 hwdep->iface = SNDRV_HWDEP_IFACE_FW_DICE;
872 hwdep->ops = ops;
873 hwdep->private_data = dice;
874 hwdep->exclusive = true;
875
876 return 0;
877}
878
879static int dice_proc_read_mem(struct snd_dice *dice, void *buffer,
880 unsigned int offset_q, unsigned int quadlets)
881{
882 unsigned int i;
883 int err;
884
885 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
886 DICE_PRIVATE_SPACE + 4 * offset_q,
887 buffer, 4 * quadlets, 0);
888 if (err < 0)
889 return err;
890
891 for (i = 0; i < quadlets; ++i)
892 be32_to_cpus(&((u32 *)buffer)[i]);
893
894 return 0;
895}
896
897static const char *str_from_array(const char *const strs[], unsigned int count,
898 unsigned int i)
899{
900 if (i < count)
901 return strs[i];
902
903 return "(unknown)";
904}
905
906static void dice_proc_fixup_string(char *s, unsigned int size)
907{
908 unsigned int i;
909
910 for (i = 0; i < size; i += 4)
911 cpu_to_le32s((u32 *)(s + i));
912
913 for (i = 0; i < size - 2; ++i) {
914 if (s[i] == '\0')
915 return;
916 if (s[i] == '\\' && s[i + 1] == '\\') {
917 s[i + 2] = '\0';
918 return;
919 }
920 }
921 s[size - 1] = '\0';
922}
923
924static void dice_proc_read(struct snd_info_entry *entry,
925 struct snd_info_buffer *buffer)
926{
927 static const char *const section_names[5] = {
928 "global", "tx", "rx", "ext_sync", "unused2"
929 };
930 static const char *const clock_sources[] = {
931 "aes1", "aes2", "aes3", "aes4", "aes", "adat", "tdif",
932 "wc", "arx1", "arx2", "arx3", "arx4", "internal"
933 };
934 static const char *const rates[] = {
935 "32000", "44100", "48000", "88200", "96000", "176400", "192000",
936 "any low", "any mid", "any high", "none"
937 };
938 struct snd_dice *dice = entry->private_data;
939 u32 sections[ARRAY_SIZE(section_names) * 2];
940 struct {
941 u32 number;
942 u32 size;
943 } tx_rx_header;
944 union {
945 struct {
946 u32 owner_hi, owner_lo;
947 u32 notification;
948 char nick_name[NICK_NAME_SIZE];
949 u32 clock_select;
950 u32 enable;
951 u32 status;
952 u32 extended_status;
953 u32 sample_rate;
954 u32 version;
955 u32 clock_caps;
956 char clock_source_names[CLOCK_SOURCE_NAMES_SIZE];
957 } global;
958 struct {
959 u32 iso;
960 u32 number_audio;
961 u32 number_midi;
962 u32 speed;
963 char names[TX_NAMES_SIZE];
964 u32 ac3_caps;
965 u32 ac3_enable;
966 } tx;
967 struct {
968 u32 iso;
969 u32 seq_start;
970 u32 number_audio;
971 u32 number_midi;
972 char names[RX_NAMES_SIZE];
973 u32 ac3_caps;
974 u32 ac3_enable;
975 } rx;
976 struct {
977 u32 clock_source;
978 u32 locked;
979 u32 rate;
980 u32 adat_user_data;
981 } ext_sync;
982 } buf;
983 unsigned int quadlets, stream, i;
984
985 if (dice_proc_read_mem(dice, sections, 0, ARRAY_SIZE(sections)) < 0)
986 return;
987 snd_iprintf(buffer, "sections:\n");
988 for (i = 0; i < ARRAY_SIZE(section_names); ++i)
989 snd_iprintf(buffer, " %s: offset %u, size %u\n",
990 section_names[i],
991 sections[i * 2], sections[i * 2 + 1]);
992
993 quadlets = min_t(u32, sections[1], sizeof(buf.global) / 4);
994 if (dice_proc_read_mem(dice, &buf.global, sections[0], quadlets) < 0)
995 return;
996 snd_iprintf(buffer, "global:\n");
997 snd_iprintf(buffer, " owner: %04x:%04x%08x\n",
998 buf.global.owner_hi >> 16,
999 buf.global.owner_hi & 0xffff, buf.global.owner_lo);
1000 snd_iprintf(buffer, " notification: %08x\n", buf.global.notification);
1001 dice_proc_fixup_string(buf.global.nick_name, NICK_NAME_SIZE);
1002 snd_iprintf(buffer, " nick name: %s\n", buf.global.nick_name);
1003 snd_iprintf(buffer, " clock select: %s %s\n",
1004 str_from_array(clock_sources, ARRAY_SIZE(clock_sources),
1005 buf.global.clock_select & CLOCK_SOURCE_MASK),
1006 str_from_array(rates, ARRAY_SIZE(rates),
1007 (buf.global.clock_select & CLOCK_RATE_MASK)
1008 >> CLOCK_RATE_SHIFT));
1009 snd_iprintf(buffer, " enable: %u\n", buf.global.enable);
1010 snd_iprintf(buffer, " status: %slocked %s\n",
1011 buf.global.status & STATUS_SOURCE_LOCKED ? "" : "un",
1012 str_from_array(rates, ARRAY_SIZE(rates),
1013 (buf.global.status &
1014 STATUS_NOMINAL_RATE_MASK)
1015 >> CLOCK_RATE_SHIFT));
1016 snd_iprintf(buffer, " ext status: %08x\n", buf.global.extended_status);
1017 snd_iprintf(buffer, " sample rate: %u\n", buf.global.sample_rate);
1018 snd_iprintf(buffer, " version: %u.%u.%u.%u\n",
1019 (buf.global.version >> 24) & 0xff,
1020 (buf.global.version >> 16) & 0xff,
1021 (buf.global.version >> 8) & 0xff,
1022 (buf.global.version >> 0) & 0xff);
1023 if (quadlets >= 90) {
1024 snd_iprintf(buffer, " clock caps:");
1025 for (i = 0; i <= 6; ++i)
1026 if (buf.global.clock_caps & (1 << i))
1027 snd_iprintf(buffer, " %s", rates[i]);
1028 for (i = 0; i <= 12; ++i)
1029 if (buf.global.clock_caps & (1 << (16 + i)))
1030 snd_iprintf(buffer, " %s", clock_sources[i]);
1031 snd_iprintf(buffer, "\n");
1032 dice_proc_fixup_string(buf.global.clock_source_names,
1033 CLOCK_SOURCE_NAMES_SIZE);
1034 snd_iprintf(buffer, " clock source names: %s\n",
1035 buf.global.clock_source_names);
1036 }
1037
1038 if (dice_proc_read_mem(dice, &tx_rx_header, sections[2], 2) < 0)
1039 return;
1040 quadlets = min_t(u32, tx_rx_header.size, sizeof(buf.tx) / 4);
1041 for (stream = 0; stream < tx_rx_header.number; ++stream) {
1042 if (dice_proc_read_mem(dice, &buf.tx, sections[2] + 2 +
1043 stream * tx_rx_header.size,
1044 quadlets) < 0)
1045 break;
1046 snd_iprintf(buffer, "tx %u:\n", stream);
1047 snd_iprintf(buffer, " iso channel: %d\n", (int)buf.tx.iso);
1048 snd_iprintf(buffer, " audio channels: %u\n",
1049 buf.tx.number_audio);
1050 snd_iprintf(buffer, " midi ports: %u\n", buf.tx.number_midi);
1051 snd_iprintf(buffer, " speed: S%u\n", 100u << buf.tx.speed);
1052 if (quadlets >= 68) {
1053 dice_proc_fixup_string(buf.tx.names, TX_NAMES_SIZE);
1054 snd_iprintf(buffer, " names: %s\n", buf.tx.names);
1055 }
1056 if (quadlets >= 70) {
1057 snd_iprintf(buffer, " ac3 caps: %08x\n",
1058 buf.tx.ac3_caps);
1059 snd_iprintf(buffer, " ac3 enable: %08x\n",
1060 buf.tx.ac3_enable);
1061 }
1062 }
1063
1064 if (dice_proc_read_mem(dice, &tx_rx_header, sections[4], 2) < 0)
1065 return;
1066 quadlets = min_t(u32, tx_rx_header.size, sizeof(buf.rx) / 4);
1067 for (stream = 0; stream < tx_rx_header.number; ++stream) {
1068 if (dice_proc_read_mem(dice, &buf.rx, sections[4] + 2 +
1069 stream * tx_rx_header.size,
1070 quadlets) < 0)
1071 break;
1072 snd_iprintf(buffer, "rx %u:\n", stream);
1073 snd_iprintf(buffer, " iso channel: %d\n", (int)buf.rx.iso);
1074 snd_iprintf(buffer, " sequence start: %u\n", buf.rx.seq_start);
1075 snd_iprintf(buffer, " audio channels: %u\n",
1076 buf.rx.number_audio);
1077 snd_iprintf(buffer, " midi ports: %u\n", buf.rx.number_midi);
1078 if (quadlets >= 68) {
1079 dice_proc_fixup_string(buf.rx.names, RX_NAMES_SIZE);
1080 snd_iprintf(buffer, " names: %s\n", buf.rx.names);
1081 }
1082 if (quadlets >= 70) {
1083 snd_iprintf(buffer, " ac3 caps: %08x\n",
1084 buf.rx.ac3_caps);
1085 snd_iprintf(buffer, " ac3 enable: %08x\n",
1086 buf.rx.ac3_enable);
1087 }
1088 }
1089
1090 quadlets = min_t(u32, sections[7], sizeof(buf.ext_sync) / 4);
1091 if (quadlets >= 4) {
1092 if (dice_proc_read_mem(dice, &buf.ext_sync,
1093 sections[6], 4) < 0)
1094 return;
1095 snd_iprintf(buffer, "ext status:\n");
1096 snd_iprintf(buffer, " clock source: %s\n",
1097 str_from_array(clock_sources,
1098 ARRAY_SIZE(clock_sources),
1099 buf.ext_sync.clock_source));
1100 snd_iprintf(buffer, " locked: %u\n", buf.ext_sync.locked);
1101 snd_iprintf(buffer, " rate: %s\n",
1102 str_from_array(rates, ARRAY_SIZE(rates),
1103 buf.ext_sync.rate));
1104 snd_iprintf(buffer, " adat user data: ");
1105 if (buf.ext_sync.adat_user_data & ADAT_USER_DATA_NO_DATA)
1106 snd_iprintf(buffer, "-\n");
1107 else
1108 snd_iprintf(buffer, "%x\n",
1109 buf.ext_sync.adat_user_data);
1110 }
1111}
1112
1113static void dice_create_proc(struct snd_dice *dice)
1114{
1115 struct snd_info_entry *entry;
1116
1117 if (!snd_card_proc_new(dice->card, "dice", &entry))
1118 snd_info_set_text_ops(entry, dice, dice_proc_read);
1119}
1120
1121static void dice_card_free(struct snd_card *card)
1122{
1123 struct snd_dice *dice = card->private_data;
1124
1125 amdtp_stream_destroy(&dice->rx_stream);
1126 fw_core_remove_address_handler(&dice->notification_handler);
1127 mutex_destroy(&dice->mutex);
1128}
1129
1130#define OUI_WEISS 0x001c6a
1131
1132#define DICE_CATEGORY_ID 0x04
1133#define WEISS_CATEGORY_ID 0x00
1134
1135static int dice_interface_check(struct fw_unit *unit)
1136{
1137 static const int min_values[10] = {
1138 10, 0x64 / 4,
1139 10, 0x18 / 4,
1140 10, 0x18 / 4,
1141 0, 0,
1142 0, 0,
1143 };
1144 struct fw_device *device = fw_parent_device(unit);
1145 struct fw_csr_iterator it;
1146 int key, value, vendor = -1, model = -1, err;
1147 unsigned int category, i;
1148 __be32 pointers[ARRAY_SIZE(min_values)];
1149 __be32 tx_data[4];
1150 __be32 version;
1151
1152 /*
1153 * Check that GUID and unit directory are constructed according to DICE
1154 * rules, i.e., that the specifier ID is the GUID's OUI, and that the
1155 * GUID chip ID consists of the 8-bit category ID, the 10-bit product
1156 * ID, and a 22-bit serial number.
1157 */
1158 fw_csr_iterator_init(&it, unit->directory);
1159 while (fw_csr_iterator_next(&it, &key, &value)) {
1160 switch (key) {
1161 case CSR_SPECIFIER_ID:
1162 vendor = value;
1163 break;
1164 case CSR_MODEL:
1165 model = value;
1166 break;
1167 }
1168 }
1169 if (vendor == OUI_WEISS)
1170 category = WEISS_CATEGORY_ID;
1171 else
1172 category = DICE_CATEGORY_ID;
1173 if (device->config_rom[3] != ((vendor << 8) | category) ||
1174 device->config_rom[4] >> 22 != model)
1175 return -ENODEV;
1176
1177 /*
1178 * Check that the sub address spaces exist and are located inside the
1179 * private address space. The minimum values are chosen so that all
1180 * minimally required registers are included.
1181 */
1182 err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
1183 DICE_PRIVATE_SPACE,
1184 pointers, sizeof(pointers), 0);
1185 if (err < 0)
1186 return -ENODEV;
1187 for (i = 0; i < ARRAY_SIZE(pointers); ++i) {
1188 value = be32_to_cpu(pointers[i]);
1189 if (value < min_values[i] || value >= 0x40000)
1190 return -ENODEV;
1191 }
1192
1193 /* We support playback only. Let capture devices be handled by FFADO. */
1194 err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
1195 DICE_PRIVATE_SPACE +
1196 be32_to_cpu(pointers[2]) * 4,
1197 tx_data, sizeof(tx_data), 0);
1198 if (err < 0 || (tx_data[0] && tx_data[3]))
1199 return -ENODEV;
1200
1201 /*
1202 * Check that the implemented DICE driver specification major version
1203 * number matches.
1204 */
1205 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
1206 DICE_PRIVATE_SPACE +
1207 be32_to_cpu(pointers[0]) * 4 + GLOBAL_VERSION,
1208 &version, 4, 0);
1209 if (err < 0)
1210 return -ENODEV;
1211 if ((version & cpu_to_be32(0xff000000)) != cpu_to_be32(0x01000000)) {
1212 dev_err(&unit->device,
1213 "unknown DICE version: 0x%08x\n", be32_to_cpu(version));
1214 return -ENODEV;
1215 }
1216
1217 return 0;
1218}
1219
1220static int highest_supported_mode_rate(struct snd_dice *dice, unsigned int mode)
1221{
1222 int i;
1223
1224 for (i = ARRAY_SIZE(dice_rates) - 1; i >= 0; --i)
1225 if ((dice->clock_caps & (1 << i)) &&
1226 rate_index_to_mode(i) == mode)
1227 return i;
1228
1229 return -1;
1230}
1231
1232static int dice_read_mode_params(struct snd_dice *dice, unsigned int mode)
1233{
1234 __be32 values[2];
1235 int rate_index, err;
1236
1237 rate_index = highest_supported_mode_rate(dice, mode);
1238 if (rate_index < 0) {
1239 dice->rx_channels[mode] = 0;
1240 dice->rx_midi_ports[mode] = 0;
1241 return 0;
1242 }
1243
1244 err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
1245 if (err < 0)
1246 return err;
1247
1248 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1249 rx_address(dice, RX_NUMBER_AUDIO),
1250 values, 2 * 4, 0);
1251 if (err < 0)
1252 return err;
1253
1254 dice->rx_channels[mode] = be32_to_cpu(values[0]);
1255 dice->rx_midi_ports[mode] = be32_to_cpu(values[1]);
1256
1257 return 0;
1258}
1259
1260static int dice_read_params(struct snd_dice *dice)
1261{
1262 __be32 pointers[6];
1263 __be32 value;
1264 int mode, err;
1265
1266 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1267 DICE_PRIVATE_SPACE,
1268 pointers, sizeof(pointers), 0);
1269 if (err < 0)
1270 return err;
1271
1272 dice->global_offset = be32_to_cpu(pointers[0]) * 4;
1273 dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
1274
1275 /* some very old firmwares don't tell about their clock support */
1276 if (be32_to_cpu(pointers[1]) * 4 >= GLOBAL_CLOCK_CAPABILITIES + 4) {
1277 err = snd_fw_transaction(
1278 dice->unit, TCODE_READ_QUADLET_REQUEST,
1279 global_address(dice, GLOBAL_CLOCK_CAPABILITIES),
1280 &value, 4, 0);
1281 if (err < 0)
1282 return err;
1283 dice->clock_caps = be32_to_cpu(value);
1284 } else {
1285 /* this should be supported by any device */
1286 dice->clock_caps = CLOCK_CAP_RATE_44100 |
1287 CLOCK_CAP_RATE_48000 |
1288 CLOCK_CAP_SOURCE_ARX1 |
1289 CLOCK_CAP_SOURCE_INTERNAL;
1290 }
1291
1292 for (mode = 2; mode >= 0; --mode) {
1293 err = dice_read_mode_params(dice, mode);
1294 if (err < 0)
1295 return err;
1296 }
1297
1298 return 0;
1299}
1300
1301static void dice_card_strings(struct snd_dice *dice)
1302{
1303 struct snd_card *card = dice->card;
1304 struct fw_device *dev = fw_parent_device(dice->unit);
1305 char vendor[32], model[32];
1306 unsigned int i;
1307 int err;
1308
1309 strcpy(card->driver, "DICE");
1310
1311 strcpy(card->shortname, "DICE");
1312 BUILD_BUG_ON(NICK_NAME_SIZE < sizeof(card->shortname));
1313 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
1314 global_address(dice, GLOBAL_NICK_NAME),
1315 card->shortname, sizeof(card->shortname), 0);
1316 if (err >= 0) {
1317 /* DICE strings are returned in "always-wrong" endianness */
1318 BUILD_BUG_ON(sizeof(card->shortname) % 4 != 0);
1319 for (i = 0; i < sizeof(card->shortname); i += 4)
1320 swab32s((u32 *)&card->shortname[i]);
1321 card->shortname[sizeof(card->shortname) - 1] = '\0';
1322 }
1323
1324 strcpy(vendor, "?");
1325 fw_csr_string(dev->config_rom + 5, CSR_VENDOR, vendor, sizeof(vendor));
1326 strcpy(model, "?");
1327 fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
1328 snprintf(card->longname, sizeof(card->longname),
1329 "%s %s (serial %u) at %s, S%d",
1330 vendor, model, dev->config_rom[4] & 0x3fffff,
1331 dev_name(&dice->unit->device), 100 << dev->max_speed);
1332
1333 strcpy(card->mixername, "DICE");
1334}
1335
1336static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
1337{
1338 struct snd_card *card;
1339 struct snd_dice *dice;
1340 __be32 clock_sel;
1341 int err;
1342
1343 err = dice_interface_check(unit);
1344 if (err < 0)
1345 return err;
1346
1347 err = snd_card_new(&unit->device, -1, NULL, THIS_MODULE,
1348 sizeof(*dice), &card);
1349 if (err < 0)
1350 return err;
1351
1352 dice = card->private_data;
1353 dice->card = card;
1354 spin_lock_init(&dice->lock);
1355 mutex_init(&dice->mutex);
1356 dice->unit = unit;
1357 init_completion(&dice->clock_accepted);
1358 init_waitqueue_head(&dice->hwdep_wait);
1359
1360 dice->notification_handler.length = 4;
1361 dice->notification_handler.address_callback = dice_notification;
1362 dice->notification_handler.callback_data = dice;
1363 err = fw_core_add_address_handler(&dice->notification_handler,
1364 &fw_high_memory_region);
1365 if (err < 0)
1366 goto err_mutex;
1367
1368 err = dice_owner_set(dice);
1369 if (err < 0)
1370 goto err_notification_handler;
1371
1372 err = dice_read_params(dice);
1373 if (err < 0)
1374 goto err_owner;
1375
1376 err = fw_iso_resources_init(&dice->rx_resources, unit);
1377 if (err < 0)
1378 goto err_owner;
1379 dice->rx_resources.channels_mask = 0x00000000ffffffffuLL;
1380
1381 err = amdtp_stream_init(&dice->rx_stream, unit, AMDTP_OUT_STREAM,
1382 CIP_BLOCKING);
1383 if (err < 0)
1384 goto err_resources;
1385
1386 card->private_free = dice_card_free;
1387
1388 dice_card_strings(dice);
1389
1390 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
1391 global_address(dice, GLOBAL_CLOCK_SELECT),
1392 &clock_sel, 4, 0);
1393 if (err < 0)
1394 goto error;
1395 clock_sel &= cpu_to_be32(~CLOCK_SOURCE_MASK);
1396 clock_sel |= cpu_to_be32(CLOCK_SOURCE_ARX1);
1397 err = snd_fw_transaction(unit, TCODE_WRITE_QUADLET_REQUEST,
1398 global_address(dice, GLOBAL_CLOCK_SELECT),
1399 &clock_sel, 4, 0);
1400 if (err < 0)
1401 goto error;
1402
1403 err = dice_create_pcm(dice);
1404 if (err < 0)
1405 goto error;
1406
1407 err = dice_create_hwdep(dice);
1408 if (err < 0)
1409 goto error;
1410
1411 dice_create_proc(dice);
1412
1413 err = snd_card_register(card);
1414 if (err < 0)
1415 goto error;
1416
1417 dev_set_drvdata(&unit->device, dice);
1418
1419 return 0;
1420
1421err_resources:
1422 fw_iso_resources_destroy(&dice->rx_resources);
1423err_owner:
1424 dice_owner_clear(dice);
1425err_notification_handler:
1426 fw_core_remove_address_handler(&dice->notification_handler);
1427err_mutex:
1428 mutex_destroy(&dice->mutex);
1429error:
1430 snd_card_free(card);
1431 return err;
1432}
1433
1434static void dice_remove(struct fw_unit *unit)
1435{
1436 struct snd_dice *dice = dev_get_drvdata(&unit->device);
1437
1438 amdtp_stream_pcm_abort(&dice->rx_stream);
1439
1440 snd_card_disconnect(dice->card);
1441
1442 mutex_lock(&dice->mutex);
1443
1444 dice_stream_stop(dice);
1445 dice_owner_clear(dice);
1446
1447 mutex_unlock(&dice->mutex);
1448
1449 snd_card_free_when_closed(dice->card);
1450}
1451
1452static void dice_bus_reset(struct fw_unit *unit)
1453{
1454 struct snd_dice *dice = dev_get_drvdata(&unit->device);
1455
1456 /*
1457 * On a bus reset, the DICE firmware disables streaming and then goes
1458 * off contemplating its own navel for hundreds of milliseconds before
1459 * it can react to any of our attempts to reenable streaming. This
1460 * means that we lose synchronization anyway, so we force our streams
1461 * to stop so that the application can restart them in an orderly
1462 * manner.
1463 */
1464 amdtp_stream_pcm_abort(&dice->rx_stream);
1465
1466 mutex_lock(&dice->mutex);
1467
1468 dice->global_enabled = false;
1469 dice_stream_stop_packets(dice);
1470
1471 dice_owner_update(dice);
1472
1473 fw_iso_resources_update(&dice->rx_resources);
1474
1475 mutex_unlock(&dice->mutex);
1476}
1477
1478#define DICE_INTERFACE 0x000001
1479
1480static const struct ieee1394_device_id dice_id_table[] = {
1481 {
1482 .match_flags = IEEE1394_MATCH_VERSION,
1483 .version = DICE_INTERFACE,
1484 },
1485 { }
1486};
1487MODULE_DEVICE_TABLE(ieee1394, dice_id_table);
1488
1489static struct fw_driver dice_driver = {
1490 .driver = {
1491 .owner = THIS_MODULE,
1492 .name = KBUILD_MODNAME,
1493 .bus = &fw_bus_type,
1494 },
1495 .probe = dice_probe,
1496 .update = dice_bus_reset,
1497 .remove = dice_remove,
1498 .id_table = dice_id_table,
1499};
1500
1501static int __init alsa_dice_init(void)
1502{
1503 return driver_register(&dice_driver.driver);
1504}
1505
1506static void __exit alsa_dice_exit(void)
1507{
1508 driver_unregister(&dice_driver.driver);
1509}
1510
1511module_init(alsa_dice_init);
1512module_exit(alsa_dice_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 22:41:53 -0400