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-rw-r--r--include/linux/i2c/twl4030-madc.h4
-rw-r--r--include/linux/mfd/ab5500/ab5500.h140
-rw-r--r--include/linux/mfd/ab8500/gpadc.h5
-rw-r--r--include/linux/mfd/abx500.h54
-rw-r--r--include/linux/mfd/db5500-prcmu.h102
-rw-r--r--include/linux/mfd/db8500-prcmu.h368
-rw-r--r--include/linux/mfd/dbx500-prcmu.h549
-rw-r--r--include/linux/mfd/intel_msic.h456
-rw-r--r--include/linux/mfd/max8997-private.h1
-rw-r--r--include/linux/mfd/mc13783.h111
-rw-r--r--include/linux/mfd/mc13xxx.h38
-rw-r--r--include/linux/mfd/pcf50633/core.h3
-rw-r--r--include/linux/mfd/wm831x/core.h1
-rw-r--r--include/linux/mfd/wm8994/core.h2
-rw-r--r--include/linux/mfd/wm8994/pdata.h7
15 files changed, 1375 insertions, 466 deletions
diff --git a/include/linux/i2c/twl4030-madc.h b/include/linux/i2c/twl4030-madc.h
index 6427d298fbfc..530e11ba0738 100644
--- a/include/linux/i2c/twl4030-madc.h
+++ b/include/linux/i2c/twl4030-madc.h
@@ -129,6 +129,10 @@ enum sample_type {
129#define REG_BCICTL2 0x024 129#define REG_BCICTL2 0x024
130#define TWL4030_BCI_ITHSENS 0x007 130#define TWL4030_BCI_ITHSENS 0x007
131 131
132/* Register and bits for GPBR1 register */
133#define TWL4030_REG_GPBR1 0x0c
134#define TWL4030_GPBR1_MADC_HFCLK_EN (1 << 7)
135
132struct twl4030_madc_user_parms { 136struct twl4030_madc_user_parms {
133 int channel; 137 int channel;
134 int average; 138 int average;
diff --git a/include/linux/mfd/ab5500/ab5500.h b/include/linux/mfd/ab5500/ab5500.h
new file mode 100644
index 000000000000..a720051ae933
--- /dev/null
+++ b/include/linux/mfd/ab5500/ab5500.h
@@ -0,0 +1,140 @@
1/*
2 * Copyright (C) ST-Ericsson 2011
3 *
4 * License Terms: GNU General Public License v2
5 */
6#ifndef MFD_AB5500_H
7#define MFD_AB5500_H
8
9#include <linux/device.h>
10
11enum ab5500_devid {
12 AB5500_DEVID_ADC,
13 AB5500_DEVID_LEDS,
14 AB5500_DEVID_POWER,
15 AB5500_DEVID_REGULATORS,
16 AB5500_DEVID_SIM,
17 AB5500_DEVID_RTC,
18 AB5500_DEVID_CHARGER,
19 AB5500_DEVID_FUELGAUGE,
20 AB5500_DEVID_VIBRATOR,
21 AB5500_DEVID_CODEC,
22 AB5500_DEVID_USB,
23 AB5500_DEVID_OTP,
24 AB5500_DEVID_VIDEO,
25 AB5500_DEVID_DBIECI,
26 AB5500_DEVID_ONSWA,
27 AB5500_NUM_DEVICES,
28};
29
30enum ab5500_banks {
31 AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP = 0,
32 AB5500_BANK_VDDDIG_IO_I2C_CLK_TST = 1,
33 AB5500_BANK_VDENC = 2,
34 AB5500_BANK_SIM_USBSIM = 3,
35 AB5500_BANK_LED = 4,
36 AB5500_BANK_ADC = 5,
37 AB5500_BANK_RTC = 6,
38 AB5500_BANK_STARTUP = 7,
39 AB5500_BANK_DBI_ECI = 8,
40 AB5500_BANK_CHG = 9,
41 AB5500_BANK_FG_BATTCOM_ACC = 10,
42 AB5500_BANK_USB = 11,
43 AB5500_BANK_IT = 12,
44 AB5500_BANK_VIBRA = 13,
45 AB5500_BANK_AUDIO_HEADSETUSB = 14,
46 AB5500_NUM_BANKS = 15,
47};
48
49enum ab5500_banks_addr {
50 AB5500_ADDR_VIT_IO_I2C_CLK_TST_OTP = 0x4A,
51 AB5500_ADDR_VDDDIG_IO_I2C_CLK_TST = 0x4B,
52 AB5500_ADDR_VDENC = 0x06,
53 AB5500_ADDR_SIM_USBSIM = 0x04,
54 AB5500_ADDR_LED = 0x10,
55 AB5500_ADDR_ADC = 0x0A,
56 AB5500_ADDR_RTC = 0x0F,
57 AB5500_ADDR_STARTUP = 0x03,
58 AB5500_ADDR_DBI_ECI = 0x07,
59 AB5500_ADDR_CHG = 0x0B,
60 AB5500_ADDR_FG_BATTCOM_ACC = 0x0C,
61 AB5500_ADDR_USB = 0x05,
62 AB5500_ADDR_IT = 0x0E,
63 AB5500_ADDR_VIBRA = 0x02,
64 AB5500_ADDR_AUDIO_HEADSETUSB = 0x0D,
65};
66
67/*
68 * Interrupt register offsets
69 * Bank : 0x0E
70 */
71#define AB5500_IT_SOURCE0_REG 0x20
72#define AB5500_IT_SOURCE1_REG 0x21
73#define AB5500_IT_SOURCE2_REG 0x22
74#define AB5500_IT_SOURCE3_REG 0x23
75#define AB5500_IT_SOURCE4_REG 0x24
76#define AB5500_IT_SOURCE5_REG 0x25
77#define AB5500_IT_SOURCE6_REG 0x26
78#define AB5500_IT_SOURCE7_REG 0x27
79#define AB5500_IT_SOURCE8_REG 0x28
80#define AB5500_IT_SOURCE9_REG 0x29
81#define AB5500_IT_SOURCE10_REG 0x2A
82#define AB5500_IT_SOURCE11_REG 0x2B
83#define AB5500_IT_SOURCE12_REG 0x2C
84#define AB5500_IT_SOURCE13_REG 0x2D
85#define AB5500_IT_SOURCE14_REG 0x2E
86#define AB5500_IT_SOURCE15_REG 0x2F
87#define AB5500_IT_SOURCE16_REG 0x30
88#define AB5500_IT_SOURCE17_REG 0x31
89#define AB5500_IT_SOURCE18_REG 0x32
90#define AB5500_IT_SOURCE19_REG 0x33
91#define AB5500_IT_SOURCE20_REG 0x34
92#define AB5500_IT_SOURCE21_REG 0x35
93#define AB5500_IT_SOURCE22_REG 0x36
94#define AB5500_IT_SOURCE23_REG 0x37
95
96#define AB5500_NUM_IRQ_REGS 23
97
98/**
99 * struct ab5500
100 * @access_mutex: lock out concurrent accesses to the AB registers
101 * @dev: a pointer to the device struct for this chip driver
102 * @ab5500_irq: the analog baseband irq
103 * @irq_base: the platform configuration irq base for subdevices
104 * @chip_name: name of this chip variant
105 * @chip_id: 8 bit chip ID for this chip variant
106 * @irq_lock: a lock to protect the mask
107 * @abb_events: a local bit mask of the prcmu wakeup events
108 * @event_mask: a local copy of the mask event registers
109 * @last_event_mask: a copy of the last event_mask written to hardware
110 * @startup_events: a copy of the first reading of the event registers
111 * @startup_events_read: whether the first events have been read
112 */
113struct ab5500 {
114 struct mutex access_mutex;
115 struct device *dev;
116 unsigned int ab5500_irq;
117 unsigned int irq_base;
118 char chip_name[32];
119 u8 chip_id;
120 struct mutex irq_lock;
121 u32 abb_events;
122 u8 mask[AB5500_NUM_IRQ_REGS];
123 u8 oldmask[AB5500_NUM_IRQ_REGS];
124 u8 startup_events[AB5500_NUM_IRQ_REGS];
125 bool startup_events_read;
126#ifdef CONFIG_DEBUG_FS
127 unsigned int debug_bank;
128 unsigned int debug_address;
129#endif
130};
131
132struct ab5500_platform_data {
133 struct {unsigned int base; unsigned int count; } irq;
134 void *dev_data[AB5500_NUM_DEVICES];
135 struct abx500_init_settings *init_settings;
136 unsigned int init_settings_sz;
137 bool pm_power_off;
138};
139
140#endif /* MFD_AB5500_H */
diff --git a/include/linux/mfd/ab8500/gpadc.h b/include/linux/mfd/ab8500/gpadc.h
index 46b954011f16..252966769d93 100644
--- a/include/linux/mfd/ab8500/gpadc.h
+++ b/include/linux/mfd/ab8500/gpadc.h
@@ -27,6 +27,9 @@
27struct ab8500_gpadc; 27struct ab8500_gpadc;
28 28
29struct ab8500_gpadc *ab8500_gpadc_get(char *name); 29struct ab8500_gpadc *ab8500_gpadc_get(char *name);
30int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 input); 30int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 channel);
31int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel);
32int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc,
33 u8 channel, int ad_value);
31 34
32#endif /* _AB8500_GPADC_H */ 35#endif /* _AB8500_GPADC_H */
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index 896b5e47f16e..9970337ff041 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -6,7 +6,7 @@
6 * 6 *
7 * ABX500 core access functions. 7 * ABX500 core access functions.
8 * The abx500 interface is used for the Analog Baseband chip 8 * The abx500 interface is used for the Analog Baseband chip
9 * ab3100, ab3550, ab5500, and ab8500. 9 * ab3100, ab5500, and ab8500.
10 * 10 *
11 * Author: Mattias Wallin <mattias.wallin@stericsson.com> 11 * Author: Mattias Wallin <mattias.wallin@stericsson.com>
12 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 12 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
@@ -29,17 +29,16 @@
29#define AB3100_P1G 0xc6 29#define AB3100_P1G 0xc6
30#define AB3100_R2A 0xc7 30#define AB3100_R2A 0xc7
31#define AB3100_R2B 0xc8 31#define AB3100_R2B 0xc8
32#define AB3550_P1A 0x10
33#define AB5500_1_0 0x20 32#define AB5500_1_0 0x20
34#define AB5500_2_0 0x21 33#define AB5500_1_1 0x21
35#define AB5500_2_1 0x22 34#define AB5500_2_0 0x24
36 35
37/* AB8500 CIDs*/ 36/* AB8500 CIDs*/
38#define AB8500_CUTEARLY 0x00
39#define AB8500_CUT1P0 0x10 37#define AB8500_CUT1P0 0x10
40#define AB8500_CUT1P1 0x11 38#define AB8500_CUT1P1 0x11
41#define AB8500_CUT2P0 0x20 39#define AB8500_CUT2P0 0x20
42#define AB8500_CUT3P0 0x30 40#define AB8500_CUT3P0 0x30
41#define AB8500_CUT3P3 0x33
43 42
44/* 43/*
45 * AB3100, EVENTA1, A2 and A3 event register flags 44 * AB3100, EVENTA1, A2 and A3 event register flags
@@ -143,39 +142,6 @@ int ab3100_event_register(struct ab3100 *ab3100,
143int ab3100_event_unregister(struct ab3100 *ab3100, 142int ab3100_event_unregister(struct ab3100 *ab3100,
144 struct notifier_block *nb); 143 struct notifier_block *nb);
145 144
146/* AB3550, STR register flags */
147#define AB3550_STR_ONSWA (0x01)
148#define AB3550_STR_ONSWB (0x02)
149#define AB3550_STR_ONSWC (0x04)
150#define AB3550_STR_DCIO (0x08)
151#define AB3550_STR_BOOT_MODE (0x10)
152#define AB3550_STR_SIM_OFF (0x20)
153#define AB3550_STR_BATT_REMOVAL (0x40)
154#define AB3550_STR_VBUS (0x80)
155
156/* Interrupt mask registers */
157#define AB3550_IMR1 0x29
158#define AB3550_IMR2 0x2a
159#define AB3550_IMR3 0x2b
160#define AB3550_IMR4 0x2c
161#define AB3550_IMR5 0x2d
162
163enum ab3550_devid {
164 AB3550_DEVID_ADC,
165 AB3550_DEVID_DAC,
166 AB3550_DEVID_LEDS,
167 AB3550_DEVID_POWER,
168 AB3550_DEVID_REGULATORS,
169 AB3550_DEVID_SIM,
170 AB3550_DEVID_UART,
171 AB3550_DEVID_RTC,
172 AB3550_DEVID_CHARGER,
173 AB3550_DEVID_FUELGAUGE,
174 AB3550_DEVID_VIBRATOR,
175 AB3550_DEVID_CODEC,
176 AB3550_NUM_DEVICES,
177};
178
179/** 145/**
180 * struct abx500_init_setting 146 * struct abx500_init_setting
181 * Initial value of the registers for driver to use during setup. 147 * Initial value of the registers for driver to use during setup.
@@ -186,18 +152,6 @@ struct abx500_init_settings {
186 u8 setting; 152 u8 setting;
187}; 153};
188 154
189/**
190 * struct ab3550_platform_data
191 * Data supplied to initialize board connections to the AB3550
192 */
193struct ab3550_platform_data {
194 struct {unsigned int base; unsigned int count; } irq;
195 void *dev_data[AB3550_NUM_DEVICES];
196 size_t dev_data_sz[AB3550_NUM_DEVICES];
197 struct abx500_init_settings *init_settings;
198 unsigned int init_settings_sz;
199};
200
201int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg, 155int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
202 u8 value); 156 u8 value);
203int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg, 157int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,
diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h
index f0977986402c..9890687f582d 100644
--- a/include/linux/mfd/db5500-prcmu.h
+++ b/include/linux/mfd/db5500-prcmu.h
@@ -5,21 +5,35 @@
5 * 5 *
6 * U5500 PRCMU API. 6 * U5500 PRCMU API.
7 */ 7 */
8#ifndef __MACH_PRCMU_U5500_H 8#ifndef __MFD_DB5500_PRCMU_H
9#define __MACH_PRCMU_U5500_H 9#define __MFD_DB5500_PRCMU_H
10 10
11#ifdef CONFIG_UX500_SOC_DB5500 11#ifdef CONFIG_MFD_DB5500_PRCMU
12 12
13void db5500_prcmu_early_init(void); 13void db5500_prcmu_early_init(void);
14 14int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state);
15int db5500_prcmu_set_display_clocks(void);
16int db5500_prcmu_disable_dsipll(void);
17int db5500_prcmu_enable_dsipll(void);
15int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); 18int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
16int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); 19int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
20void db5500_prcmu_enable_wakeups(u32 wakeups);
21int db5500_prcmu_request_clock(u8 clock, bool enable);
22void db5500_prcmu_config_abb_event_readout(u32 abb_events);
23void db5500_prcmu_get_abb_event_buffer(void __iomem **buf);
24int prcmu_resetout(u8 resoutn, u8 state);
25int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
26 bool keep_ap_pll);
27int db5500_prcmu_config_esram0_deep_sleep(u8 state);
28void db5500_prcmu_system_reset(u16 reset_code);
29u16 db5500_prcmu_get_reset_code(void);
30bool db5500_prcmu_is_ac_wake_requested(void);
31int db5500_prcmu_set_arm_opp(u8 opp);
32int db5500_prcmu_get_arm_opp(void);
17 33
18#else /* !CONFIG_UX500_SOC_DB5500 */ 34#else /* !CONFIG_UX500_SOC_DB5500 */
19 35
20static inline void db5500_prcmu_early_init(void) 36static inline void db5500_prcmu_early_init(void) {}
21{
22}
23 37
24static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 38static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
25{ 39{
@@ -31,15 +45,75 @@ static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
31 return -ENOSYS; 45 return -ENOSYS;
32} 46}
33 47
34#endif /* CONFIG_UX500_SOC_DB5500 */ 48static inline int db5500_prcmu_request_clock(u8 clock, bool enable)
49{
50 return 0;
51}
52
53static inline int db5500_prcmu_set_display_clocks(void)
54{
55 return 0;
56}
57
58static inline int db5500_prcmu_disable_dsipll(void)
59{
60 return 0;
61}
62
63static inline int db5500_prcmu_enable_dsipll(void)
64{
65 return 0;
66}
35 67
36static inline int db5500_prcmu_config_abb_event_readout(u32 abb_events) 68static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state)
37{ 69{
38#ifdef CONFIG_MACH_U5500_SIMULATOR
39 return 0; 70 return 0;
40#else
41 return -1;
42#endif
43} 71}
44 72
45#endif /* __MACH_PRCMU_U5500_H */ 73static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {}
74
75static inline int prcmu_resetout(u8 resoutn, u8 state)
76{
77 return 0;
78}
79
80static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state)
81{
82 return 0;
83}
84
85static inline void db5500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
86static inline void db5500_prcmu_config_abb_event_readout(u32 abb_events) {}
87
88static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
89 bool keep_ap_pll)
90{
91 return 0;
92}
93
94static inline void db5500_prcmu_system_reset(u16 reset_code) {}
95
96static inline u16 db5500_prcmu_get_reset_code(void)
97{
98 return 0;
99}
100
101static inline bool db5500_prcmu_is_ac_wake_requested(void)
102{
103 return 0;
104}
105
106static inline int db5500_prcmu_set_arm_opp(u8 opp)
107{
108 return 0;
109}
110
111static inline int db5500_prcmu_get_arm_opp(void)
112{
113 return 0;
114}
115
116
117#endif /* CONFIG_MFD_DB5500_PRCMU */
118
119#endif /* __MFD_DB5500_PRCMU_H */
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index 917dbcab701c..60d27f7bfc1f 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -11,7 +11,6 @@
11#define __MFD_DB8500_PRCMU_H 11#define __MFD_DB8500_PRCMU_H
12 12
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14#include <linux/notifier.h>
15 14
16/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */ 15/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
17 16
@@ -133,7 +132,7 @@ enum ap_pwrst {
133 * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle 132 * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
134 */ 133 */
135enum ap_pwrst_trans { 134enum ap_pwrst_trans {
136 NO_TRANSITION = 0x00, 135 PRCMU_AP_NO_CHANGE = 0x00,
137 APEXECUTE_TO_APSLEEP = 0x01, 136 APEXECUTE_TO_APSLEEP = 0x01,
138 APIDLE_TO_APSLEEP = 0x02, /* To be removed */ 137 APIDLE_TO_APSLEEP = 0x02, /* To be removed */
139 PRCMU_AP_SLEEP = 0x01, 138 PRCMU_AP_SLEEP = 0x01,
@@ -146,54 +145,6 @@ enum ap_pwrst_trans {
146}; 145};
147 146
148/** 147/**
149 * enum ddr_pwrst - DDR power states definition
150 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
151 * @DDR_PWR_STATE_ON:
152 * @DDR_PWR_STATE_OFFLOWLAT:
153 * @DDR_PWR_STATE_OFFHIGHLAT:
154 */
155enum ddr_pwrst {
156 DDR_PWR_STATE_UNCHANGED = 0x00,
157 DDR_PWR_STATE_ON = 0x01,
158 DDR_PWR_STATE_OFFLOWLAT = 0x02,
159 DDR_PWR_STATE_OFFHIGHLAT = 0x03
160};
161
162/**
163 * enum arm_opp - ARM OPP states definition
164 * @ARM_OPP_INIT:
165 * @ARM_NO_CHANGE: The ARM operating point is unchanged
166 * @ARM_100_OPP: The new ARM operating point is arm100opp
167 * @ARM_50_OPP: The new ARM operating point is arm50opp
168 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
169 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
170 * @ARM_EXTCLK: The new ARM operating point is armExtClk
171 */
172enum arm_opp {
173 ARM_OPP_INIT = 0x00,
174 ARM_NO_CHANGE = 0x01,
175 ARM_100_OPP = 0x02,
176 ARM_50_OPP = 0x03,
177 ARM_MAX_OPP = 0x04,
178 ARM_MAX_FREQ100OPP = 0x05,
179 ARM_EXTCLK = 0x07
180};
181
182/**
183 * enum ape_opp - APE OPP states definition
184 * @APE_OPP_INIT:
185 * @APE_NO_CHANGE: The APE operating point is unchanged
186 * @APE_100_OPP: The new APE operating point is ape100opp
187 * @APE_50_OPP: 50%
188 */
189enum ape_opp {
190 APE_OPP_INIT = 0x00,
191 APE_NO_CHANGE = 0x01,
192 APE_100_OPP = 0x02,
193 APE_50_OPP = 0x03
194};
195
196/**
197 * enum hw_acc_state - State definition for hardware accelerator 148 * enum hw_acc_state - State definition for hardware accelerator
198 * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged 149 * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
199 * @HW_OFF: The hardware accelerator must be switched off 150 * @HW_OFF: The hardware accelerator must be switched off
@@ -469,26 +420,6 @@ enum auto_enable {
469 420
470/* End of file previously known as prcmu-fw-defs_v1.h */ 421/* End of file previously known as prcmu-fw-defs_v1.h */
471 422
472/* PRCMU Wakeup defines */
473enum prcmu_wakeup_index {
474 PRCMU_WAKEUP_INDEX_RTC,
475 PRCMU_WAKEUP_INDEX_RTT0,
476 PRCMU_WAKEUP_INDEX_RTT1,
477 PRCMU_WAKEUP_INDEX_HSI0,
478 PRCMU_WAKEUP_INDEX_HSI1,
479 PRCMU_WAKEUP_INDEX_USB,
480 PRCMU_WAKEUP_INDEX_ABB,
481 PRCMU_WAKEUP_INDEX_ABB_FIFO,
482 PRCMU_WAKEUP_INDEX_ARM,
483 NUM_PRCMU_WAKEUP_INDICES
484};
485#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
486
487/* PRCMU QoS APE OPP class */
488#define PRCMU_QOS_APE_OPP 1
489#define PRCMU_QOS_DDR_OPP 2
490#define PRCMU_QOS_DEFAULT_VALUE -1
491
492/** 423/**
493 * enum hw_acc_dev - enum for hw accelerators 424 * enum hw_acc_dev - enum for hw accelerators
494 * @HW_ACC_SVAMMDSP: for SVAMMDSP 425 * @HW_ACC_SVAMMDSP: for SVAMMDSP
@@ -527,64 +458,6 @@ enum hw_acc_dev {
527}; 458};
528 459
529/* 460/*
530 * Ids for all EPODs (power domains)
531 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
532 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
533 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
534 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
535 * - EPOD_ID_SGA: power domain for SGA
536 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
537 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
538 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
539 * - NUM_EPOD_ID: number of power domains
540 */
541#define EPOD_ID_SVAMMDSP 0
542#define EPOD_ID_SVAPIPE 1
543#define EPOD_ID_SIAMMDSP 2
544#define EPOD_ID_SIAPIPE 3
545#define EPOD_ID_SGA 4
546#define EPOD_ID_B2R2_MCDE 5
547#define EPOD_ID_ESRAM12 6
548#define EPOD_ID_ESRAM34 7
549#define NUM_EPOD_ID 8
550
551/*
552 * state definition for EPOD (power domain)
553 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
554 * - EPOD_STATE_OFF: The EPOD is switched off
555 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
556 * retention
557 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
558 * - EPOD_STATE_ON: Same as above, but with clock enabled
559 */
560#define EPOD_STATE_NO_CHANGE 0x00
561#define EPOD_STATE_OFF 0x01
562#define EPOD_STATE_RAMRET 0x02
563#define EPOD_STATE_ON_CLK_OFF 0x03
564#define EPOD_STATE_ON 0x04
565
566/*
567 * CLKOUT sources
568 */
569#define PRCMU_CLKSRC_CLK38M 0x00
570#define PRCMU_CLKSRC_ACLK 0x01
571#define PRCMU_CLKSRC_SYSCLK 0x02
572#define PRCMU_CLKSRC_LCDCLK 0x03
573#define PRCMU_CLKSRC_SDMMCCLK 0x04
574#define PRCMU_CLKSRC_TVCLK 0x05
575#define PRCMU_CLKSRC_TIMCLK 0x06
576#define PRCMU_CLKSRC_CLK009 0x07
577/* These are only valid for CLKOUT1: */
578#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
579#define PRCMU_CLKSRC_I2CCLK 0x41
580#define PRCMU_CLKSRC_MSP02CLK 0x42
581#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
582#define PRCMU_CLKSRC_HSIRXCLK 0x44
583#define PRCMU_CLKSRC_HSITXCLK 0x45
584#define PRCMU_CLKSRC_ARMCLKFIX 0x46
585#define PRCMU_CLKSRC_HDMICLK 0x47
586
587/*
588 * Definitions for autonomous power management configuration. 461 * Definitions for autonomous power management configuration.
589 */ 462 */
590 463
@@ -620,88 +493,12 @@ struct prcmu_auto_pm_config {
620 u8 sva_policy; 493 u8 sva_policy;
621}; 494};
622 495
623/**
624 * enum ddr_opp - DDR OPP states definition
625 * @DDR_100_OPP: The new DDR operating point is ddr100opp
626 * @DDR_50_OPP: The new DDR operating point is ddr50opp
627 * @DDR_25_OPP: The new DDR operating point is ddr25opp
628 */
629enum ddr_opp {
630 DDR_100_OPP = 0x00,
631 DDR_50_OPP = 0x01,
632 DDR_25_OPP = 0x02,
633};
634
635/*
636 * Clock identifiers.
637 */
638enum prcmu_clock {
639 PRCMU_SGACLK,
640 PRCMU_UARTCLK,
641 PRCMU_MSP02CLK,
642 PRCMU_MSP1CLK,
643 PRCMU_I2CCLK,
644 PRCMU_SDMMCCLK,
645 PRCMU_SLIMCLK,
646 PRCMU_PER1CLK,
647 PRCMU_PER2CLK,
648 PRCMU_PER3CLK,
649 PRCMU_PER5CLK,
650 PRCMU_PER6CLK,
651 PRCMU_PER7CLK,
652 PRCMU_LCDCLK,
653 PRCMU_BMLCLK,
654 PRCMU_HSITXCLK,
655 PRCMU_HSIRXCLK,
656 PRCMU_HDMICLK,
657 PRCMU_APEATCLK,
658 PRCMU_APETRACECLK,
659 PRCMU_MCDECLK,
660 PRCMU_IPI2CCLK,
661 PRCMU_DSIALTCLK,
662 PRCMU_DMACLK,
663 PRCMU_B2R2CLK,
664 PRCMU_TVCLK,
665 PRCMU_SSPCLK,
666 PRCMU_RNGCLK,
667 PRCMU_UICCCLK,
668 PRCMU_NUM_REG_CLOCKS,
669 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
670 PRCMU_TIMCLK,
671};
672
673/*
674 * Definitions for controlling ESRAM0 in deep sleep.
675 */
676#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
677#define ESRAM0_DEEP_SLEEP_STATE_RET 2
678
679#ifdef CONFIG_MFD_DB8500_PRCMU
680void __init prcmu_early_init(void);
681int prcmu_set_display_clocks(void);
682int prcmu_disable_dsipll(void);
683int prcmu_enable_dsipll(void);
684#else
685static inline void __init prcmu_early_init(void) {}
686#endif
687
688#ifdef CONFIG_MFD_DB8500_PRCMU 496#ifdef CONFIG_MFD_DB8500_PRCMU
689 497
498void db8500_prcmu_early_init(void);
690int prcmu_set_rc_a2p(enum romcode_write); 499int prcmu_set_rc_a2p(enum romcode_write);
691enum romcode_read prcmu_get_rc_p2a(void); 500enum romcode_read prcmu_get_rc_p2a(void);
692enum ap_pwrst prcmu_get_xp70_current_state(void); 501enum ap_pwrst prcmu_get_xp70_current_state(void);
693int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
694
695void prcmu_enable_wakeups(u32 wakeups);
696static inline void prcmu_disable_wakeups(void)
697{
698 prcmu_enable_wakeups(0);
699}
700
701void prcmu_config_abb_event_readout(u32 abb_events);
702void prcmu_get_abb_event_buffer(void __iomem **buf);
703int prcmu_set_arm_opp(u8 opp);
704int prcmu_get_arm_opp(void);
705bool prcmu_has_arm_maxopp(void); 502bool prcmu_has_arm_maxopp(void);
706bool prcmu_is_u8400(void); 503bool prcmu_is_u8400(void);
707int prcmu_set_ape_opp(u8 opp); 504int prcmu_set_ape_opp(u8 opp);
@@ -710,19 +507,14 @@ int prcmu_request_ape_opp_100_voltage(bool enable);
710int prcmu_release_usb_wakeup_state(void); 507int prcmu_release_usb_wakeup_state(void);
711int prcmu_set_ddr_opp(u8 opp); 508int prcmu_set_ddr_opp(u8 opp);
712int prcmu_get_ddr_opp(void); 509int prcmu_get_ddr_opp(void);
713unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
714void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
715/* NOTE! Use regulator framework instead */ 510/* NOTE! Use regulator framework instead */
716int prcmu_set_hwacc(u16 hw_acc_dev, u8 state); 511int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
717int prcmu_set_epod(u16 epod_id, u8 epod_state);
718void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 512void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
719 struct prcmu_auto_pm_config *idle); 513 struct prcmu_auto_pm_config *idle);
720bool prcmu_is_auto_pm_enabled(void); 514bool prcmu_is_auto_pm_enabled(void);
721 515
722int prcmu_config_clkout(u8 clkout, u8 source, u8 div); 516int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
723int prcmu_request_clock(u8 clock, bool enable);
724int prcmu_set_clock_divider(u8 clock, u8 divider); 517int prcmu_set_clock_divider(u8 clock, u8 divider);
725int prcmu_config_esram0_deep_sleep(u8 state);
726int prcmu_config_hotdog(u8 threshold); 518int prcmu_config_hotdog(u8 threshold);
727int prcmu_config_hotmon(u8 low, u8 high); 519int prcmu_config_hotmon(u8 low, u8 high);
728int prcmu_start_temp_sense(u16 cycles32k); 520int prcmu_start_temp_sense(u16 cycles32k);
@@ -732,14 +524,36 @@ int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
732 524
733void prcmu_ac_wake_req(void); 525void prcmu_ac_wake_req(void);
734void prcmu_ac_sleep_req(void); 526void prcmu_ac_sleep_req(void);
735void prcmu_system_reset(u16 reset_code);
736void prcmu_modem_reset(void); 527void prcmu_modem_reset(void);
737bool prcmu_is_ac_wake_requested(void);
738void prcmu_enable_spi2(void); 528void prcmu_enable_spi2(void);
739void prcmu_disable_spi2(void); 529void prcmu_disable_spi2(void);
740 530
531int prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
532int prcmu_enable_a9wdog(u8 id);
533int prcmu_disable_a9wdog(u8 id);
534int prcmu_kick_a9wdog(u8 id);
535int prcmu_load_a9wdog(u8 id, u32 val);
536
537void db8500_prcmu_system_reset(u16 reset_code);
538int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
539void db8500_prcmu_enable_wakeups(u32 wakeups);
540int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
541int db8500_prcmu_request_clock(u8 clock, bool enable);
542int db8500_prcmu_set_display_clocks(void);
543int db8500_prcmu_disable_dsipll(void);
544int db8500_prcmu_enable_dsipll(void);
545void db8500_prcmu_config_abb_event_readout(u32 abb_events);
546void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
547int db8500_prcmu_config_esram0_deep_sleep(u8 state);
548u16 db8500_prcmu_get_reset_code(void);
549bool db8500_prcmu_is_ac_wake_requested(void);
550int db8500_prcmu_set_arm_opp(u8 opp);
551int db8500_prcmu_get_arm_opp(void);
552
741#else /* !CONFIG_MFD_DB8500_PRCMU */ 553#else /* !CONFIG_MFD_DB8500_PRCMU */
742 554
555static inline void db8500_prcmu_early_init(void) {}
556
743static inline int prcmu_set_rc_a2p(enum romcode_write code) 557static inline int prcmu_set_rc_a2p(enum romcode_write code)
744{ 558{
745 return 0; 559 return 0;
@@ -755,34 +569,12 @@ static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
755 return AP_EXECUTE; 569 return AP_EXECUTE;
756} 570}
757 571
758static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 572static inline bool prcmu_has_arm_maxopp(void)
759 bool keep_ap_pll)
760{
761 return 0;
762}
763
764static inline void prcmu_enable_wakeups(u32 wakeups) {}
765
766static inline void prcmu_disable_wakeups(void) {}
767
768static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
769
770static inline int prcmu_set_arm_opp(u8 opp)
771{
772 return 0;
773}
774
775static inline int prcmu_get_arm_opp(void)
776{
777 return ARM_100_OPP;
778}
779
780static bool prcmu_has_arm_maxopp(void)
781{ 573{
782 return false; 574 return false;
783} 575}
784 576
785static bool prcmu_is_u8400(void) 577static inline bool prcmu_is_u8400(void)
786{ 578{
787 return false; 579 return false;
788} 580}
@@ -817,13 +609,6 @@ static inline int prcmu_get_ddr_opp(void)
817 return DDR_100_OPP; 609 return DDR_100_OPP;
818} 610}
819 611
820static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
821{
822 return 0;
823}
824
825static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
826
827static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state) 612static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
828{ 613{
829 return 0; 614 return 0;
@@ -844,21 +629,11 @@ static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
844 return 0; 629 return 0;
845} 630}
846 631
847static inline int prcmu_request_clock(u8 clock, bool enable)
848{
849 return 0;
850}
851
852static inline int prcmu_set_clock_divider(u8 clock, u8 divider) 632static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
853{ 633{
854 return 0; 634 return 0;
855} 635}
856 636
857int prcmu_config_esram0_deep_sleep(u8 state)
858{
859 return 0;
860}
861
862static inline int prcmu_config_hotdog(u8 threshold) 637static inline int prcmu_config_hotdog(u8 threshold)
863{ 638{
864 return 0; 639 return 0;
@@ -893,86 +668,107 @@ static inline void prcmu_ac_wake_req(void) {}
893 668
894static inline void prcmu_ac_sleep_req(void) {} 669static inline void prcmu_ac_sleep_req(void) {}
895 670
896static inline void prcmu_system_reset(u16 reset_code) {}
897
898static inline void prcmu_modem_reset(void) {} 671static inline void prcmu_modem_reset(void) {}
899 672
900static inline bool prcmu_is_ac_wake_requested(void) 673static inline int prcmu_enable_spi2(void)
901{ 674{
902 return false; 675 return 0;
903} 676}
904 677
905#ifndef CONFIG_UX500_SOC_DB5500 678static inline int prcmu_disable_spi2(void)
906static inline int prcmu_set_display_clocks(void)
907{ 679{
908 return 0; 680 return 0;
909} 681}
910 682
911static inline int prcmu_disable_dsipll(void) 683static inline void db8500_prcmu_system_reset(u16 reset_code) {}
684
685static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
686 bool keep_ap_pll)
912{ 687{
913 return 0; 688 return 0;
914} 689}
915 690
916static inline int prcmu_enable_dsipll(void) 691static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
692
693static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
917{ 694{
918 return 0; 695 return 0;
919} 696}
920#endif
921 697
922static inline int prcmu_enable_spi2(void) 698static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
923{ 699{
924 return 0; 700 return 0;
925} 701}
926 702
927static inline int prcmu_disable_spi2(void) 703static inline int db8500_prcmu_set_display_clocks(void)
928{ 704{
929 return 0; 705 return 0;
930} 706}
931 707
932#endif /* !CONFIG_MFD_DB8500_PRCMU */ 708static inline int db8500_prcmu_disable_dsipll(void)
709{
710 return 0;
711}
712
713static inline int db8500_prcmu_enable_dsipll(void)
714{
715 return 0;
716}
717
718static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
719{
720 return 0;
721}
722
723static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
933 724
934#ifdef CONFIG_UX500_PRCMU_QOS_POWER 725static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
935int prcmu_qos_requirement(int pm_qos_class); 726
936int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value); 727static inline u16 db8500_prcmu_get_reset_code(void)
937int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
938void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
939int prcmu_qos_add_notifier(int prcmu_qos_class,
940 struct notifier_block *notifier);
941int prcmu_qos_remove_notifier(int prcmu_qos_class,
942 struct notifier_block *notifier);
943#else
944static inline int prcmu_qos_requirement(int prcmu_qos_class)
945{ 728{
946 return 0; 729 return 0;
947} 730}
948 731
949static inline int prcmu_qos_add_requirement(int prcmu_qos_class, 732static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
950 char *name, s32 value)
951{ 733{
952 return 0; 734 return 0;
953} 735}
954 736
955static inline int prcmu_qos_update_requirement(int prcmu_qos_class, 737static inline int prcmu_enable_a9wdog(u8 id)
956 char *name, s32 new_value)
957{ 738{
958 return 0; 739 return 0;
959} 740}
960 741
961static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name) 742static inline int prcmu_disable_a9wdog(u8 id)
962{ 743{
744 return 0;
963} 745}
964 746
965static inline int prcmu_qos_add_notifier(int prcmu_qos_class, 747static inline int prcmu_kick_a9wdog(u8 id)
966 struct notifier_block *notifier)
967{ 748{
968 return 0; 749 return 0;
969} 750}
970static inline int prcmu_qos_remove_notifier(int prcmu_qos_class, 751
971 struct notifier_block *notifier) 752static inline int prcmu_load_a9wdog(u8 id, u32 val)
972{ 753{
973 return 0; 754 return 0;
974} 755}
975 756
976#endif 757static inline bool db8500_prcmu_is_ac_wake_requested(void)
758{
759 return 0;
760}
761
762static inline int db8500_prcmu_set_arm_opp(u8 opp)
763{
764 return 0;
765}
766
767static inline int db8500_prcmu_get_arm_opp(void)
768{
769 return 0;
770}
771
772#endif /* !CONFIG_MFD_DB8500_PRCMU */
977 773
978#endif /* __MFD_DB8500_PRCMU_H */ 774#endif /* __MFD_DB8500_PRCMU_H */
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
new file mode 100644
index 000000000000..bac942f959c1
--- /dev/null
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -0,0 +1,549 @@
1/*
2 * Copyright (C) ST Ericsson SA 2011
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * STE Ux500 PRCMU API
7 */
8#ifndef __MACH_PRCMU_H
9#define __MACH_PRCMU_H
10
11#include <linux/interrupt.h>
12#include <linux/notifier.h>
13#include <asm/mach-types.h>
14
15/* PRCMU Wakeup defines */
16enum prcmu_wakeup_index {
17 PRCMU_WAKEUP_INDEX_RTC,
18 PRCMU_WAKEUP_INDEX_RTT0,
19 PRCMU_WAKEUP_INDEX_RTT1,
20 PRCMU_WAKEUP_INDEX_HSI0,
21 PRCMU_WAKEUP_INDEX_HSI1,
22 PRCMU_WAKEUP_INDEX_USB,
23 PRCMU_WAKEUP_INDEX_ABB,
24 PRCMU_WAKEUP_INDEX_ABB_FIFO,
25 PRCMU_WAKEUP_INDEX_ARM,
26 PRCMU_WAKEUP_INDEX_CD_IRQ,
27 NUM_PRCMU_WAKEUP_INDICES
28};
29#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
30
31/* EPOD (power domain) IDs */
32
33/*
34 * DB8500 EPODs
35 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
36 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
37 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
38 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
39 * - EPOD_ID_SGA: power domain for SGA
40 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
41 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
42 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
43 * - NUM_EPOD_ID: number of power domains
44 *
45 * TODO: These should be prefixed.
46 */
47#define EPOD_ID_SVAMMDSP 0
48#define EPOD_ID_SVAPIPE 1
49#define EPOD_ID_SIAMMDSP 2
50#define EPOD_ID_SIAPIPE 3
51#define EPOD_ID_SGA 4
52#define EPOD_ID_B2R2_MCDE 5
53#define EPOD_ID_ESRAM12 6
54#define EPOD_ID_ESRAM34 7
55#define NUM_EPOD_ID 8
56
57/*
58 * DB5500 EPODs
59 */
60#define DB5500_EPOD_ID_BASE 0x0100
61#define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0)
62#define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1)
63#define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2)
64#define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3)
65#define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6)
66#define DB5500_NUM_EPOD_ID 7
67
68/*
69 * state definition for EPOD (power domain)
70 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
71 * - EPOD_STATE_OFF: The EPOD is switched off
72 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
73 * retention
74 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
75 * - EPOD_STATE_ON: Same as above, but with clock enabled
76 */
77#define EPOD_STATE_NO_CHANGE 0x00
78#define EPOD_STATE_OFF 0x01
79#define EPOD_STATE_RAMRET 0x02
80#define EPOD_STATE_ON_CLK_OFF 0x03
81#define EPOD_STATE_ON 0x04
82
83/*
84 * CLKOUT sources
85 */
86#define PRCMU_CLKSRC_CLK38M 0x00
87#define PRCMU_CLKSRC_ACLK 0x01
88#define PRCMU_CLKSRC_SYSCLK 0x02
89#define PRCMU_CLKSRC_LCDCLK 0x03
90#define PRCMU_CLKSRC_SDMMCCLK 0x04
91#define PRCMU_CLKSRC_TVCLK 0x05
92#define PRCMU_CLKSRC_TIMCLK 0x06
93#define PRCMU_CLKSRC_CLK009 0x07
94/* These are only valid for CLKOUT1: */
95#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
96#define PRCMU_CLKSRC_I2CCLK 0x41
97#define PRCMU_CLKSRC_MSP02CLK 0x42
98#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
99#define PRCMU_CLKSRC_HSIRXCLK 0x44
100#define PRCMU_CLKSRC_HSITXCLK 0x45
101#define PRCMU_CLKSRC_ARMCLKFIX 0x46
102#define PRCMU_CLKSRC_HDMICLK 0x47
103
104/*
105 * Clock identifiers.
106 */
107enum prcmu_clock {
108 PRCMU_SGACLK,
109 PRCMU_UARTCLK,
110 PRCMU_MSP02CLK,
111 PRCMU_MSP1CLK,
112 PRCMU_I2CCLK,
113 PRCMU_SDMMCCLK,
114 PRCMU_SLIMCLK,
115 PRCMU_PER1CLK,
116 PRCMU_PER2CLK,
117 PRCMU_PER3CLK,
118 PRCMU_PER5CLK,
119 PRCMU_PER6CLK,
120 PRCMU_PER7CLK,
121 PRCMU_LCDCLK,
122 PRCMU_BMLCLK,
123 PRCMU_HSITXCLK,
124 PRCMU_HSIRXCLK,
125 PRCMU_HDMICLK,
126 PRCMU_APEATCLK,
127 PRCMU_APETRACECLK,
128 PRCMU_MCDECLK,
129 PRCMU_IPI2CCLK,
130 PRCMU_DSIALTCLK,
131 PRCMU_DMACLK,
132 PRCMU_B2R2CLK,
133 PRCMU_TVCLK,
134 PRCMU_SSPCLK,
135 PRCMU_RNGCLK,
136 PRCMU_UICCCLK,
137 PRCMU_PWMCLK,
138 PRCMU_IRDACLK,
139 PRCMU_IRRCCLK,
140 PRCMU_SIACLK,
141 PRCMU_SVACLK,
142 PRCMU_NUM_REG_CLOCKS,
143 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
144 PRCMU_TIMCLK,
145 PRCMU_PLLSOC0,
146 PRCMU_PLLSOC1,
147 PRCMU_PLLDDR,
148};
149
150/**
151 * enum ape_opp - APE OPP states definition
152 * @APE_OPP_INIT:
153 * @APE_NO_CHANGE: The APE operating point is unchanged
154 * @APE_100_OPP: The new APE operating point is ape100opp
155 * @APE_50_OPP: 50%
156 */
157enum ape_opp {
158 APE_OPP_INIT = 0x00,
159 APE_NO_CHANGE = 0x01,
160 APE_100_OPP = 0x02,
161 APE_50_OPP = 0x03
162};
163
164/**
165 * enum arm_opp - ARM OPP states definition
166 * @ARM_OPP_INIT:
167 * @ARM_NO_CHANGE: The ARM operating point is unchanged
168 * @ARM_100_OPP: The new ARM operating point is arm100opp
169 * @ARM_50_OPP: The new ARM operating point is arm50opp
170 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
171 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
172 * @ARM_EXTCLK: The new ARM operating point is armExtClk
173 */
174enum arm_opp {
175 ARM_OPP_INIT = 0x00,
176 ARM_NO_CHANGE = 0x01,
177 ARM_100_OPP = 0x02,
178 ARM_50_OPP = 0x03,
179 ARM_MAX_OPP = 0x04,
180 ARM_MAX_FREQ100OPP = 0x05,
181 ARM_EXTCLK = 0x07
182};
183
184/**
185 * enum ddr_opp - DDR OPP states definition
186 * @DDR_100_OPP: The new DDR operating point is ddr100opp
187 * @DDR_50_OPP: The new DDR operating point is ddr50opp
188 * @DDR_25_OPP: The new DDR operating point is ddr25opp
189 */
190enum ddr_opp {
191 DDR_100_OPP = 0x00,
192 DDR_50_OPP = 0x01,
193 DDR_25_OPP = 0x02,
194};
195
196/*
197 * Definitions for controlling ESRAM0 in deep sleep.
198 */
199#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
200#define ESRAM0_DEEP_SLEEP_STATE_RET 2
201
202/**
203 * enum ddr_pwrst - DDR power states definition
204 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
205 * @DDR_PWR_STATE_ON:
206 * @DDR_PWR_STATE_OFFLOWLAT:
207 * @DDR_PWR_STATE_OFFHIGHLAT:
208 */
209enum ddr_pwrst {
210 DDR_PWR_STATE_UNCHANGED = 0x00,
211 DDR_PWR_STATE_ON = 0x01,
212 DDR_PWR_STATE_OFFLOWLAT = 0x02,
213 DDR_PWR_STATE_OFFHIGHLAT = 0x03
214};
215
216#include <linux/mfd/db8500-prcmu.h>
217#include <linux/mfd/db5500-prcmu.h>
218
219#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
220
221static inline void __init prcmu_early_init(void)
222{
223 if (machine_is_u5500())
224 return db5500_prcmu_early_init();
225 else
226 return db8500_prcmu_early_init();
227}
228
229static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
230 bool keep_ap_pll)
231{
232 if (machine_is_u5500())
233 return db5500_prcmu_set_power_state(state, keep_ulp_clk,
234 keep_ap_pll);
235 else
236 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
237 keep_ap_pll);
238}
239
240static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
241{
242 if (machine_is_u5500())
243 return -EINVAL;
244 else
245 return db8500_prcmu_set_epod(epod_id, epod_state);
246}
247
248static inline void prcmu_enable_wakeups(u32 wakeups)
249{
250 if (machine_is_u5500())
251 db5500_prcmu_enable_wakeups(wakeups);
252 else
253 db8500_prcmu_enable_wakeups(wakeups);
254}
255
256static inline void prcmu_disable_wakeups(void)
257{
258 prcmu_enable_wakeups(0);
259}
260
261static inline void prcmu_config_abb_event_readout(u32 abb_events)
262{
263 if (machine_is_u5500())
264 db5500_prcmu_config_abb_event_readout(abb_events);
265 else
266 db8500_prcmu_config_abb_event_readout(abb_events);
267}
268
269static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
270{
271 if (machine_is_u5500())
272 db5500_prcmu_get_abb_event_buffer(buf);
273 else
274 db8500_prcmu_get_abb_event_buffer(buf);
275}
276
277int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
278int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
279
280int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
281
282static inline int prcmu_request_clock(u8 clock, bool enable)
283{
284 if (machine_is_u5500())
285 return db5500_prcmu_request_clock(clock, enable);
286 else
287 return db8500_prcmu_request_clock(clock, enable);
288}
289
290int prcmu_set_ape_opp(u8 opp);
291int prcmu_get_ape_opp(void);
292int prcmu_set_ddr_opp(u8 opp);
293int prcmu_get_ddr_opp(void);
294
295static inline int prcmu_set_arm_opp(u8 opp)
296{
297 if (machine_is_u5500())
298 return -EINVAL;
299 else
300 return db8500_prcmu_set_arm_opp(opp);
301}
302
303static inline int prcmu_get_arm_opp(void)
304{
305 if (machine_is_u5500())
306 return -EINVAL;
307 else
308 return db8500_prcmu_get_arm_opp();
309}
310
311static inline void prcmu_system_reset(u16 reset_code)
312{
313 if (machine_is_u5500())
314 return db5500_prcmu_system_reset(reset_code);
315 else
316 return db8500_prcmu_system_reset(reset_code);
317}
318
319static inline u16 prcmu_get_reset_code(void)
320{
321 if (machine_is_u5500())
322 return db5500_prcmu_get_reset_code();
323 else
324 return db8500_prcmu_get_reset_code();
325}
326
327void prcmu_ac_wake_req(void);
328void prcmu_ac_sleep_req(void);
329void prcmu_modem_reset(void);
330static inline bool prcmu_is_ac_wake_requested(void)
331{
332 if (machine_is_u5500())
333 return db5500_prcmu_is_ac_wake_requested();
334 else
335 return db8500_prcmu_is_ac_wake_requested();
336}
337
338static inline int prcmu_set_display_clocks(void)
339{
340 if (machine_is_u5500())
341 return db5500_prcmu_set_display_clocks();
342 else
343 return db8500_prcmu_set_display_clocks();
344}
345
346static inline int prcmu_disable_dsipll(void)
347{
348 if (machine_is_u5500())
349 return db5500_prcmu_disable_dsipll();
350 else
351 return db8500_prcmu_disable_dsipll();
352}
353
354static inline int prcmu_enable_dsipll(void)
355{
356 if (machine_is_u5500())
357 return db5500_prcmu_enable_dsipll();
358 else
359 return db8500_prcmu_enable_dsipll();
360}
361
362static inline int prcmu_config_esram0_deep_sleep(u8 state)
363{
364 if (machine_is_u5500())
365 return -EINVAL;
366 else
367 return db8500_prcmu_config_esram0_deep_sleep(state);
368}
369#else
370
371static inline void __init prcmu_early_init(void) {}
372
373static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
374 bool keep_ap_pll)
375{
376 return 0;
377}
378
379static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
380{
381 return 0;
382}
383
384static inline void prcmu_enable_wakeups(u32 wakeups) {}
385
386static inline void prcmu_disable_wakeups(void) {}
387
388static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
389{
390 return -ENOSYS;
391}
392
393static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
394{
395 return -ENOSYS;
396}
397
398static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
399{
400 return 0;
401}
402
403static inline int prcmu_request_clock(u8 clock, bool enable)
404{
405 return 0;
406}
407
408static inline int prcmu_set_ape_opp(u8 opp)
409{
410 return 0;
411}
412
413static inline int prcmu_get_ape_opp(void)
414{
415 return APE_100_OPP;
416}
417
418static inline int prcmu_set_arm_opp(u8 opp)
419{
420 return 0;
421}
422
423static inline int prcmu_get_arm_opp(void)
424{
425 return ARM_100_OPP;
426}
427
428static inline int prcmu_set_ddr_opp(u8 opp)
429{
430 return 0;
431}
432
433static inline int prcmu_get_ddr_opp(void)
434{
435 return DDR_100_OPP;
436}
437
438static inline void prcmu_system_reset(u16 reset_code) {}
439
440static inline u16 prcmu_get_reset_code(void)
441{
442 return 0;
443}
444
445static inline void prcmu_ac_wake_req(void) {}
446
447static inline void prcmu_ac_sleep_req(void) {}
448
449static inline void prcmu_modem_reset(void) {}
450
451static inline bool prcmu_is_ac_wake_requested(void)
452{
453 return false;
454}
455
456static inline int prcmu_set_display_clocks(void)
457{
458 return 0;
459}
460
461static inline int prcmu_disable_dsipll(void)
462{
463 return 0;
464}
465
466static inline int prcmu_enable_dsipll(void)
467{
468 return 0;
469}
470
471static inline int prcmu_config_esram0_deep_sleep(u8 state)
472{
473 return 0;
474}
475
476static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
477
478static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
479{
480 *buf = NULL;
481}
482
483#endif
484
485/* PRCMU QoS APE OPP class */
486#define PRCMU_QOS_APE_OPP 1
487#define PRCMU_QOS_DDR_OPP 2
488#define PRCMU_QOS_DEFAULT_VALUE -1
489
490#ifdef CONFIG_UX500_PRCMU_QOS_POWER
491
492unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
493void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
494void prcmu_qos_force_opp(int, s32);
495int prcmu_qos_requirement(int pm_qos_class);
496int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
497int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
498void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
499int prcmu_qos_add_notifier(int prcmu_qos_class,
500 struct notifier_block *notifier);
501int prcmu_qos_remove_notifier(int prcmu_qos_class,
502 struct notifier_block *notifier);
503
504#else
505
506static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
507{
508 return 0;
509}
510
511static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
512
513static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
514
515static inline int prcmu_qos_requirement(int prcmu_qos_class)
516{
517 return 0;
518}
519
520static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
521 char *name, s32 value)
522{
523 return 0;
524}
525
526static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
527 char *name, s32 new_value)
528{
529 return 0;
530}
531
532static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
533{
534}
535
536static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
537 struct notifier_block *notifier)
538{
539 return 0;
540}
541static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
542 struct notifier_block *notifier)
543{
544 return 0;
545}
546
547#endif
548
549#endif /* __MACH_PRCMU_H */
diff --git a/include/linux/mfd/intel_msic.h b/include/linux/mfd/intel_msic.h
new file mode 100644
index 000000000000..439a7a617bc9
--- /dev/null
+++ b/include/linux/mfd/intel_msic.h
@@ -0,0 +1,456 @@
1/*
2 * include/linux/mfd/intel_msic.h - Core interface for Intel MSIC
3 *
4 * Copyright (C) 2011, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __LINUX_MFD_INTEL_MSIC_H__
13#define __LINUX_MFD_INTEL_MSIC_H__
14
15/* ID */
16#define INTEL_MSIC_ID0 0x000 /* RO */
17#define INTEL_MSIC_ID1 0x001 /* RO */
18
19/* IRQ */
20#define INTEL_MSIC_IRQLVL1 0x002
21#define INTEL_MSIC_ADC1INT 0x003
22#define INTEL_MSIC_CCINT 0x004
23#define INTEL_MSIC_PWRSRCINT 0x005
24#define INTEL_MSIC_PWRSRCINT1 0x006
25#define INTEL_MSIC_CHRINT 0x007
26#define INTEL_MSIC_CHRINT1 0x008
27#define INTEL_MSIC_RTCIRQ 0x009
28#define INTEL_MSIC_GPIO0LVIRQ 0x00a
29#define INTEL_MSIC_GPIO1LVIRQ 0x00b
30#define INTEL_MSIC_GPIOHVIRQ 0x00c
31#define INTEL_MSIC_VRINT 0x00d
32#define INTEL_MSIC_OCAUDIO 0x00e
33#define INTEL_MSIC_ACCDET 0x00f
34#define INTEL_MSIC_RESETIRQ1 0x010
35#define INTEL_MSIC_RESETIRQ2 0x011
36#define INTEL_MSIC_MADC1INT 0x012
37#define INTEL_MSIC_MCCINT 0x013
38#define INTEL_MSIC_MPWRSRCINT 0x014
39#define INTEL_MSIC_MPWRSRCINT1 0x015
40#define INTEL_MSIC_MCHRINT 0x016
41#define INTEL_MSIC_MCHRINT1 0x017
42#define INTEL_MSIC_RTCIRQMASK 0x018
43#define INTEL_MSIC_GPIO0LVIRQMASK 0x019
44#define INTEL_MSIC_GPIO1LVIRQMASK 0x01a
45#define INTEL_MSIC_GPIOHVIRQMASK 0x01b
46#define INTEL_MSIC_VRINTMASK 0x01c
47#define INTEL_MSIC_OCAUDIOMASK 0x01d
48#define INTEL_MSIC_ACCDETMASK 0x01e
49#define INTEL_MSIC_RESETIRQ1MASK 0x01f
50#define INTEL_MSIC_RESETIRQ2MASK 0x020
51#define INTEL_MSIC_IRQLVL1MSK 0x021
52#define INTEL_MSIC_PBCONFIG 0x03e
53#define INTEL_MSIC_PBSTATUS 0x03f /* RO */
54
55/* GPIO */
56#define INTEL_MSIC_GPIO0LV7CTLO 0x040
57#define INTEL_MSIC_GPIO0LV6CTLO 0x041
58#define INTEL_MSIC_GPIO0LV5CTLO 0x042
59#define INTEL_MSIC_GPIO0LV4CTLO 0x043
60#define INTEL_MSIC_GPIO0LV3CTLO 0x044
61#define INTEL_MSIC_GPIO0LV2CTLO 0x045
62#define INTEL_MSIC_GPIO0LV1CTLO 0x046
63#define INTEL_MSIC_GPIO0LV0CTLO 0x047
64#define INTEL_MSIC_GPIO1LV7CTLOS 0x048
65#define INTEL_MSIC_GPIO1LV6CTLO 0x049
66#define INTEL_MSIC_GPIO1LV5CTLO 0x04a
67#define INTEL_MSIC_GPIO1LV4CTLO 0x04b
68#define INTEL_MSIC_GPIO1LV3CTLO 0x04c
69#define INTEL_MSIC_GPIO1LV2CTLO 0x04d
70#define INTEL_MSIC_GPIO1LV1CTLO 0x04e
71#define INTEL_MSIC_GPIO1LV0CTLO 0x04f
72#define INTEL_MSIC_GPIO0LV7CTLI 0x050
73#define INTEL_MSIC_GPIO0LV6CTLI 0x051
74#define INTEL_MSIC_GPIO0LV5CTLI 0x052
75#define INTEL_MSIC_GPIO0LV4CTLI 0x053
76#define INTEL_MSIC_GPIO0LV3CTLI 0x054
77#define INTEL_MSIC_GPIO0LV2CTLI 0x055
78#define INTEL_MSIC_GPIO0LV1CTLI 0x056
79#define INTEL_MSIC_GPIO0LV0CTLI 0x057
80#define INTEL_MSIC_GPIO1LV7CTLIS 0x058
81#define INTEL_MSIC_GPIO1LV6CTLI 0x059
82#define INTEL_MSIC_GPIO1LV5CTLI 0x05a
83#define INTEL_MSIC_GPIO1LV4CTLI 0x05b
84#define INTEL_MSIC_GPIO1LV3CTLI 0x05c
85#define INTEL_MSIC_GPIO1LV2CTLI 0x05d
86#define INTEL_MSIC_GPIO1LV1CTLI 0x05e
87#define INTEL_MSIC_GPIO1LV0CTLI 0x05f
88#define INTEL_MSIC_PWM0CLKDIV1 0x061
89#define INTEL_MSIC_PWM0CLKDIV0 0x062
90#define INTEL_MSIC_PWM1CLKDIV1 0x063
91#define INTEL_MSIC_PWM1CLKDIV0 0x064
92#define INTEL_MSIC_PWM2CLKDIV1 0x065
93#define INTEL_MSIC_PWM2CLKDIV0 0x066
94#define INTEL_MSIC_PWM0DUTYCYCLE 0x067
95#define INTEL_MSIC_PWM1DUTYCYCLE 0x068
96#define INTEL_MSIC_PWM2DUTYCYCLE 0x069
97#define INTEL_MSIC_GPIO0HV3CTLO 0x06d
98#define INTEL_MSIC_GPIO0HV2CTLO 0x06e
99#define INTEL_MSIC_GPIO0HV1CTLO 0x06f
100#define INTEL_MSIC_GPIO0HV0CTLO 0x070
101#define INTEL_MSIC_GPIO1HV3CTLO 0x071
102#define INTEL_MSIC_GPIO1HV2CTLO 0x072
103#define INTEL_MSIC_GPIO1HV1CTLO 0x073
104#define INTEL_MSIC_GPIO1HV0CTLO 0x074
105#define INTEL_MSIC_GPIO0HV3CTLI 0x075
106#define INTEL_MSIC_GPIO0HV2CTLI 0x076
107#define INTEL_MSIC_GPIO0HV1CTLI 0x077
108#define INTEL_MSIC_GPIO0HV0CTLI 0x078
109#define INTEL_MSIC_GPIO1HV3CTLI 0x079
110#define INTEL_MSIC_GPIO1HV2CTLI 0x07a
111#define INTEL_MSIC_GPIO1HV1CTLI 0x07b
112#define INTEL_MSIC_GPIO1HV0CTLI 0x07c
113
114/* SVID */
115#define INTEL_MSIC_SVIDCTRL0 0x080
116#define INTEL_MSIC_SVIDCTRL1 0x081
117#define INTEL_MSIC_SVIDCTRL2 0x082
118#define INTEL_MSIC_SVIDTXLASTPKT3 0x083 /* RO */
119#define INTEL_MSIC_SVIDTXLASTPKT2 0x084 /* RO */
120#define INTEL_MSIC_SVIDTXLASTPKT1 0x085 /* RO */
121#define INTEL_MSIC_SVIDTXLASTPKT0 0x086 /* RO */
122#define INTEL_MSIC_SVIDPKTOUTBYTE3 0x087
123#define INTEL_MSIC_SVIDPKTOUTBYTE2 0x088
124#define INTEL_MSIC_SVIDPKTOUTBYTE1 0x089
125#define INTEL_MSIC_SVIDPKTOUTBYTE0 0x08a
126#define INTEL_MSIC_SVIDRXVPDEBUG1 0x08b
127#define INTEL_MSIC_SVIDRXVPDEBUG0 0x08c
128#define INTEL_MSIC_SVIDRXLASTPKT3 0x08d /* RO */
129#define INTEL_MSIC_SVIDRXLASTPKT2 0x08e /* RO */
130#define INTEL_MSIC_SVIDRXLASTPKT1 0x08f /* RO */
131#define INTEL_MSIC_SVIDRXLASTPKT0 0x090 /* RO */
132#define INTEL_MSIC_SVIDRXCHKSTATUS3 0x091 /* RO */
133#define INTEL_MSIC_SVIDRXCHKSTATUS2 0x092 /* RO */
134#define INTEL_MSIC_SVIDRXCHKSTATUS1 0x093 /* RO */
135#define INTEL_MSIC_SVIDRXCHKSTATUS0 0x094 /* RO */
136
137/* VREG */
138#define INTEL_MSIC_VCCLATCH 0x0c0
139#define INTEL_MSIC_VNNLATCH 0x0c1
140#define INTEL_MSIC_VCCCNT 0x0c2
141#define INTEL_MSIC_SMPSRAMP 0x0c3
142#define INTEL_MSIC_VNNCNT 0x0c4
143#define INTEL_MSIC_VNNAONCNT 0x0c5
144#define INTEL_MSIC_VCC122AONCNT 0x0c6
145#define INTEL_MSIC_V180AONCNT 0x0c7
146#define INTEL_MSIC_V500CNT 0x0c8
147#define INTEL_MSIC_VIHFCNT 0x0c9
148#define INTEL_MSIC_LDORAMP1 0x0ca
149#define INTEL_MSIC_LDORAMP2 0x0cb
150#define INTEL_MSIC_VCC108AONCNT 0x0cc
151#define INTEL_MSIC_VCC108ASCNT 0x0cd
152#define INTEL_MSIC_VCC108CNT 0x0ce
153#define INTEL_MSIC_VCCA100ASCNT 0x0cf
154#define INTEL_MSIC_VCCA100CNT 0x0d0
155#define INTEL_MSIC_VCC180AONCNT 0x0d1
156#define INTEL_MSIC_VCC180CNT 0x0d2
157#define INTEL_MSIC_VCC330CNT 0x0d3
158#define INTEL_MSIC_VUSB330CNT 0x0d4
159#define INTEL_MSIC_VCCSDIOCNT 0x0d5
160#define INTEL_MSIC_VPROG1CNT 0x0d6
161#define INTEL_MSIC_VPROG2CNT 0x0d7
162#define INTEL_MSIC_VEMMCSCNT 0x0d8
163#define INTEL_MSIC_VEMMC1CNT 0x0d9
164#define INTEL_MSIC_VEMMC2CNT 0x0da
165#define INTEL_MSIC_VAUDACNT 0x0db
166#define INTEL_MSIC_VHSPCNT 0x0dc
167#define INTEL_MSIC_VHSNCNT 0x0dd
168#define INTEL_MSIC_VHDMICNT 0x0de
169#define INTEL_MSIC_VOTGCNT 0x0df
170#define INTEL_MSIC_V1P35CNT 0x0e0
171#define INTEL_MSIC_V330AONCNT 0x0e1
172
173/* RESET */
174#define INTEL_MSIC_CHIPCNTRL 0x100 /* WO */
175#define INTEL_MSIC_ERCONFIG 0x101
176
177/* BURST */
178#define INTEL_MSIC_BATCURRENTLIMIT12 0x102
179#define INTEL_MSIC_BATTIMELIMIT12 0x103
180#define INTEL_MSIC_BATTIMELIMIT3 0x104
181#define INTEL_MSIC_BATTIMEDB 0x105
182#define INTEL_MSIC_BRSTCONFIGOUTPUTS 0x106
183#define INTEL_MSIC_BRSTCONFIGACTIONS 0x107
184#define INTEL_MSIC_BURSTCONTROLSTATUS 0x108
185
186/* RTC */
187#define INTEL_MSIC_RTCB1 0x140 /* RO */
188#define INTEL_MSIC_RTCB2 0x141 /* RO */
189#define INTEL_MSIC_RTCB3 0x142 /* RO */
190#define INTEL_MSIC_RTCB4 0x143 /* RO */
191#define INTEL_MSIC_RTCOB1 0x144
192#define INTEL_MSIC_RTCOB2 0x145
193#define INTEL_MSIC_RTCOB3 0x146
194#define INTEL_MSIC_RTCOB4 0x147
195#define INTEL_MSIC_RTCAB1 0x148
196#define INTEL_MSIC_RTCAB2 0x149
197#define INTEL_MSIC_RTCAB3 0x14a
198#define INTEL_MSIC_RTCAB4 0x14b
199#define INTEL_MSIC_RTCWAB1 0x14c
200#define INTEL_MSIC_RTCWAB2 0x14d
201#define INTEL_MSIC_RTCWAB3 0x14e
202#define INTEL_MSIC_RTCWAB4 0x14f
203#define INTEL_MSIC_RTCSC1 0x150
204#define INTEL_MSIC_RTCSC2 0x151
205#define INTEL_MSIC_RTCSC3 0x152
206#define INTEL_MSIC_RTCSC4 0x153
207#define INTEL_MSIC_RTCSTATUS 0x154 /* RO */
208#define INTEL_MSIC_RTCCONFIG1 0x155
209#define INTEL_MSIC_RTCCONFIG2 0x156
210
211/* CHARGER */
212#define INTEL_MSIC_BDTIMER 0x180
213#define INTEL_MSIC_BATTRMV 0x181
214#define INTEL_MSIC_VBUSDET 0x182
215#define INTEL_MSIC_VBUSDET1 0x183
216#define INTEL_MSIC_ADPHVDET 0x184
217#define INTEL_MSIC_ADPLVDET 0x185
218#define INTEL_MSIC_ADPDETDBDM 0x186
219#define INTEL_MSIC_LOWBATTDET 0x187
220#define INTEL_MSIC_CHRCTRL 0x188
221#define INTEL_MSIC_CHRCVOLTAGE 0x189
222#define INTEL_MSIC_CHRCCURRENT 0x18a
223#define INTEL_MSIC_SPCHARGER 0x18b
224#define INTEL_MSIC_CHRTTIME 0x18c
225#define INTEL_MSIC_CHRCTRL1 0x18d
226#define INTEL_MSIC_PWRSRCLMT 0x18e
227#define INTEL_MSIC_CHRSTWDT 0x18f
228#define INTEL_MSIC_WDTWRITE 0x190 /* WO */
229#define INTEL_MSIC_CHRSAFELMT 0x191
230#define INTEL_MSIC_SPWRSRCINT 0x192 /* RO */
231#define INTEL_MSIC_SPWRSRCINT1 0x193 /* RO */
232#define INTEL_MSIC_CHRLEDPWM 0x194
233#define INTEL_MSIC_CHRLEDCTRL 0x195
234
235/* ADC */
236#define INTEL_MSIC_ADC1CNTL1 0x1c0
237#define INTEL_MSIC_ADC1CNTL2 0x1c1
238#define INTEL_MSIC_ADC1CNTL3 0x1c2
239#define INTEL_MSIC_ADC1OFFSETH 0x1c3 /* RO */
240#define INTEL_MSIC_ADC1OFFSETL 0x1c4 /* RO */
241#define INTEL_MSIC_ADC1ADDR0 0x1c5
242#define INTEL_MSIC_ADC1ADDR1 0x1c6
243#define INTEL_MSIC_ADC1ADDR2 0x1c7
244#define INTEL_MSIC_ADC1ADDR3 0x1c8
245#define INTEL_MSIC_ADC1ADDR4 0x1c9
246#define INTEL_MSIC_ADC1ADDR5 0x1ca
247#define INTEL_MSIC_ADC1ADDR6 0x1cb
248#define INTEL_MSIC_ADC1ADDR7 0x1cc
249#define INTEL_MSIC_ADC1ADDR8 0x1cd
250#define INTEL_MSIC_ADC1ADDR9 0x1ce
251#define INTEL_MSIC_ADC1ADDR10 0x1cf
252#define INTEL_MSIC_ADC1ADDR11 0x1d0
253#define INTEL_MSIC_ADC1ADDR12 0x1d1
254#define INTEL_MSIC_ADC1ADDR13 0x1d2
255#define INTEL_MSIC_ADC1ADDR14 0x1d3
256#define INTEL_MSIC_ADC1SNS0H 0x1d4 /* RO */
257#define INTEL_MSIC_ADC1SNS0L 0x1d5 /* RO */
258#define INTEL_MSIC_ADC1SNS1H 0x1d6 /* RO */
259#define INTEL_MSIC_ADC1SNS1L 0x1d7 /* RO */
260#define INTEL_MSIC_ADC1SNS2H 0x1d8 /* RO */
261#define INTEL_MSIC_ADC1SNS2L 0x1d9 /* RO */
262#define INTEL_MSIC_ADC1SNS3H 0x1da /* RO */
263#define INTEL_MSIC_ADC1SNS3L 0x1db /* RO */
264#define INTEL_MSIC_ADC1SNS4H 0x1dc /* RO */
265#define INTEL_MSIC_ADC1SNS4L 0x1dd /* RO */
266#define INTEL_MSIC_ADC1SNS5H 0x1de /* RO */
267#define INTEL_MSIC_ADC1SNS5L 0x1df /* RO */
268#define INTEL_MSIC_ADC1SNS6H 0x1e0 /* RO */
269#define INTEL_MSIC_ADC1SNS6L 0x1e1 /* RO */
270#define INTEL_MSIC_ADC1SNS7H 0x1e2 /* RO */
271#define INTEL_MSIC_ADC1SNS7L 0x1e3 /* RO */
272#define INTEL_MSIC_ADC1SNS8H 0x1e4 /* RO */
273#define INTEL_MSIC_ADC1SNS8L 0x1e5 /* RO */
274#define INTEL_MSIC_ADC1SNS9H 0x1e6 /* RO */
275#define INTEL_MSIC_ADC1SNS9L 0x1e7 /* RO */
276#define INTEL_MSIC_ADC1SNS10H 0x1e8 /* RO */
277#define INTEL_MSIC_ADC1SNS10L 0x1e9 /* RO */
278#define INTEL_MSIC_ADC1SNS11H 0x1ea /* RO */
279#define INTEL_MSIC_ADC1SNS11L 0x1eb /* RO */
280#define INTEL_MSIC_ADC1SNS12H 0x1ec /* RO */
281#define INTEL_MSIC_ADC1SNS12L 0x1ed /* RO */
282#define INTEL_MSIC_ADC1SNS13H 0x1ee /* RO */
283#define INTEL_MSIC_ADC1SNS13L 0x1ef /* RO */
284#define INTEL_MSIC_ADC1SNS14H 0x1f0 /* RO */
285#define INTEL_MSIC_ADC1SNS14L 0x1f1 /* RO */
286#define INTEL_MSIC_ADC1BV0H 0x1f2 /* RO */
287#define INTEL_MSIC_ADC1BV0L 0x1f3 /* RO */
288#define INTEL_MSIC_ADC1BV1H 0x1f4 /* RO */
289#define INTEL_MSIC_ADC1BV1L 0x1f5 /* RO */
290#define INTEL_MSIC_ADC1BV2H 0x1f6 /* RO */
291#define INTEL_MSIC_ADC1BV2L 0x1f7 /* RO */
292#define INTEL_MSIC_ADC1BV3H 0x1f8 /* RO */
293#define INTEL_MSIC_ADC1BV3L 0x1f9 /* RO */
294#define INTEL_MSIC_ADC1BI0H 0x1fa /* RO */
295#define INTEL_MSIC_ADC1BI0L 0x1fb /* RO */
296#define INTEL_MSIC_ADC1BI1H 0x1fc /* RO */
297#define INTEL_MSIC_ADC1BI1L 0x1fd /* RO */
298#define INTEL_MSIC_ADC1BI2H 0x1fe /* RO */
299#define INTEL_MSIC_ADC1BI2L 0x1ff /* RO */
300#define INTEL_MSIC_ADC1BI3H 0x200 /* RO */
301#define INTEL_MSIC_ADC1BI3L 0x201 /* RO */
302#define INTEL_MSIC_CCCNTL 0x202
303#define INTEL_MSIC_CCOFFSETH 0x203 /* RO */
304#define INTEL_MSIC_CCOFFSETL 0x204 /* RO */
305#define INTEL_MSIC_CCADCHA 0x205 /* RO */
306#define INTEL_MSIC_CCADCLA 0x206 /* RO */
307
308/* AUDIO */
309#define INTEL_MSIC_AUDPLLCTRL 0x240
310#define INTEL_MSIC_DMICBUF0123 0x241
311#define INTEL_MSIC_DMICBUF45 0x242
312#define INTEL_MSIC_DMICGPO 0x244
313#define INTEL_MSIC_DMICMUX 0x245
314#define INTEL_MSIC_DMICCLK 0x246
315#define INTEL_MSIC_MICBIAS 0x247
316#define INTEL_MSIC_ADCCONFIG 0x248
317#define INTEL_MSIC_MICAMP1 0x249
318#define INTEL_MSIC_MICAMP2 0x24a
319#define INTEL_MSIC_NOISEMUX 0x24b
320#define INTEL_MSIC_AUDIOMUX12 0x24c
321#define INTEL_MSIC_AUDIOMUX34 0x24d
322#define INTEL_MSIC_AUDIOSINC 0x24e
323#define INTEL_MSIC_AUDIOTXEN 0x24f
324#define INTEL_MSIC_HSEPRXCTRL 0x250
325#define INTEL_MSIC_IHFRXCTRL 0x251
326#define INTEL_MSIC_VOICETXVOL 0x252
327#define INTEL_MSIC_SIDETONEVOL 0x253
328#define INTEL_MSIC_MUSICSHARVOL 0x254
329#define INTEL_MSIC_VOICETXCTRL 0x255
330#define INTEL_MSIC_HSMIXER 0x256
331#define INTEL_MSIC_DACCONFIG 0x257
332#define INTEL_MSIC_SOFTMUTE 0x258
333#define INTEL_MSIC_HSLVOLCTRL 0x259
334#define INTEL_MSIC_HSRVOLCTRL 0x25a
335#define INTEL_MSIC_IHFLVOLCTRL 0x25b
336#define INTEL_MSIC_IHFRVOLCTRL 0x25c
337#define INTEL_MSIC_DRIVEREN 0x25d
338#define INTEL_MSIC_LINEOUTCTRL 0x25e
339#define INTEL_MSIC_VIB1CTRL1 0x25f
340#define INTEL_MSIC_VIB1CTRL2 0x260
341#define INTEL_MSIC_VIB1CTRL3 0x261
342#define INTEL_MSIC_VIB1SPIPCM_1 0x262
343#define INTEL_MSIC_VIB1SPIPCM_2 0x263
344#define INTEL_MSIC_VIB1CTRL5 0x264
345#define INTEL_MSIC_VIB2CTRL1 0x265
346#define INTEL_MSIC_VIB2CTRL2 0x266
347#define INTEL_MSIC_VIB2CTRL3 0x267
348#define INTEL_MSIC_VIB2SPIPCM_1 0x268
349#define INTEL_MSIC_VIB2SPIPCM_2 0x269
350#define INTEL_MSIC_VIB2CTRL5 0x26a
351#define INTEL_MSIC_BTNCTRL1 0x26b
352#define INTEL_MSIC_BTNCTRL2 0x26c
353#define INTEL_MSIC_PCM1TXSLOT01 0x26d
354#define INTEL_MSIC_PCM1TXSLOT23 0x26e
355#define INTEL_MSIC_PCM1TXSLOT45 0x26f
356#define INTEL_MSIC_PCM1RXSLOT0123 0x270
357#define INTEL_MSIC_PCM1RXSLOT045 0x271
358#define INTEL_MSIC_PCM2TXSLOT01 0x272
359#define INTEL_MSIC_PCM2TXSLOT23 0x273
360#define INTEL_MSIC_PCM2TXSLOT45 0x274
361#define INTEL_MSIC_PCM2RXSLOT01 0x275
362#define INTEL_MSIC_PCM2RXSLOT23 0x276
363#define INTEL_MSIC_PCM2RXSLOT45 0x277
364#define INTEL_MSIC_PCM1CTRL1 0x278
365#define INTEL_MSIC_PCM1CTRL2 0x279
366#define INTEL_MSIC_PCM1CTRL3 0x27a
367#define INTEL_MSIC_PCM2CTRL1 0x27b
368#define INTEL_MSIC_PCM2CTRL2 0x27c
369
370/* HDMI */
371#define INTEL_MSIC_HDMIPUEN 0x280
372#define INTEL_MSIC_HDMISTATUS 0x281 /* RO */
373
374/* Physical address of the start of the MSIC interrupt tree in SRAM */
375#define INTEL_MSIC_IRQ_PHYS_BASE 0xffff7fc0
376
377/**
378 * struct intel_msic_gpio_pdata - platform data for the MSIC GPIO driver
379 * @gpio_base: base number for the GPIOs
380 */
381struct intel_msic_gpio_pdata {
382 unsigned gpio_base;
383};
384
385/**
386 * struct intel_msic_ocd_pdata - platform data for the MSIC OCD driver
387 * @gpio: GPIO number used for OCD interrupts
388 *
389 * The MSIC MFD driver converts @gpio into an IRQ number and passes it to
390 * the OCD driver as %IORESOURCE_IRQ.
391 */
392struct intel_msic_ocd_pdata {
393 unsigned gpio;
394};
395
396/* MSIC embedded blocks (subdevices) */
397enum intel_msic_block {
398 INTEL_MSIC_BLOCK_TOUCH,
399 INTEL_MSIC_BLOCK_ADC,
400 INTEL_MSIC_BLOCK_BATTERY,
401 INTEL_MSIC_BLOCK_GPIO,
402 INTEL_MSIC_BLOCK_AUDIO,
403 INTEL_MSIC_BLOCK_HDMI,
404 INTEL_MSIC_BLOCK_THERMAL,
405 INTEL_MSIC_BLOCK_POWER_BTN,
406 INTEL_MSIC_BLOCK_OCD,
407
408 INTEL_MSIC_BLOCK_LAST,
409};
410
411/**
412 * struct intel_msic_platform_data - platform data for the MSIC driver
413 * @irq: array of interrupt numbers, one per device. If @irq is set to %0
414 * for a given block, the corresponding platform device is not
415 * created. For devices which don't have an interrupt, use %0xff
416 * (this is same as in SFI spec).
417 * @gpio: platform data for the MSIC GPIO driver
418 * @ocd: platform data for the MSIC OCD driver
419 *
420 * Once the MSIC driver is initialized, the register interface is ready to
421 * use. All the platform devices for subdevices are created after the
422 * register interface is ready so that we can guarantee its availability to
423 * the subdevice drivers.
424 *
425 * Interrupt numbers are passed to the subdevices via %IORESOURCE_IRQ
426 * resources of the created platform device.
427 */
428struct intel_msic_platform_data {
429 int irq[INTEL_MSIC_BLOCK_LAST];
430 struct intel_msic_gpio_pdata *gpio;
431 struct intel_msic_ocd_pdata *ocd;
432};
433
434struct intel_msic;
435
436extern int intel_msic_reg_read(unsigned short reg, u8 *val);
437extern int intel_msic_reg_write(unsigned short reg, u8 val);
438extern int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask);
439extern int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count);
440extern int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count);
441
442/*
443 * pdev_to_intel_msic - gets an MSIC instance from the platform device
444 * @pdev: platform device pointer
445 *
446 * The client drivers need to have pointer to the MSIC instance if they
447 * want to call intel_msic_irq_read(). This macro can be used for
448 * convenience to get the MSIC pointer from @pdev where needed. This is
449 * _only_ valid for devices which are managed by the MSIC.
450 */
451#define pdev_to_intel_msic(pdev) (dev_get_drvdata(pdev->dev.parent))
452
453extern int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg,
454 u8 *val);
455
456#endif /* __LINUX_MFD_INTEL_MSIC_H__ */
diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h
index 5ff2400ad46c..3f4deb62d6b0 100644
--- a/include/linux/mfd/max8997-private.h
+++ b/include/linux/mfd/max8997-private.h
@@ -326,7 +326,6 @@ struct max8997_dev {
326 int irq; 326 int irq;
327 int ono; 327 int ono;
328 int irq_base; 328 int irq_base;
329 bool wakeup;
330 struct mutex irqlock; 329 struct mutex irqlock;
331 int irq_masks_cur[MAX8997_IRQ_GROUP_NR]; 330 int irq_masks_cur[MAX8997_IRQ_GROUP_NR];
332 int irq_masks_cache[MAX8997_IRQ_GROUP_NR]; 331 int irq_masks_cache[MAX8997_IRQ_GROUP_NR];
diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h
index 7d0f3d6a0002..a8eeda773a7b 100644
--- a/include/linux/mfd/mc13783.h
+++ b/include/linux/mfd/mc13783.h
@@ -12,117 +12,6 @@
12 12
13#include <linux/mfd/mc13xxx.h> 13#include <linux/mfd/mc13xxx.h>
14 14
15struct mc13783;
16
17struct mc13xxx *mc13783_to_mc13xxx(struct mc13783 *mc13783);
18
19static inline void mc13783_lock(struct mc13783 *mc13783)
20{
21 mc13xxx_lock(mc13783_to_mc13xxx(mc13783));
22}
23
24static inline void mc13783_unlock(struct mc13783 *mc13783)
25{
26 mc13xxx_unlock(mc13783_to_mc13xxx(mc13783));
27}
28
29static inline int mc13783_reg_read(struct mc13783 *mc13783,
30 unsigned int offset, u32 *val)
31{
32 return mc13xxx_reg_read(mc13783_to_mc13xxx(mc13783), offset, val);
33}
34
35static inline int mc13783_reg_write(struct mc13783 *mc13783,
36 unsigned int offset, u32 val)
37{
38 return mc13xxx_reg_write(mc13783_to_mc13xxx(mc13783), offset, val);
39}
40
41static inline int mc13783_reg_rmw(struct mc13783 *mc13783,
42 unsigned int offset, u32 mask, u32 val)
43{
44 return mc13xxx_reg_rmw(mc13783_to_mc13xxx(mc13783), offset, mask, val);
45}
46
47static inline int mc13783_get_flags(struct mc13783 *mc13783)
48{
49 return mc13xxx_get_flags(mc13783_to_mc13xxx(mc13783));
50}
51
52static inline int mc13783_irq_request(struct mc13783 *mc13783, int irq,
53 irq_handler_t handler, const char *name, void *dev)
54{
55 return mc13xxx_irq_request(mc13783_to_mc13xxx(mc13783), irq,
56 handler, name, dev);
57}
58
59static inline int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
60 irq_handler_t handler, const char *name, void *dev)
61{
62 return mc13xxx_irq_request_nounmask(mc13783_to_mc13xxx(mc13783), irq,
63 handler, name, dev);
64}
65
66static inline int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
67{
68 return mc13xxx_irq_free(mc13783_to_mc13xxx(mc13783), irq, dev);
69}
70
71static inline int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
72{
73 return mc13xxx_irq_mask(mc13783_to_mc13xxx(mc13783), irq);
74}
75
76static inline int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
77{
78 return mc13xxx_irq_unmask(mc13783_to_mc13xxx(mc13783), irq);
79}
80static inline int mc13783_irq_status(struct mc13783 *mc13783, int irq,
81 int *enabled, int *pending)
82{
83 return mc13xxx_irq_status(mc13783_to_mc13xxx(mc13783),
84 irq, enabled, pending);
85}
86
87static inline int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
88{
89 return mc13xxx_irq_ack(mc13783_to_mc13xxx(mc13783), irq);
90}
91
92#define MC13783_ADC0 43
93#define MC13783_ADC0_ADREFEN (1 << 10)
94#define MC13783_ADC0_ADREFMODE (1 << 11)
95#define MC13783_ADC0_TSMOD0 (1 << 12)
96#define MC13783_ADC0_TSMOD1 (1 << 13)
97#define MC13783_ADC0_TSMOD2 (1 << 14)
98#define MC13783_ADC0_ADINC1 (1 << 16)
99#define MC13783_ADC0_ADINC2 (1 << 17)
100
101#define MC13783_ADC0_TSMOD_MASK (MC13783_ADC0_TSMOD0 | \
102 MC13783_ADC0_TSMOD1 | \
103 MC13783_ADC0_TSMOD2)
104
105#define mc13783_regulator_init_data mc13xxx_regulator_init_data
106#define mc13783_regulator_platform_data mc13xxx_regulator_platform_data
107#define mc13783_led_platform_data mc13xxx_led_platform_data
108#define mc13783_leds_platform_data mc13xxx_leds_platform_data
109
110#define mc13783_platform_data mc13xxx_platform_data
111#define MC13783_USE_TOUCHSCREEN MC13XXX_USE_TOUCHSCREEN
112#define MC13783_USE_CODEC MC13XXX_USE_CODEC
113#define MC13783_USE_ADC MC13XXX_USE_ADC
114#define MC13783_USE_RTC MC13XXX_USE_RTC
115#define MC13783_USE_REGULATOR MC13XXX_USE_REGULATOR
116#define MC13783_USE_LED MC13XXX_USE_LED
117
118#define MC13783_ADC_MODE_TS 1
119#define MC13783_ADC_MODE_SINGLE_CHAN 2
120#define MC13783_ADC_MODE_MULT_CHAN 3
121
122int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
123 unsigned int channel, unsigned int *sample);
124
125
126#define MC13783_REG_SW1A 0 15#define MC13783_REG_SW1A 0
127#define MC13783_REG_SW1B 1 16#define MC13783_REG_SW1B 1
128#define MC13783_REG_SW2A 2 17#define MC13783_REG_SW2A 2
diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h
index c064beaaccb7..3816c2fac0ad 100644
--- a/include/linux/mfd/mc13xxx.h
+++ b/include/linux/mfd/mc13xxx.h
@@ -37,6 +37,9 @@ int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq);
37 37
38int mc13xxx_get_flags(struct mc13xxx *mc13xxx); 38int mc13xxx_get_flags(struct mc13xxx *mc13xxx);
39 39
40int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx,
41 unsigned int mode, unsigned int channel, unsigned int *sample);
42
40#define MC13XXX_IRQ_ADCDONE 0 43#define MC13XXX_IRQ_ADCDONE 0
41#define MC13XXX_IRQ_ADCBISDONE 1 44#define MC13XXX_IRQ_ADCBISDONE 1
42#define MC13XXX_IRQ_TS 2 45#define MC13XXX_IRQ_TS 2
@@ -137,17 +140,48 @@ struct mc13xxx_leds_platform_data {
137 char tc3_period; 140 char tc3_period;
138}; 141};
139 142
143struct mc13xxx_buttons_platform_data {
144#define MC13783_BUTTON_DBNC_0MS 0
145#define MC13783_BUTTON_DBNC_30MS 1
146#define MC13783_BUTTON_DBNC_150MS 2
147#define MC13783_BUTTON_DBNC_750MS 3
148#define MC13783_BUTTON_ENABLE (1 << 2)
149#define MC13783_BUTTON_POL_INVERT (1 << 3)
150#define MC13783_BUTTON_RESET_EN (1 << 4)
151 int b1on_flags;
152 unsigned short b1on_key;
153 int b2on_flags;
154 unsigned short b2on_key;
155 int b3on_flags;
156 unsigned short b3on_key;
157};
158
140struct mc13xxx_platform_data { 159struct mc13xxx_platform_data {
141#define MC13XXX_USE_TOUCHSCREEN (1 << 0) 160#define MC13XXX_USE_TOUCHSCREEN (1 << 0)
142#define MC13XXX_USE_CODEC (1 << 1) 161#define MC13XXX_USE_CODEC (1 << 1)
143#define MC13XXX_USE_ADC (1 << 2) 162#define MC13XXX_USE_ADC (1 << 2)
144#define MC13XXX_USE_RTC (1 << 3) 163#define MC13XXX_USE_RTC (1 << 3)
145#define MC13XXX_USE_REGULATOR (1 << 4)
146#define MC13XXX_USE_LED (1 << 5)
147 unsigned int flags; 164 unsigned int flags;
148 165
149 struct mc13xxx_regulator_platform_data regulators; 166 struct mc13xxx_regulator_platform_data regulators;
150 struct mc13xxx_leds_platform_data *leds; 167 struct mc13xxx_leds_platform_data *leds;
168 struct mc13xxx_buttons_platform_data *buttons;
151}; 169};
152 170
171#define MC13XXX_ADC_MODE_TS 1
172#define MC13XXX_ADC_MODE_SINGLE_CHAN 2
173#define MC13XXX_ADC_MODE_MULT_CHAN 3
174
175#define MC13XXX_ADC0 43
176#define MC13XXX_ADC0_ADREFEN (1 << 10)
177#define MC13XXX_ADC0_TSMOD0 (1 << 12)
178#define MC13XXX_ADC0_TSMOD1 (1 << 13)
179#define MC13XXX_ADC0_TSMOD2 (1 << 14)
180#define MC13XXX_ADC0_ADINC1 (1 << 16)
181#define MC13XXX_ADC0_ADINC2 (1 << 17)
182
183#define MC13XXX_ADC0_TSMOD_MASK (MC13XXX_ADC0_TSMOD0 | \
184 MC13XXX_ADC0_TSMOD1 | \
185 MC13XXX_ADC0_TSMOD2)
186
153#endif /* ifndef __LINUX_MFD_MC13XXX_H */ 187#endif /* ifndef __LINUX_MFD_MC13XXX_H */
diff --git a/include/linux/mfd/pcf50633/core.h b/include/linux/mfd/pcf50633/core.h
index 50d4a047118d..a80840752b4c 100644
--- a/include/linux/mfd/pcf50633/core.h
+++ b/include/linux/mfd/pcf50633/core.h
@@ -21,6 +21,7 @@
21#include <linux/mfd/pcf50633/backlight.h> 21#include <linux/mfd/pcf50633/backlight.h>
22 22
23struct pcf50633; 23struct pcf50633;
24struct regmap;
24 25
25#define PCF50633_NUM_REGULATORS 11 26#define PCF50633_NUM_REGULATORS 11
26 27
@@ -134,7 +135,7 @@ enum {
134 135
135struct pcf50633 { 136struct pcf50633 {
136 struct device *dev; 137 struct device *dev;
137 struct i2c_client *i2c_client; 138 struct regmap *regmap;
138 139
139 struct pcf50633_platform_data *pdata; 140 struct pcf50633_platform_data *pdata;
140 int irq; 141 int irq;
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index ed8fe0d04097..4b1211859f74 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -382,6 +382,7 @@ struct wm831x {
382 382
383 /* Used by the interrupt controller code to post writes */ 383 /* Used by the interrupt controller code to post writes */
384 int gpio_update[WM831X_NUM_GPIO_REGS]; 384 int gpio_update[WM831X_NUM_GPIO_REGS];
385 bool gpio_level[WM831X_NUM_GPIO_REGS];
385 386
386 struct mutex auxadc_lock; 387 struct mutex auxadc_lock;
387 struct list_head auxadc_pending; 388 struct list_head auxadc_pending;
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
index 626809147624..f44bdb7273bd 100644
--- a/include/linux/mfd/wm8994/core.h
+++ b/include/linux/mfd/wm8994/core.h
@@ -59,6 +59,8 @@ struct wm8994 {
59 struct device *dev; 59 struct device *dev;
60 struct regmap *regmap; 60 struct regmap *regmap;
61 61
62 bool ldo_ena_always_driven;
63
62 int gpio_base; 64 int gpio_base;
63 int irq_base; 65 int irq_base;
64 66
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
index 97cf4f27d647..ea32f306dca6 100644
--- a/include/linux/mfd/wm8994/pdata.h
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -167,6 +167,13 @@ struct wm8994_pdata {
167 167
168 /* WM8958 microphone bias configuration */ 168 /* WM8958 microphone bias configuration */
169 int micbias[2]; 169 int micbias[2];
170
171 /* Disable the internal pull downs on the LDOs if they are
172 * always driven (eg, connected to an always on supply or
173 * GPIO that always drives an output. If they float power
174 * consumption will rise.
175 */
176 bool ldo_ena_always_driven;
170}; 177};
171 178
172#endif 179#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-01 16:47:00 -0500