diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/rk3288-cru.h | 38 |
1 files changed, 37 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index e65d5224e848..750e5587a7aa 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h | |||
| @@ -61,6 +61,15 @@ | |||
| 61 | #define SCLK_LCDC_PWM1 101 | 61 | #define SCLK_LCDC_PWM1 101 |
| 62 | #define SCLK_MAC_RX 102 | 62 | #define SCLK_MAC_RX 102 |
| 63 | #define SCLK_MAC_TX 103 | 63 | #define SCLK_MAC_TX 103 |
| 64 | #define SCLK_EDP_24M 104 | ||
| 65 | #define SCLK_EDP 105 | ||
| 66 | #define SCLK_RGA 106 | ||
| 67 | #define SCLK_ISP 107 | ||
| 68 | #define SCLK_ISP_JPE 108 | ||
| 69 | #define SCLK_HDMI_HDCP 109 | ||
| 70 | #define SCLK_HDMI_CEC 110 | ||
| 71 | #define SCLK_HEVC_CABAC 111 | ||
| 72 | #define SCLK_HEVC_CORE 112 | ||
| 64 | 73 | ||
| 65 | #define DCLK_VOP0 190 | 74 | #define DCLK_VOP0 190 |
| 66 | #define DCLK_VOP1 191 | 75 | #define DCLK_VOP1 191 |
| @@ -75,6 +84,16 @@ | |||
| 75 | #define ACLK_VOP1 198 | 84 | #define ACLK_VOP1 198 |
| 76 | #define ACLK_CRYPTO 199 | 85 | #define ACLK_CRYPTO 199 |
| 77 | #define ACLK_RGA 200 | 86 | #define ACLK_RGA 200 |
| 87 | #define ACLK_RGA_NIU 201 | ||
| 88 | #define ACLK_IEP 202 | ||
| 89 | #define ACLK_VIO0_NIU 203 | ||
| 90 | #define ACLK_VIP 204 | ||
| 91 | #define ACLK_ISP 205 | ||
| 92 | #define ACLK_VIO1_NIU 206 | ||
| 93 | #define ACLK_HEVC 207 | ||
| 94 | #define ACLK_VCODEC 208 | ||
| 95 | #define ACLK_CPU 209 | ||
| 96 | #define ACLK_PERI 210 | ||
| 78 | 97 | ||
| 79 | /* pclk gates */ | 98 | /* pclk gates */ |
| 80 | #define PCLK_GPIO0 320 | 99 | #define PCLK_GPIO0 320 |
| @@ -112,6 +131,15 @@ | |||
| 112 | #define PCLK_PS2C 352 | 131 | #define PCLK_PS2C 352 |
| 113 | #define PCLK_TIMER 353 | 132 | #define PCLK_TIMER 353 |
| 114 | #define PCLK_TZPC 354 | 133 | #define PCLK_TZPC 354 |
| 134 | #define PCLK_EDP_CTRL 355 | ||
| 135 | #define PCLK_MIPI_DSI0 356 | ||
| 136 | #define PCLK_MIPI_DSI1 357 | ||
| 137 | #define PCLK_MIPI_CSI 358 | ||
| 138 | #define PCLK_LVDS_PHY 359 | ||
| 139 | #define PCLK_HDMI_CTRL 360 | ||
| 140 | #define PCLK_VIO2_H2P 361 | ||
| 141 | #define PCLK_CPU 362 | ||
| 142 | #define PCLK_PERI 363 | ||
| 115 | 143 | ||
| 116 | /* hclk gates */ | 144 | /* hclk gates */ |
| 117 | #define HCLK_GPS 448 | 145 | #define HCLK_GPS 448 |
| @@ -137,8 +165,16 @@ | |||
| 137 | #define HCLK_IEP 468 | 165 | #define HCLK_IEP 468 |
| 138 | #define HCLK_ISP 469 | 166 | #define HCLK_ISP 469 |
| 139 | #define HCLK_RGA 470 | 167 | #define HCLK_RGA 470 |
| 168 | #define HCLK_VIO_AHB_ARBI 471 | ||
| 169 | #define HCLK_VIO_NIU 472 | ||
| 170 | #define HCLK_VIP 473 | ||
| 171 | #define HCLK_VIO2_H2P 474 | ||
| 172 | #define HCLK_HEVC 475 | ||
| 173 | #define HCLK_VCODEC 476 | ||
| 174 | #define HCLK_CPU 477 | ||
| 175 | #define HCLK_PERI 478 | ||
| 140 | 176 | ||
| 141 | #define CLK_NR_CLKS (HCLK_RGA + 1) | 177 | #define CLK_NR_CLKS (HCLK_PERI + 1) |
| 142 | 178 | ||
| 143 | /* soft-reset indices */ | 179 | /* soft-reset indices */ |
| 144 | #define SRST_CORE0 0 | 180 | #define SRST_CORE0 0 |
