10 files changed, 1754 insertions, 31 deletions

diff --git a/include/dt-bindings/mfd/qcom-rpm.h b/include/dt-bindings/mfd/qcom-rpm.h
new file mode 100644
index 000000000000..388a6f3d6165
--- /dev/null
+++ b/include/dt-bindings/mfd/qcom-rpm.h
@@ -0,0 +1,154 @@
+/*
+ * This header provides constants for the Qualcomm RPM bindings.
+ */
+
+#ifndef _DT_BINDINGS_MFD_QCOM_RPM_H
+#define _DT_BINDINGS_MFD_QCOM_RPM_H
+
+/*
+ * Constants use to identify individual resources in the RPM.
+ */
+#define QCOM_RPM_APPS_FABRIC_ARB                1
+#define QCOM_RPM_APPS_FABRIC_CLK                2
+#define QCOM_RPM_APPS_FABRIC_HALT               3
+#define QCOM_RPM_APPS_FABRIC_IOCTL              4
+#define QCOM_RPM_APPS_FABRIC_MODE               5
+#define QCOM_RPM_APPS_L2_CACHE_CTL              6
+#define QCOM_RPM_CFPB_CLK                       7
+#define QCOM_RPM_CXO_BUFFERS                    8
+#define QCOM_RPM_CXO_CLK                        9
+#define QCOM_RPM_DAYTONA_FABRIC_CLK             10
+#define QCOM_RPM_DDR_DMM                        11
+#define QCOM_RPM_EBI1_CLK                       12
+#define QCOM_RPM_HDMI_SWITCH                    13
+#define QCOM_RPM_MMFPB_CLK                      14
+#define QCOM_RPM_MM_FABRIC_ARB                  15
+#define QCOM_RPM_MM_FABRIC_CLK                  16
+#define QCOM_RPM_MM_FABRIC_HALT                 17
+#define QCOM_RPM_MM_FABRIC_IOCTL                18
+#define QCOM_RPM_MM_FABRIC_MODE                 19
+#define QCOM_RPM_PLL_4                          20
+#define QCOM_RPM_PM8058_LDO0                    21
+#define QCOM_RPM_PM8058_LDO1                    22
+#define QCOM_RPM_PM8058_LDO2                    23
+#define QCOM_RPM_PM8058_LDO3                    24
+#define QCOM_RPM_PM8058_LDO4                    25
+#define QCOM_RPM_PM8058_LDO5                    26
+#define QCOM_RPM_PM8058_LDO6                    27
+#define QCOM_RPM_PM8058_LDO7                    28
+#define QCOM_RPM_PM8058_LDO8                    29
+#define QCOM_RPM_PM8058_LDO9                    30
+#define QCOM_RPM_PM8058_LDO10                   31
+#define QCOM_RPM_PM8058_LDO11                   32
+#define QCOM_RPM_PM8058_LDO12                   33
+#define QCOM_RPM_PM8058_LDO13                   34
+#define QCOM_RPM_PM8058_LDO14                   35
+#define QCOM_RPM_PM8058_LDO15                   36
+#define QCOM_RPM_PM8058_LDO16                   37
+#define QCOM_RPM_PM8058_LDO17                   38
+#define QCOM_RPM_PM8058_LDO18                   39
+#define QCOM_RPM_PM8058_LDO19                   40
+#define QCOM_RPM_PM8058_LDO20                   41
+#define QCOM_RPM_PM8058_LDO21                   42
+#define QCOM_RPM_PM8058_LDO22                   43
+#define QCOM_RPM_PM8058_LDO23                   44
+#define QCOM_RPM_PM8058_LDO24                   45
+#define QCOM_RPM_PM8058_LDO25                   46
+#define QCOM_RPM_PM8058_LVS0                    47
+#define QCOM_RPM_PM8058_LVS1                    48
+#define QCOM_RPM_PM8058_NCP                     49
+#define QCOM_RPM_PM8058_SMPS0                   50
+#define QCOM_RPM_PM8058_SMPS1                   51
+#define QCOM_RPM_PM8058_SMPS2                   52
+#define QCOM_RPM_PM8058_SMPS3                   53
+#define QCOM_RPM_PM8058_SMPS4                   54
+#define QCOM_RPM_PM8821_LDO1                    55
+#define QCOM_RPM_PM8821_SMPS1                   56
+#define QCOM_RPM_PM8821_SMPS2                   57
+#define QCOM_RPM_PM8901_LDO0                    58
+#define QCOM_RPM_PM8901_LDO1                    59
+#define QCOM_RPM_PM8901_LDO2                    60
+#define QCOM_RPM_PM8901_LDO3                    61
+#define QCOM_RPM_PM8901_LDO4                    62
+#define QCOM_RPM_PM8901_LDO5                    63
+#define QCOM_RPM_PM8901_LDO6                    64
+#define QCOM_RPM_PM8901_LVS0                    65
+#define QCOM_RPM_PM8901_LVS1                    66
+#define QCOM_RPM_PM8901_LVS2                    67
+#define QCOM_RPM_PM8901_LVS3                    68
+#define QCOM_RPM_PM8901_MVS                     69
+#define QCOM_RPM_PM8901_SMPS0                   70
+#define QCOM_RPM_PM8901_SMPS1                   71
+#define QCOM_RPM_PM8901_SMPS2                   72
+#define QCOM_RPM_PM8901_SMPS3                   73
+#define QCOM_RPM_PM8901_SMPS4                   74
+#define QCOM_RPM_PM8921_CLK1                    75
+#define QCOM_RPM_PM8921_CLK2                    76
+#define QCOM_RPM_PM8921_LDO1                    77
+#define QCOM_RPM_PM8921_LDO2                    78
+#define QCOM_RPM_PM8921_LDO3                    79
+#define QCOM_RPM_PM8921_LDO4                    80
+#define QCOM_RPM_PM8921_LDO5                    81
+#define QCOM_RPM_PM8921_LDO6                    82
+#define QCOM_RPM_PM8921_LDO7                    83
+#define QCOM_RPM_PM8921_LDO8                    84
+#define QCOM_RPM_PM8921_LDO9                    85
+#define QCOM_RPM_PM8921_LDO10                   86
+#define QCOM_RPM_PM8921_LDO11                   87
+#define QCOM_RPM_PM8921_LDO12                   88
+#define QCOM_RPM_PM8921_LDO13                   89
+#define QCOM_RPM_PM8921_LDO14                   90
+#define QCOM_RPM_PM8921_LDO15                   91
+#define QCOM_RPM_PM8921_LDO16                   92
+#define QCOM_RPM_PM8921_LDO17                   93
+#define QCOM_RPM_PM8921_LDO18                   94
+#define QCOM_RPM_PM8921_LDO19                   95
+#define QCOM_RPM_PM8921_LDO20                   96
+#define QCOM_RPM_PM8921_LDO21                   97
+#define QCOM_RPM_PM8921_LDO22                   98
+#define QCOM_RPM_PM8921_LDO23                   99
+#define QCOM_RPM_PM8921_LDO24                   100
+#define QCOM_RPM_PM8921_LDO25                   101
+#define QCOM_RPM_PM8921_LDO26                   102
+#define QCOM_RPM_PM8921_LDO27                   103
+#define QCOM_RPM_PM8921_LDO28                   104
+#define QCOM_RPM_PM8921_LDO29                   105
+#define QCOM_RPM_PM8921_LVS1                    106
+#define QCOM_RPM_PM8921_LVS2                    107
+#define QCOM_RPM_PM8921_LVS3                    108
+#define QCOM_RPM_PM8921_LVS4                    109
+#define QCOM_RPM_PM8921_LVS5                    110
+#define QCOM_RPM_PM8921_LVS6                    111
+#define QCOM_RPM_PM8921_LVS7                    112
+#define QCOM_RPM_PM8921_MVS                     113
+#define QCOM_RPM_PM8921_NCP                     114
+#define QCOM_RPM_PM8921_SMPS1                   115
+#define QCOM_RPM_PM8921_SMPS2                   116
+#define QCOM_RPM_PM8921_SMPS3                   117
+#define QCOM_RPM_PM8921_SMPS4                   118
+#define QCOM_RPM_PM8921_SMPS5                   119
+#define QCOM_RPM_PM8921_SMPS6                   120
+#define QCOM_RPM_PM8921_SMPS7                   121
+#define QCOM_RPM_PM8921_SMPS8                   122
+#define QCOM_RPM_PXO_CLK                        123
+#define QCOM_RPM_QDSS_CLK                       124
+#define QCOM_RPM_SFPB_CLK                       125
+#define QCOM_RPM_SMI_CLK                        126
+#define QCOM_RPM_SYS_FABRIC_ARB                 127
+#define QCOM_RPM_SYS_FABRIC_CLK                 128
+#define QCOM_RPM_SYS_FABRIC_HALT                129
+#define QCOM_RPM_SYS_FABRIC_IOCTL               130
+#define QCOM_RPM_SYS_FABRIC_MODE                131
+#define QCOM_RPM_USB_OTG_SWITCH                 132
+#define QCOM_RPM_VDDMIN_GPIO                    133
+
+/*
+ * Constants used to select force mode for regulators.
+ */
+#define QCOM_RPM_FORCE_MODE_NONE                0
+#define QCOM_RPM_FORCE_MODE_LPM                 1
+#define QCOM_RPM_FORCE_MODE_HPM                 2
+#define QCOM_RPM_FORCE_MODE_AUTO                3
+#define QCOM_RPM_FORCE_MODE_BYPASS              4
+
+#endif
diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h
index 81589d176ae8..dfabd6db7ddf 100644
--- a/include/linux/mfd/axp20x.h
+++ b/include/linux/mfd/axp20x.h
@@ -124,10 +124,27 @@ enum {
 #define AXP288_PMIC_ADC_H               0x56
 #define AXP288_PMIC_ADC_L               0x57
 #define AXP288_ADC_TS_PIN_CTRL          0x84
-
 #define AXP288_PMIC_ADC_EN              0x84
-#define AXP288_FG_TUNE5                 0xed
 
+/* Fuel Gauge */
+#define AXP288_FG_RDC1_REG          0xba
+#define AXP288_FG_RDC0_REG          0xbb
+#define AXP288_FG_OCVH_REG          0xbc
+#define AXP288_FG_OCVL_REG          0xbd
+#define AXP288_FG_OCV_CURVE_REG     0xc0
+#define AXP288_FG_DES_CAP1_REG      0xe0
+#define AXP288_FG_DES_CAP0_REG      0xe1
+#define AXP288_FG_CC_MTR1_REG       0xe2
+#define AXP288_FG_CC_MTR0_REG       0xe3
+#define AXP288_FG_OCV_CAP_REG       0xe4
+#define AXP288_FG_CC_CAP_REG        0xe5
+#define AXP288_FG_LOW_CAP_REG       0xe6
+#define AXP288_FG_TUNE0             0xe8
+#define AXP288_FG_TUNE1             0xe9
+#define AXP288_FG_TUNE2             0xea
+#define AXP288_FG_TUNE3             0xeb
+#define AXP288_FG_TUNE4             0xec
+#define AXP288_FG_TUNE5             0xed
 
 /* Regulators IDs */
 enum {
@@ -236,4 +253,26 @@ struct axp20x_dev {
         const struct regmap_irq_chip    *regmap_irq_chip;
 };
 
+#define BATTID_LEN                              64
+#define OCV_CURVE_SIZE                  32
+#define MAX_THERM_CURVE_SIZE    25
+#define PD_DEF_MIN_TEMP                 0
+#define PD_DEF_MAX_TEMP                 55
+
+struct axp20x_fg_pdata {
+        char battid[BATTID_LEN + 1];
+        int design_cap;
+        int min_volt;
+        int max_volt;
+        int max_temp;
+        int min_temp;
+        int cap1;
+        int cap0;
+        int rdc1;
+        int rdc0;
+        int ocv_curve[OCV_CURVE_SIZE];
+        int tcsz;
+        int thermistor_curve[MAX_THERM_CURVE_SIZE][2];
+};
+
 #endif /* __LINUX_MFD_AXP20X_H */
diff --git a/include/linux/mfd/da9063/core.h b/include/linux/mfd/da9063/core.h
index b92a3262f8f6..79f4d822ba13 100644
--- a/include/linux/mfd/da9063/core.h
+++ b/include/linux/mfd/da9063/core.h
@@ -36,6 +36,7 @@ enum da9063_models {
 enum da9063_variant_codes {
         PMIC_DA9063_AD = 0x3,
         PMIC_DA9063_BB = 0x5,
+        PMIC_DA9063_CA = 0x6,
 };
 
 /* Interrupts */
diff --git a/include/linux/mfd/da9150/core.h b/include/linux/mfd/da9150/core.h
new file mode 100644
index 000000000000..76e668933a77
--- /dev/null
+++ b/include/linux/mfd/da9150/core.h
@@ -0,0 +1,68 @@
+/*
+ * DA9150 MFD Driver - Core Data
+ *
+ * Copyright (c) 2014 Dialog Semiconductor
+ *
+ * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __DA9150_CORE_H
+#define __DA9150_CORE_H
+
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/regmap.h>
+
+/* I2C address paging */
+#define DA9150_REG_PAGE_SHIFT   8
+#define DA9150_REG_PAGE_MASK    0xFF
+
+/* IRQs */
+#define DA9150_NUM_IRQ_REGS     4
+#define DA9150_IRQ_VBUS         0
+#define DA9150_IRQ_CHG          1
+#define DA9150_IRQ_TCLASS       2
+#define DA9150_IRQ_TJUNC        3
+#define DA9150_IRQ_VFAULT       4
+#define DA9150_IRQ_CONF         5
+#define DA9150_IRQ_DAT          6
+#define DA9150_IRQ_DTYPE        7
+#define DA9150_IRQ_ID           8
+#define DA9150_IRQ_ADP          9
+#define DA9150_IRQ_SESS_END     10
+#define DA9150_IRQ_SESS_VLD     11
+#define DA9150_IRQ_FG           12
+#define DA9150_IRQ_GP           13
+#define DA9150_IRQ_TBAT         14
+#define DA9150_IRQ_GPIOA        15
+#define DA9150_IRQ_GPIOB        16
+#define DA9150_IRQ_GPIOC        17
+#define DA9150_IRQ_GPIOD        18
+#define DA9150_IRQ_GPADC        19
+#define DA9150_IRQ_WKUP         20
+
+struct da9150_pdata {
+        int irq_base;
+};
+
+struct da9150 {
+        struct device *dev;
+        struct regmap *regmap;
+        struct regmap_irq_chip_data *regmap_irq_data;
+        int irq;
+        int irq_base;
+};
+
+/* Device I/O */
+u8 da9150_reg_read(struct da9150 *da9150, u16 reg);
+void da9150_reg_write(struct da9150 *da9150, u16 reg, u8 val);
+void da9150_set_bits(struct da9150 *da9150, u16 reg, u8 mask, u8 val);
+
+void da9150_bulk_read(struct da9150 *da9150, u16 reg, int count, u8 *buf);
+void da9150_bulk_write(struct da9150 *da9150, u16 reg, int count, const u8 *buf);
+#endif /* __DA9150_CORE_H */
diff --git a/include/linux/mfd/da9150/registers.h b/include/linux/mfd/da9150/registers.h
new file mode 100644
index 000000000000..27ca6ee4d840
--- /dev/null
+++ b/include/linux/mfd/da9150/registers.h
@@ -0,0 +1,1155 @@
+/*
+ * DA9150 MFD Driver - Registers
+ *
+ * Copyright (c) 2014 Dialog Semiconductor
+ *
+ * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __DA9150_REGISTERS_H
+#define __DA9150_REGISTERS_H
+
+#include <linux/bitops.h>
+
+/* Registers */
+#define DA9150_PAGE_CON                 0x000
+#define DA9150_STATUS_A                 0x068
+#define DA9150_STATUS_B                 0x069
+#define DA9150_STATUS_C                 0x06A
+#define DA9150_STATUS_D                 0x06B
+#define DA9150_STATUS_E                 0x06C
+#define DA9150_STATUS_F                 0x06D
+#define DA9150_STATUS_G                 0x06E
+#define DA9150_STATUS_H                 0x06F
+#define DA9150_STATUS_I                 0x070
+#define DA9150_STATUS_J                 0x071
+#define DA9150_STATUS_K                 0x072
+#define DA9150_STATUS_L                 0x073
+#define DA9150_STATUS_N                 0x074
+#define DA9150_FAULT_LOG_A              0x076
+#define DA9150_FAULT_LOG_B              0x077
+#define DA9150_EVENT_E                  0x078
+#define DA9150_EVENT_F                  0x079
+#define DA9150_EVENT_G                  0x07A
+#define DA9150_EVENT_H                  0x07B
+#define DA9150_IRQ_MASK_E               0x07C
+#define DA9150_IRQ_MASK_F               0x07D
+#define DA9150_IRQ_MASK_G               0x07E
+#define DA9150_IRQ_MASK_H               0x07F
+#define DA9150_PAGE_CON_1               0x080
+#define DA9150_CONFIG_A                 0x0E0
+#define DA9150_CONFIG_B                 0x0E1
+#define DA9150_CONFIG_C                 0x0E2
+#define DA9150_CONFIG_D                 0x0E3
+#define DA9150_CONFIG_E                 0x0E4
+#define DA9150_CONTROL_A                0x0E5
+#define DA9150_CONTROL_B                0x0E6
+#define DA9150_CONTROL_C                0x0E7
+#define DA9150_GPIO_A_B                 0x0E8
+#define DA9150_GPIO_C_D                 0x0E9
+#define DA9150_GPIO_MODE_CONT           0x0EA
+#define DA9150_GPIO_CTRL_B              0x0EB
+#define DA9150_GPIO_CTRL_A              0x0EC
+#define DA9150_GPIO_CTRL_C              0x0ED
+#define DA9150_GPIO_CFG_A               0x0EE
+#define DA9150_GPIO_CFG_B               0x0EF
+#define DA9150_GPIO_CFG_C               0x0F0
+#define DA9150_GPADC_MAN                0x0F2
+#define DA9150_GPADC_RES_A              0x0F4
+#define DA9150_GPADC_RES_B              0x0F5
+#define DA9150_PAGE_CON_2               0x100
+#define DA9150_OTP_CONT_SHARED          0x101
+#define DA9150_INTERFACE_SHARED         0x105
+#define DA9150_CONFIG_A_SHARED          0x106
+#define DA9150_CONFIG_D_SHARED          0x109
+#define DA9150_ADETVB_CFG_C             0x150
+#define DA9150_ADETD_STAT               0x151
+#define DA9150_ADET_CMPSTAT             0x152
+#define DA9150_ADET_CTRL_A              0x153
+#define DA9150_ADETVB_CFG_B             0x154
+#define DA9150_ADETVB_CFG_A             0x155
+#define DA9150_ADETAC_CFG_A             0x156
+#define DA9150_ADDETAC_CFG_B            0x157
+#define DA9150_ADETAC_CFG_C             0x158
+#define DA9150_ADETAC_CFG_D             0x159
+#define DA9150_ADETVB_CFG_D             0x15A
+#define DA9150_ADETID_CFG_A             0x15B
+#define DA9150_ADET_RID_PT_CHG_H        0x15C
+#define DA9150_ADET_RID_PT_CHG_L        0x15D
+#define DA9150_PPR_TCTR_B               0x160
+#define DA9150_PPR_BKCTRL_A             0x163
+#define DA9150_PPR_BKCFG_A              0x164
+#define DA9150_PPR_BKCFG_B              0x165
+#define DA9150_PPR_CHGCTRL_A            0x166
+#define DA9150_PPR_CHGCTRL_B            0x167
+#define DA9150_PPR_CHGCTRL_C            0x168
+#define DA9150_PPR_TCTR_A               0x169
+#define DA9150_PPR_CHGCTRL_D            0x16A
+#define DA9150_PPR_CHGCTRL_E            0x16B
+#define DA9150_PPR_CHGCTRL_F            0x16C
+#define DA9150_PPR_CHGCTRL_G            0x16D
+#define DA9150_PPR_CHGCTRL_H            0x16E
+#define DA9150_PPR_CHGCTRL_I            0x16F
+#define DA9150_PPR_CHGCTRL_J            0x170
+#define DA9150_PPR_CHGCTRL_K            0x171
+#define DA9150_PPR_CHGCTRL_L            0x172
+#define DA9150_PPR_CHGCTRL_M            0x173
+#define DA9150_PPR_THYST_A              0x174
+#define DA9150_PPR_THYST_B              0x175
+#define DA9150_PPR_THYST_C              0x176
+#define DA9150_PPR_THYST_D              0x177
+#define DA9150_PPR_THYST_E              0x178
+#define DA9150_PPR_THYST_F              0x179
+#define DA9150_PPR_THYST_G              0x17A
+#define DA9150_PAGE_CON_3               0x180
+#define DA9150_PAGE_CON_4               0x200
+#define DA9150_PAGE_CON_5               0x280
+#define DA9150_PAGE_CON_6               0x300
+#define DA9150_COREBTLD_STAT_A          0x302
+#define DA9150_COREBTLD_CTRL_A          0x303
+#define DA9150_CORE_CONFIG_A            0x304
+#define DA9150_CORE_CONFIG_C            0x305
+#define DA9150_CORE_CONFIG_B            0x306
+#define DA9150_CORE_CFG_DATA_A          0x307
+#define DA9150_CORE_CFG_DATA_B          0x308
+#define DA9150_CORE_CMD_A               0x309
+#define DA9150_CORE_DATA_A              0x30A
+#define DA9150_CORE_DATA_B              0x30B
+#define DA9150_CORE_DATA_C              0x30C
+#define DA9150_CORE_DATA_D              0x30D
+#define DA9150_CORE2WIRE_STAT_A         0x310
+#define DA9150_CORE2WIRE_CTRL_A         0x311
+#define DA9150_FW_CTRL_A                0x312
+#define DA9150_FW_CTRL_C                0x313
+#define DA9150_FW_CTRL_D                0x314
+#define DA9150_FG_CTRL_A                0x315
+#define DA9150_FG_CTRL_B                0x316
+#define DA9150_FW_CTRL_E                0x317
+#define DA9150_FW_CTRL_B                0x318
+#define DA9150_GPADC_CMAN               0x320
+#define DA9150_GPADC_CRES_A             0x322
+#define DA9150_GPADC_CRES_B             0x323
+#define DA9150_CC_CFG_A                 0x328
+#define DA9150_CC_CFG_B                 0x329
+#define DA9150_CC_ICHG_RES_A            0x32A
+#define DA9150_CC_ICHG_RES_B            0x32B
+#define DA9150_CC_IAVG_RES_A            0x32C
+#define DA9150_CC_IAVG_RES_B            0x32D
+#define DA9150_TAUX_CTRL_A              0x330
+#define DA9150_TAUX_RELOAD_H            0x332
+#define DA9150_TAUX_RELOAD_L            0x333
+#define DA9150_TAUX_VALUE_H             0x334
+#define DA9150_TAUX_VALUE_L             0x335
+#define DA9150_AUX_DATA_0               0x338
+#define DA9150_AUX_DATA_1               0x339
+#define DA9150_AUX_DATA_2               0x33A
+#define DA9150_AUX_DATA_3               0x33B
+#define DA9150_BIF_CTRL                 0x340
+#define DA9150_TBAT_CTRL_A              0x342
+#define DA9150_TBAT_CTRL_B              0x343
+#define DA9150_TBAT_RES_A               0x344
+#define DA9150_TBAT_RES_B               0x345
+
+/* DA9150_PAGE_CON = 0x000 */
+#define DA9150_PAGE_SHIFT                       0
+#define DA9150_PAGE_MASK                        (0x3f << 0)
+#define DA9150_I2C_PAGE_SHIFT                   1
+#define DA9150_I2C_PAGE_MASK                    (0x1f << 1)
+#define DA9150_WRITE_MODE_SHIFT                 6
+#define DA9150_WRITE_MODE_MASK                  BIT(6)
+#define DA9150_REVERT_SHIFT                     7
+#define DA9150_REVERT_MASK                      BIT(7)
+
+/* DA9150_STATUS_A = 0x068 */
+#define DA9150_WKUP_STAT_SHIFT                  2
+#define DA9150_WKUP_STAT_MASK                   (0x0f << 2)
+#define DA9150_SLEEP_STAT_SHIFT                 6
+#define DA9150_SLEEP_STAT_MASK                  (0x03 << 6)
+
+/* DA9150_STATUS_B = 0x069 */
+#define DA9150_VFAULT_STAT_SHIFT                0
+#define DA9150_VFAULT_STAT_MASK                 BIT(0)
+#define DA9150_TFAULT_STAT_SHIFT                1
+#define DA9150_TFAULT_STAT_MASK                 BIT(1)
+
+/* DA9150_STATUS_C = 0x06A */
+#define DA9150_VDD33_STAT_SHIFT                 0
+#define DA9150_VDD33_STAT_MASK                  BIT(0)
+#define DA9150_VDD33_SLEEP_SHIFT                1
+#define DA9150_VDD33_SLEEP_MASK                 BIT(1)
+#define DA9150_LFOSC_STAT_SHIFT                 7
+#define DA9150_LFOSC_STAT_MASK                  BIT(7)
+
+/* DA9150_STATUS_D = 0x06B */
+#define DA9150_GPIOA_STAT_SHIFT                 0
+#define DA9150_GPIOA_STAT_MASK                  BIT(0)
+#define DA9150_GPIOB_STAT_SHIFT                 1
+#define DA9150_GPIOB_STAT_MASK                  BIT(1)
+#define DA9150_GPIOC_STAT_SHIFT                 2
+#define DA9150_GPIOC_STAT_MASK                  BIT(2)
+#define DA9150_GPIOD_STAT_SHIFT                 3
+#define DA9150_GPIOD_STAT_MASK                  BIT(3)
+
+/* DA9150_STATUS_E = 0x06C */
+#define DA9150_DTYPE_SHIFT                      0
+#define DA9150_DTYPE_MASK                       (0x1f << 0)
+#define DA9150_DTYPE_DT_NIL                     (0x00 << 0)
+#define DA9150_DTYPE_DT_USB_OTG                 BIT(0)
+#define DA9150_DTYPE_DT_USB_STD                 (0x02 << 0)
+#define DA9150_DTYPE_DT_USB_CHG                 (0x03 << 0)
+#define DA9150_DTYPE_DT_ACA_CHG                 (0x04 << 0)
+#define DA9150_DTYPE_DT_ACA_OTG                 (0x05 << 0)
+#define DA9150_DTYPE_DT_ACA_DOC                 (0x06 << 0)
+#define DA9150_DTYPE_DT_DED_CHG                 (0x07 << 0)
+#define DA9150_DTYPE_DT_CR5_CHG                 (0x08 << 0)
+#define DA9150_DTYPE_DT_CR4_CHG                 (0x0c << 0)
+#define DA9150_DTYPE_DT_PT_CHG                  (0x11 << 0)
+#define DA9150_DTYPE_DT_NN_ACC                  (0x16 << 0)
+#define DA9150_DTYPE_DT_NN_CHG                  (0x17 << 0)
+
+/* DA9150_STATUS_F = 0x06D */
+#define DA9150_SESS_VLD_SHIFT                   0
+#define DA9150_SESS_VLD_MASK                    BIT(0)
+#define DA9150_ID_ERR_SHIFT                     1
+#define DA9150_ID_ERR_MASK                      BIT(1)
+#define DA9150_PT_CHG_SHIFT                     2
+#define DA9150_PT_CHG_MASK                      BIT(2)
+
+/* DA9150_STATUS_G = 0x06E */
+#define DA9150_RID_SHIFT                        0
+#define DA9150_RID_MASK                         (0xff << 0)
+
+/* DA9150_STATUS_H = 0x06F */
+#define DA9150_VBUS_STAT_SHIFT                  0
+#define DA9150_VBUS_STAT_MASK                   (0x07 << 0)
+#define DA9150_VBUS_STAT_OFF                    (0x00 << 0)
+#define DA9150_VBUS_STAT_WAIT                   BIT(0)
+#define DA9150_VBUS_STAT_CHG                    (0x02 << 0)
+#define DA9150_VBUS_TRED_SHIFT                  3
+#define DA9150_VBUS_TRED_MASK                   BIT(3)
+#define DA9150_VBUS_DROP_STAT_SHIFT             4
+#define DA9150_VBUS_DROP_STAT_MASK              (0x0f << 4)
+
+/* DA9150_STATUS_I = 0x070 */
+#define DA9150_VBUS_ISET_STAT_SHIFT             0
+#define DA9150_VBUS_ISET_STAT_MASK              (0x1f << 0)
+#define DA9150_VBUS_OT_SHIFT                    7
+#define DA9150_VBUS_OT_MASK                     BIT(7)
+
+/* DA9150_STATUS_J = 0x071 */
+#define DA9150_CHG_STAT_SHIFT                   0
+#define DA9150_CHG_STAT_MASK                    (0x0f << 0)
+#define DA9150_CHG_STAT_OFF                     (0x00 << 0)
+#define DA9150_CHG_STAT_SUSP                    BIT(0)
+#define DA9150_CHG_STAT_ACT                     (0x02 << 0)
+#define DA9150_CHG_STAT_PRE                     (0x03 << 0)
+#define DA9150_CHG_STAT_CC                      (0x04 << 0)
+#define DA9150_CHG_STAT_CV                      (0x05 << 0)
+#define DA9150_CHG_STAT_FULL                    (0x06 << 0)
+#define DA9150_CHG_STAT_TEMP                    (0x07 << 0)
+#define DA9150_CHG_STAT_TIME                    (0x08 << 0)
+#define DA9150_CHG_STAT_BAT                     (0x09 << 0)
+#define DA9150_CHG_TEMP_SHIFT                   4
+#define DA9150_CHG_TEMP_MASK                    (0x07 << 4)
+#define DA9150_CHG_TEMP_UNDER                   (0x06 << 4)
+#define DA9150_CHG_TEMP_OVER                    (0x07 << 4)
+#define DA9150_CHG_IEND_STAT_SHIFT              7
+#define DA9150_CHG_IEND_STAT_MASK               BIT(7)
+
+/* DA9150_STATUS_K = 0x072 */
+#define DA9150_CHG_IAV_H_SHIFT                  0
+#define DA9150_CHG_IAV_H_MASK                   (0xff << 0)
+
+/* DA9150_STATUS_L = 0x073 */
+#define DA9150_CHG_IAV_L_SHIFT                  5
+#define DA9150_CHG_IAV_L_MASK                   (0x07 << 5)
+
+/* DA9150_STATUS_N = 0x074 */
+#define DA9150_CHG_TIME_SHIFT                   1
+#define DA9150_CHG_TIME_MASK                    BIT(1)
+#define DA9150_CHG_TRED_SHIFT                   2
+#define DA9150_CHG_TRED_MASK                    BIT(2)
+#define DA9150_CHG_TJUNC_CLASS_SHIFT            3
+#define DA9150_CHG_TJUNC_CLASS_MASK             (0x07 << 3)
+#define DA9150_CHG_TJUNC_CLASS_6                (0x06 << 3)
+#define DA9150_EBS_STAT_SHIFT                   6
+#define DA9150_EBS_STAT_MASK                    BIT(6)
+#define DA9150_CHG_BAT_REMOVED_SHIFT            7
+#define DA9150_CHG_BAT_REMOVED_MASK             BIT(7)
+
+/* DA9150_FAULT_LOG_A = 0x076 */
+#define DA9150_TEMP_FAULT_SHIFT                 0
+#define DA9150_TEMP_FAULT_MASK                  BIT(0)
+#define DA9150_VSYS_FAULT_SHIFT                 1
+#define DA9150_VSYS_FAULT_MASK                  BIT(1)
+#define DA9150_START_FAULT_SHIFT                2
+#define DA9150_START_FAULT_MASK                 BIT(2)
+#define DA9150_EXT_FAULT_SHIFT                  3
+#define DA9150_EXT_FAULT_MASK                   BIT(3)
+#define DA9150_POR_FAULT_SHIFT                  4
+#define DA9150_POR_FAULT_MASK                   BIT(4)
+
+/* DA9150_FAULT_LOG_B = 0x077 */
+#define DA9150_VBUS_FAULT_SHIFT                 0
+#define DA9150_VBUS_FAULT_MASK                  BIT(0)
+#define DA9150_OTG_FAULT_SHIFT                  1
+#define DA9150_OTG_FAULT_MASK                   BIT(1)
+
+/* DA9150_EVENT_E = 0x078 */
+#define DA9150_E_VBUS_SHIFT                     0
+#define DA9150_E_VBUS_MASK                      BIT(0)
+#define DA9150_E_CHG_SHIFT                      1
+#define DA9150_E_CHG_MASK                       BIT(1)
+#define DA9150_E_TCLASS_SHIFT                   2
+#define DA9150_E_TCLASS_MASK                    BIT(2)
+#define DA9150_E_TJUNC_SHIFT                    3
+#define DA9150_E_TJUNC_MASK                     BIT(3)
+#define DA9150_E_VFAULT_SHIFT                   4
+#define DA9150_E_VFAULT_MASK                    BIT(4)
+#define DA9150_EVENTS_H_SHIFT                   5
+#define DA9150_EVENTS_H_MASK                    BIT(5)
+#define DA9150_EVENTS_G_SHIFT                   6
+#define DA9150_EVENTS_G_MASK                    BIT(6)
+#define DA9150_EVENTS_F_SHIFT                   7
+#define DA9150_EVENTS_F_MASK                    BIT(7)
+
+/* DA9150_EVENT_F = 0x079 */
+#define DA9150_E_CONF_SHIFT                     0
+#define DA9150_E_CONF_MASK                      BIT(0)
+#define DA9150_E_DAT_SHIFT                      1
+#define DA9150_E_DAT_MASK                       BIT(1)
+#define DA9150_E_DTYPE_SHIFT                    3
+#define DA9150_E_DTYPE_MASK                     BIT(3)
+#define DA9150_E_ID_SHIFT                       4
+#define DA9150_E_ID_MASK                        BIT(4)
+#define DA9150_E_ADP_SHIFT                      5
+#define DA9150_E_ADP_MASK                       BIT(5)
+#define DA9150_E_SESS_END_SHIFT                 6
+#define DA9150_E_SESS_END_MASK                  BIT(6)
+#define DA9150_E_SESS_VLD_SHIFT                 7
+#define DA9150_E_SESS_VLD_MASK                  BIT(7)
+
+/* DA9150_EVENT_G = 0x07A */
+#define DA9150_E_FG_SHIFT                       0
+#define DA9150_E_FG_MASK                        BIT(0)
+#define DA9150_E_GP_SHIFT                       1
+#define DA9150_E_GP_MASK                        BIT(1)
+#define DA9150_E_TBAT_SHIFT                     2
+#define DA9150_E_TBAT_MASK                      BIT(2)
+#define DA9150_E_GPIOA_SHIFT                    3
+#define DA9150_E_GPIOA_MASK                     BIT(3)
+#define DA9150_E_GPIOB_SHIFT                    4
+#define DA9150_E_GPIOB_MASK                     BIT(4)
+#define DA9150_E_GPIOC_SHIFT                    5
+#define DA9150_E_GPIOC_MASK                     BIT(5)
+#define DA9150_E_GPIOD_SHIFT                    6
+#define DA9150_E_GPIOD_MASK                     BIT(6)
+#define DA9150_E_GPADC_SHIFT                    7
+#define DA9150_E_GPADC_MASK                     BIT(7)
+
+/* DA9150_EVENT_H = 0x07B */
+#define DA9150_E_WKUP_SHIFT                     0
+#define DA9150_E_WKUP_MASK                      BIT(0)
+
+/* DA9150_IRQ_MASK_E = 0x07C */
+#define DA9150_M_VBUS_SHIFT                     0
+#define DA9150_M_VBUS_MASK                      BIT(0)
+#define DA9150_M_CHG_SHIFT                      1
+#define DA9150_M_CHG_MASK                       BIT(1)
+#define DA9150_M_TJUNC_SHIFT                    3
+#define DA9150_M_TJUNC_MASK                     BIT(3)
+#define DA9150_M_VFAULT_SHIFT                   4
+#define DA9150_M_VFAULT_MASK                    BIT(4)
+
+/* DA9150_IRQ_MASK_F = 0x07D */
+#define DA9150_M_CONF_SHIFT                     0
+#define DA9150_M_CONF_MASK                      BIT(0)
+#define DA9150_M_DAT_SHIFT                      1
+#define DA9150_M_DAT_MASK                       BIT(1)
+#define DA9150_M_DTYPE_SHIFT                    3
+#define DA9150_M_DTYPE_MASK                     BIT(3)
+#define DA9150_M_ID_SHIFT                       4
+#define DA9150_M_ID_MASK                        BIT(4)
+#define DA9150_M_ADP_SHIFT                      5
+#define DA9150_M_ADP_MASK                       BIT(5)
+#define DA9150_M_SESS_END_SHIFT                 6
+#define DA9150_M_SESS_END_MASK                  BIT(6)
+#define DA9150_M_SESS_VLD_SHIFT                 7
+#define DA9150_M_SESS_VLD_MASK                  BIT(7)
+
+/* DA9150_IRQ_MASK_G = 0x07E */
+#define DA9150_M_FG_SHIFT                       0
+#define DA9150_M_FG_MASK                        BIT(0)
+#define DA9150_M_GP_SHIFT                       1
+#define DA9150_M_GP_MASK                        BIT(1)
+#define DA9150_M_TBAT_SHIFT                     2
+#define DA9150_M_TBAT_MASK                      BIT(2)
+#define DA9150_M_GPIOA_SHIFT                    3
+#define DA9150_M_GPIOA_MASK                     BIT(3)
+#define DA9150_M_GPIOB_SHIFT                    4
+#define DA9150_M_GPIOB_MASK                     BIT(4)
+#define DA9150_M_GPIOC_SHIFT                    5
+#define DA9150_M_GPIOC_MASK                     BIT(5)
+#define DA9150_M_GPIOD_SHIFT                    6
+#define DA9150_M_GPIOD_MASK                     BIT(6)
+#define DA9150_M_GPADC_SHIFT                    7
+#define DA9150_M_GPADC_MASK                     BIT(7)
+
+/* DA9150_IRQ_MASK_H = 0x07F */
+#define DA9150_M_WKUP_SHIFT                     0
+#define DA9150_M_WKUP_MASK                      BIT(0)
+
+/* DA9150_PAGE_CON_1 = 0x080 */
+#define DA9150_PAGE_SHIFT                       0
+#define DA9150_PAGE_MASK                        (0x3f << 0)
+#define DA9150_WRITE_MODE_SHIFT                 6
+#define DA9150_WRITE_MODE_MASK                  BIT(6)
+#define DA9150_REVERT_SHIFT                     7
+#define DA9150_REVERT_MASK                      BIT(7)
+
+/* DA9150_CONFIG_A = 0x0E0 */
+#define DA9150_RESET_DUR_SHIFT                  0
+#define DA9150_RESET_DUR_MASK                   (0x03 << 0)
+#define DA9150_RESET_EXT_SHIFT                  2
+#define DA9150_RESET_EXT_MASK                   (0x03 << 2)
+#define DA9150_START_MAX_SHIFT                  4
+#define DA9150_START_MAX_MASK                   (0x03 << 4)
+#define DA9150_PS_WAIT_EN_SHIFT                 6
+#define DA9150_PS_WAIT_EN_MASK                  BIT(6)
+#define DA9150_PS_DISABLE_DIRECT_SHIFT          7
+#define DA9150_PS_DISABLE_DIRECT_MASK           BIT(7)
+
+/* DA9150_CONFIG_B = 0x0E1 */
+#define DA9150_VFAULT_ADJ_SHIFT                 0
+#define DA9150_VFAULT_ADJ_MASK                  (0x0f << 0)
+#define DA9150_VFAULT_HYST_SHIFT                4
+#define DA9150_VFAULT_HYST_MASK                 (0x07 << 4)
+#define DA9150_VFAULT_EN_SHIFT                  7
+#define DA9150_VFAULT_EN_MASK                   BIT(7)
+
+/* DA9150_CONFIG_C = 0x0E2 */
+#define DA9150_VSYS_MIN_SHIFT                   3
+#define DA9150_VSYS_MIN_MASK                    (0x1f << 3)
+
+/* DA9150_CONFIG_D = 0x0E3 */
+#define DA9150_LFOSC_EXT_SHIFT                  0
+#define DA9150_LFOSC_EXT_MASK                   BIT(0)
+#define DA9150_VDD33_DWN_SHIFT                  1
+#define DA9150_VDD33_DWN_MASK                   BIT(1)
+#define DA9150_WKUP_PM_EN_SHIFT                 2
+#define DA9150_WKUP_PM_EN_MASK                  BIT(2)
+#define DA9150_WKUP_CE_SEL_SHIFT                3
+#define DA9150_WKUP_CE_SEL_MASK                 (0x03 << 3)
+#define DA9150_WKUP_CLK32K_EN_SHIFT             5
+#define DA9150_WKUP_CLK32K_EN_MASK              BIT(5)
+#define DA9150_DISABLE_DEL_SHIFT                7
+#define DA9150_DISABLE_DEL_MASK                 BIT(7)
+
+/* DA9150_CONFIG_E = 0x0E4 */
+#define DA9150_PM_SPKSUP_DIS_SHIFT              0
+#define DA9150_PM_SPKSUP_DIS_MASK               BIT(0)
+#define DA9150_PM_MERGE_SHIFT                   1
+#define DA9150_PM_MERGE_MASK                    BIT(1)
+#define DA9150_PM_SR_OFF_SHIFT                  2
+#define DA9150_PM_SR_OFF_MASK                   BIT(2)
+#define DA9150_PM_TIMEOUT_EN_SHIFT              3
+#define DA9150_PM_TIMEOUT_EN_MASK               BIT(3)
+#define DA9150_PM_DLY_SEL_SHIFT                 4
+#define DA9150_PM_DLY_SEL_MASK                  (0x07 << 4)
+#define DA9150_PM_OUT_DLY_SEL_SHIFT             7
+#define DA9150_PM_OUT_DLY_SEL_MASK              BIT(7)
+
+/* DA9150_CONTROL_A = 0x0E5 */
+#define DA9150_VDD33_SL_SHIFT                   0
+#define DA9150_VDD33_SL_MASK                    BIT(0)
+#define DA9150_VDD33_LPM_SHIFT                  1
+#define DA9150_VDD33_LPM_MASK                   (0x03 << 1)
+#define DA9150_VDD33_EN_SHIFT                   3
+#define DA9150_VDD33_EN_MASK                    BIT(3)
+#define DA9150_GPI_LPM_SHIFT                    6
+#define DA9150_GPI_LPM_MASK                     BIT(6)
+#define DA9150_PM_IF_LPM_SHIFT                  7
+#define DA9150_PM_IF_LPM_MASK                   BIT(7)
+
+/* DA9150_CONTROL_B = 0x0E6 */
+#define DA9150_LPM_SHIFT                        0
+#define DA9150_LPM_MASK                         BIT(0)
+#define DA9150_RESET_SHIFT                      1
+#define DA9150_RESET_MASK                       BIT(1)
+#define DA9150_RESET_USRCONF_EN_SHIFT           2
+#define DA9150_RESET_USRCONF_EN_MASK            BIT(2)
+
+/* DA9150_CONTROL_C = 0x0E7 */
+#define DA9150_DISABLE_SHIFT                    0
+#define DA9150_DISABLE_MASK                     BIT(0)
+
+/* DA9150_GPIO_A_B = 0x0E8 */
+#define DA9150_GPIOA_PIN_SHIFT                  0
+#define DA9150_GPIOA_PIN_MASK                   (0x07 << 0)
+#define DA9150_GPIOA_PIN_GPI                    (0x00 << 0)
+#define DA9150_GPIOA_PIN_GPO_OD                 BIT(0)
+#define DA9150_GPIOA_TYPE_SHIFT                 3
+#define DA9150_GPIOA_TYPE_MASK                  BIT(3)
+#define DA9150_GPIOB_PIN_SHIFT                  4
+#define DA9150_GPIOB_PIN_MASK                   (0x07 << 4)
+#define DA9150_GPIOB_PIN_GPI                    (0x00 << 4)
+#define DA9150_GPIOB_PIN_GPO_OD                 BIT(4)
+#define DA9150_GPIOB_TYPE_SHIFT                 7
+#define DA9150_GPIOB_TYPE_MASK                  BIT(7)
+
+/* DA9150_GPIO_C_D = 0x0E9 */
+#define DA9150_GPIOC_PIN_SHIFT                  0
+#define DA9150_GPIOC_PIN_MASK                   (0x07 << 0)
+#define DA9150_GPIOC_PIN_GPI                    (0x00 << 0)
+#define DA9150_GPIOC_PIN_GPO_OD                 BIT(0)
+#define DA9150_GPIOC_TYPE_SHIFT                 3
+#define DA9150_GPIOC_TYPE_MASK                  BIT(3)
+#define DA9150_GPIOD_PIN_SHIFT                  4
+#define DA9150_GPIOD_PIN_MASK                   (0x07 << 4)
+#define DA9150_GPIOD_PIN_GPI                    (0x00 << 4)
+#define DA9150_GPIOD_PIN_GPO_OD                 BIT(4)
+#define DA9150_GPIOD_TYPE_SHIFT                 7
+#define DA9150_GPIOD_TYPE_MASK                  BIT(7)
+
+/* DA9150_GPIO_MODE_CONT = 0x0EA */
+#define DA9150_GPIOA_MODE_SHIFT                 0
+#define DA9150_GPIOA_MODE_MASK                  BIT(0)
+#define DA9150_GPIOB_MODE_SHIFT                 1
+#define DA9150_GPIOB_MODE_MASK                  BIT(1)
+#define DA9150_GPIOC_MODE_SHIFT                 2
+#define DA9150_GPIOC_MODE_MASK                  BIT(2)
+#define DA9150_GPIOD_MODE_SHIFT                 3
+#define DA9150_GPIOD_MODE_MASK                  BIT(3)
+#define DA9150_GPIOA_CONT_SHIFT                 4
+#define DA9150_GPIOA_CONT_MASK                  BIT(4)
+#define DA9150_GPIOB_CONT_SHIFT                 5
+#define DA9150_GPIOB_CONT_MASK                  BIT(5)
+#define DA9150_GPIOC_CONT_SHIFT                 6
+#define DA9150_GPIOC_CONT_MASK                  BIT(6)
+#define DA9150_GPIOD_CONT_SHIFT                 7
+#define DA9150_GPIOD_CONT_MASK                  BIT(7)
+
+/* DA9150_GPIO_CTRL_B = 0x0EB */
+#define DA9150_WAKE_PIN_SHIFT                   0
+#define DA9150_WAKE_PIN_MASK                    (0x03 << 0)
+#define DA9150_WAKE_MODE_SHIFT                  2
+#define DA9150_WAKE_MODE_MASK                   BIT(2)
+#define DA9150_WAKE_CONT_SHIFT                  3
+#define DA9150_WAKE_CONT_MASK                   BIT(3)
+#define DA9150_WAKE_DLY_SHIFT                   4
+#define DA9150_WAKE_DLY_MASK                    BIT(4)
+
+/* DA9150_GPIO_CTRL_A = 0x0EC */
+#define DA9150_GPIOA_ANAEN_SHIFT                0
+#define DA9150_GPIOA_ANAEN_MASK                 BIT(0)
+#define DA9150_GPIOB_ANAEN_SHIFT                1
+#define DA9150_GPIOB_ANAEN_MASK                 BIT(1)
+#define DA9150_GPIOC_ANAEN_SHIFT                2
+#define DA9150_GPIOC_ANAEN_MASK                 BIT(2)
+#define DA9150_GPIOD_ANAEN_SHIFT                3
+#define DA9150_GPIOD_ANAEN_MASK                 BIT(3)
+#define DA9150_GPIO_ANAEN                       0x01
+#define DA9150_GPIO_ANAEN_MASK                  0x0F
+#define DA9150_CHGLED_PIN_SHIFT                 5
+#define DA9150_CHGLED_PIN_MASK                  (0x07 << 5)
+
+/* DA9150_GPIO_CTRL_C = 0x0ED */
+#define DA9150_CHGBL_DUR_SHIFT                  0
+#define DA9150_CHGBL_DUR_MASK                   (0x03 << 0)
+#define DA9150_CHGBL_DBL_SHIFT                  2
+#define DA9150_CHGBL_DBL_MASK                   BIT(2)
+#define DA9150_CHGBL_FRQ_SHIFT                  3
+#define DA9150_CHGBL_FRQ_MASK                   (0x03 << 3)
+#define DA9150_CHGBL_FLKR_SHIFT                 5
+#define DA9150_CHGBL_FLKR_MASK                  BIT(5)
+
+/* DA9150_GPIO_CFG_A = 0x0EE */
+#define DA9150_CE_LPM_DEB_SHIFT                 0
+#define DA9150_CE_LPM_DEB_MASK                  (0x07 << 0)
+
+/* DA9150_GPIO_CFG_B = 0x0EF */
+#define DA9150_GPIOA_PUPD_SHIFT                 0
+#define DA9150_GPIOA_PUPD_MASK                  BIT(0)
+#define DA9150_GPIOB_PUPD_SHIFT                 1
+#define DA9150_GPIOB_PUPD_MASK                  BIT(1)
+#define DA9150_GPIOC_PUPD_SHIFT                 2
+#define DA9150_GPIOC_PUPD_MASK                  BIT(2)
+#define DA9150_GPIOD_PUPD_SHIFT                 3
+#define DA9150_GPIOD_PUPD_MASK                  BIT(3)
+#define DA9150_GPIO_PUPD_MASK                   (0xF << 0)
+#define DA9150_GPI_DEB_SHIFT                    4
+#define DA9150_GPI_DEB_MASK                     (0x07 << 4)
+#define DA9150_LPM_EN_SHIFT                     7
+#define DA9150_LPM_EN_MASK                      BIT(7)
+
+/* DA9150_GPIO_CFG_C = 0x0F0 */
+#define DA9150_GPI_V_SHIFT                      0
+#define DA9150_GPI_V_MASK                       BIT(0)
+#define DA9150_VDDIO_INT_SHIFT                  1
+#define DA9150_VDDIO_INT_MASK                   BIT(1)
+#define DA9150_FAULT_PIN_SHIFT                  3
+#define DA9150_FAULT_PIN_MASK                   (0x07 << 3)
+#define DA9150_FAULT_TYPE_SHIFT                 6
+#define DA9150_FAULT_TYPE_MASK                  BIT(6)
+#define DA9150_NIRQ_PUPD_SHIFT                  7
+#define DA9150_NIRQ_PUPD_MASK                   BIT(7)
+
+/* DA9150_GPADC_MAN = 0x0F2 */
+#define DA9150_GPADC_EN_SHIFT                   0
+#define DA9150_GPADC_EN_MASK                    BIT(0)
+#define DA9150_GPADC_MUX_SHIFT                  1
+#define DA9150_GPADC_MUX_MASK                   (0x1f << 1)
+
+/* DA9150_GPADC_RES_A = 0x0F4 */
+#define DA9150_GPADC_RES_H_SHIFT                0
+#define DA9150_GPADC_RES_H_MASK                 (0xff << 0)
+
+/* DA9150_GPADC_RES_B = 0x0F5 */
+#define DA9150_GPADC_RUN_SHIFT                  0
+#define DA9150_GPADC_RUN_MASK                   BIT(0)
+#define DA9150_GPADC_RES_L_SHIFT                6
+#define DA9150_GPADC_RES_L_MASK                 (0x03 << 6)
+#define DA9150_GPADC_RES_L_BITS                 2
+
+/* DA9150_PAGE_CON_2 = 0x100 */
+#define DA9150_PAGE_SHIFT                       0
+#define DA9150_PAGE_MASK                        (0x3f << 0)
+#define DA9150_WRITE_MODE_SHIFT                 6
+#define DA9150_WRITE_MODE_MASK                  BIT(6)
+#define DA9150_REVERT_SHIFT                     7
+#define DA9150_REVERT_MASK                      BIT(7)
+
+/* DA9150_OTP_CONT_SHARED = 0x101 */
+#define DA9150_PC_DONE_SHIFT                    3
+#define DA9150_PC_DONE_MASK                     BIT(3)
+
+/* DA9150_INTERFACE_SHARED = 0x105 */
+#define DA9150_IF_BASE_ADDR_SHIFT               4
+#define DA9150_IF_BASE_ADDR_MASK                (0x0f << 4)
+
+/* DA9150_CONFIG_A_SHARED = 0x106 */
+#define DA9150_NIRQ_VDD_SHIFT                   1
+#define DA9150_NIRQ_VDD_MASK                    BIT(1)
+#define DA9150_NIRQ_PIN_SHIFT                   2
+#define DA9150_NIRQ_PIN_MASK                    BIT(2)
+#define DA9150_NIRQ_TYPE_SHIFT                  3
+#define DA9150_NIRQ_TYPE_MASK                   BIT(3)
+#define DA9150_PM_IF_V_SHIFT                    4
+#define DA9150_PM_IF_V_MASK                     BIT(4)
+#define DA9150_PM_IF_FMP_SHIFT                  5
+#define DA9150_PM_IF_FMP_MASK                   BIT(5)
+#define DA9150_PM_IF_HSM_SHIFT                  6
+#define DA9150_PM_IF_HSM_MASK                   BIT(6)
+
+/* DA9150_CONFIG_D_SHARED = 0x109 */
+#define DA9150_NIRQ_MODE_SHIFT                  1
+#define DA9150_NIRQ_MODE_MASK                   BIT(1)
+
+/* DA9150_ADETVB_CFG_C = 0x150 */
+#define DA9150_TADP_RISE_SHIFT                  0
+#define DA9150_TADP_RISE_MASK                   (0xff << 0)
+
+/* DA9150_ADETD_STAT = 0x151 */
+#define DA9150_DCD_STAT_SHIFT                   0
+#define DA9150_DCD_STAT_MASK                    BIT(0)
+#define DA9150_PCD_STAT_SHIFT                   1
+#define DA9150_PCD_STAT_MASK                    (0x03 << 1)
+#define DA9150_SCD_STAT_SHIFT                   3
+#define DA9150_SCD_STAT_MASK                    (0x03 << 3)
+#define DA9150_DP_STAT_SHIFT                    5
+#define DA9150_DP_STAT_MASK                     BIT(5)
+#define DA9150_DM_STAT_SHIFT                    6
+#define DA9150_DM_STAT_MASK                     BIT(6)
+
+/* DA9150_ADET_CMPSTAT = 0x152 */
+#define DA9150_DP_COMP_SHIFT                    1
+#define DA9150_DP_COMP_MASK                     BIT(1)
+#define DA9150_DM_COMP_SHIFT                    2
+#define DA9150_DM_COMP_MASK                     BIT(2)
+#define DA9150_ADP_SNS_COMP_SHIFT               3
+#define DA9150_ADP_SNS_COMP_MASK                BIT(3)
+#define DA9150_ADP_PRB_COMP_SHIFT               4
+#define DA9150_ADP_PRB_COMP_MASK                BIT(4)
+#define DA9150_ID_COMP_SHIFT                    5
+#define DA9150_ID_COMP_MASK                     BIT(5)
+
+/* DA9150_ADET_CTRL_A = 0x153 */
+#define DA9150_AID_DAT_SHIFT                    0
+#define DA9150_AID_DAT_MASK                     BIT(0)
+#define DA9150_AID_ID_SHIFT                     1
+#define DA9150_AID_ID_MASK                      BIT(1)
+#define DA9150_AID_TRIG_SHIFT                   2
+#define DA9150_AID_TRIG_MASK                    BIT(2)
+
+/* DA9150_ADETVB_CFG_B = 0x154 */
+#define DA9150_VB_MODE_SHIFT                    0
+#define DA9150_VB_MODE_MASK                     (0x03 << 0)
+#define DA9150_VB_MODE_VB_SESS                  BIT(0)
+
+#define DA9150_TADP_PRB_SHIFT                   2
+#define DA9150_TADP_PRB_MASK                    BIT(2)
+#define DA9150_DAT_RPD_EXT_SHIFT                5
+#define DA9150_DAT_RPD_EXT_MASK                 BIT(5)
+#define DA9150_CONF_RPD_SHIFT                   6
+#define DA9150_CONF_RPD_MASK                    BIT(6)
+#define DA9150_CONF_SRP_SHIFT                   7
+#define DA9150_CONF_SRP_MASK                    BIT(7)
+
+/* DA9150_ADETVB_CFG_A = 0x155 */
+#define DA9150_AID_MODE_SHIFT                   0
+#define DA9150_AID_MODE_MASK                    (0x03 << 0)
+#define DA9150_AID_EXT_POL_SHIFT                2
+#define DA9150_AID_EXT_POL_MASK                 BIT(2)
+
+/* DA9150_ADETAC_CFG_A = 0x156 */
+#define DA9150_ISET_CDP_SHIFT                   0
+#define DA9150_ISET_CDP_MASK                    (0x1f << 0)
+#define DA9150_CONF_DBP_SHIFT                   5
+#define DA9150_CONF_DBP_MASK                    BIT(5)
+
+/* DA9150_ADDETAC_CFG_B = 0x157 */
+#define DA9150_ISET_DCHG_SHIFT                  0
+#define DA9150_ISET_DCHG_MASK                   (0x1f << 0)
+#define DA9150_CONF_GPIOA_SHIFT                 5
+#define DA9150_CONF_GPIOA_MASK                  BIT(5)
+#define DA9150_CONF_GPIOB_SHIFT                 6
+#define DA9150_CONF_GPIOB_MASK                  BIT(6)
+#define DA9150_AID_VB_SHIFT                     7
+#define DA9150_AID_VB_MASK                      BIT(7)
+
+/* DA9150_ADETAC_CFG_C = 0x158 */
+#define DA9150_ISET_DEF_SHIFT                   0
+#define DA9150_ISET_DEF_MASK                    (0x1f << 0)
+#define DA9150_CONF_MODE_SHIFT                  5
+#define DA9150_CONF_MODE_MASK                   (0x03 << 5)
+#define DA9150_AID_CR_DIS_SHIFT                 7
+#define DA9150_AID_CR_DIS_MASK                  BIT(7)
+
+/* DA9150_ADETAC_CFG_D = 0x159 */
+#define DA9150_ISET_UNIT_SHIFT                  0
+#define DA9150_ISET_UNIT_MASK                   (0x1f << 0)
+#define DA9150_AID_UNCLAMP_SHIFT                5
+#define DA9150_AID_UNCLAMP_MASK                 BIT(5)
+
+/* DA9150_ADETVB_CFG_D = 0x15A */
+#define DA9150_ID_MODE_SHIFT                    0
+#define DA9150_ID_MODE_MASK                     (0x03 << 0)
+#define DA9150_DAT_MODE_SHIFT                   2
+#define DA9150_DAT_MODE_MASK                    (0x0f << 2)
+#define DA9150_DAT_SWP_SHIFT                    6
+#define DA9150_DAT_SWP_MASK                     BIT(6)
+#define DA9150_DAT_CLAMP_EXT_SHIFT              7
+#define DA9150_DAT_CLAMP_EXT_MASK               BIT(7)
+
+/* DA9150_ADETID_CFG_A = 0x15B */
+#define DA9150_TID_POLL_SHIFT                   0
+#define DA9150_TID_POLL_MASK                    (0x07 << 0)
+#define DA9150_RID_CONV_SHIFT                   3
+#define DA9150_RID_CONV_MASK                    BIT(3)
+
+/* DA9150_ADET_RID_PT_CHG_H = 0x15C */
+#define DA9150_RID_PT_CHG_H_SHIFT               0
+#define DA9150_RID_PT_CHG_H_MASK                (0xff << 0)
+
+/* DA9150_ADET_RID_PT_CHG_L = 0x15D */
+#define DA9150_RID_PT_CHG_L_SHIFT               6
+#define DA9150_RID_PT_CHG_L_MASK                (0x03 << 6)
+
+/* DA9150_PPR_TCTR_B = 0x160 */
+#define DA9150_CHG_TCTR_VAL_SHIFT               0
+#define DA9150_CHG_TCTR_VAL_MASK                (0xff << 0)
+
+/* DA9150_PPR_BKCTRL_A = 0x163 */
+#define DA9150_VBUS_MODE_SHIFT                  0
+#define DA9150_VBUS_MODE_MASK                   (0x03 << 0)
+#define DA9150_VBUS_MODE_CHG                    BIT(0)
+#define DA9150_VBUS_MODE_OTG                    (0x02 << 0)
+#define DA9150_VBUS_LPM_SHIFT                   2
+#define DA9150_VBUS_LPM_MASK                    (0x03 << 2)
+#define DA9150_VBUS_SUSP_SHIFT                  4
+#define DA9150_VBUS_SUSP_MASK                   BIT(4)
+#define DA9150_VBUS_PWM_SHIFT                   5
+#define DA9150_VBUS_PWM_MASK                    BIT(5)
+#define DA9150_VBUS_ISO_SHIFT                   6
+#define DA9150_VBUS_ISO_MASK                    BIT(6)
+#define DA9150_VBUS_LDO_SHIFT                   7
+#define DA9150_VBUS_LDO_MASK                    BIT(7)
+
+/* DA9150_PPR_BKCFG_A = 0x164 */
+#define DA9150_VBUS_ISET_SHIFT                  0
+#define DA9150_VBUS_ISET_MASK                   (0x1f << 0)
+#define DA9150_VBUS_IMAX_SHIFT                  5
+#define DA9150_VBUS_IMAX_MASK                   BIT(5)
+#define DA9150_VBUS_IOTG_SHIFT                  6
+#define DA9150_VBUS_IOTG_MASK                   (0x03 << 6)
+
+/* DA9150_PPR_BKCFG_B = 0x165 */
+#define DA9150_VBUS_DROP_SHIFT                  0
+#define DA9150_VBUS_DROP_MASK                   (0x0f << 0)
+#define DA9150_VBUS_FAULT_DIS_SHIFT             6
+#define DA9150_VBUS_FAULT_DIS_MASK              BIT(6)
+#define DA9150_OTG_FAULT_DIS_SHIFT              7
+#define DA9150_OTG_FAULT_DIS_MASK               BIT(7)
+
+/* DA9150_PPR_CHGCTRL_A = 0x166 */
+#define DA9150_CHG_EN_SHIFT                     0
+#define DA9150_CHG_EN_MASK                      BIT(0)
+
+/* DA9150_PPR_CHGCTRL_B = 0x167 */
+#define DA9150_CHG_VBAT_SHIFT                   0
+#define DA9150_CHG_VBAT_MASK                    (0x1f << 0)
+#define DA9150_CHG_VDROP_SHIFT                  6
+#define DA9150_CHG_VDROP_MASK                   (0x03 << 6)
+
+/* DA9150_PPR_CHGCTRL_C = 0x168 */
+#define DA9150_CHG_VFAULT_SHIFT                 0
+#define DA9150_CHG_VFAULT_MASK                  (0x0f << 0)
+#define DA9150_CHG_IPRE_SHIFT                   4
+#define DA9150_CHG_IPRE_MASK                    (0x03 << 4)
+
+/* DA9150_PPR_TCTR_A = 0x169 */
+#define DA9150_CHG_TCTR_SHIFT                   0
+#define DA9150_CHG_TCTR_MASK                    (0x07 << 0)
+#define DA9150_CHG_TCTR_MODE_SHIFT              4
+#define DA9150_CHG_TCTR_MODE_MASK               BIT(4)
+
+/* DA9150_PPR_CHGCTRL_D = 0x16A */
+#define DA9150_CHG_IBAT_SHIFT                   0
+#define DA9150_CHG_IBAT_MASK                    (0xff << 0)
+
+/* DA9150_PPR_CHGCTRL_E = 0x16B */
+#define DA9150_CHG_IEND_SHIFT                   0
+#define DA9150_CHG_IEND_MASK                    (0xff << 0)
+
+/* DA9150_PPR_CHGCTRL_F = 0x16C */
+#define DA9150_CHG_VCOLD_SHIFT                  0
+#define DA9150_CHG_VCOLD_MASK                   (0x1f << 0)
+#define DA9150_TBAT_TQA_EN_SHIFT                6
+#define DA9150_TBAT_TQA_EN_MASK                 BIT(6)
+#define DA9150_TBAT_TDP_EN_SHIFT                7
+#define DA9150_TBAT_TDP_EN_MASK                 BIT(7)
+
+/* DA9150_PPR_CHGCTRL_G = 0x16D */
+#define DA9150_CHG_VWARM_SHIFT                  0
+#define DA9150_CHG_VWARM_MASK                   (0x1f << 0)
+
+/* DA9150_PPR_CHGCTRL_H = 0x16E */
+#define DA9150_CHG_VHOT_SHIFT                   0
+#define DA9150_CHG_VHOT_MASK                    (0x1f << 0)
+
+/* DA9150_PPR_CHGCTRL_I = 0x16F */
+#define DA9150_CHG_ICOLD_SHIFT                  0
+#define DA9150_CHG_ICOLD_MASK                   (0xff << 0)
+
+/* DA9150_PPR_CHGCTRL_J = 0x170 */
+#define DA9150_CHG_IWARM_SHIFT                  0
+#define DA9150_CHG_IWARM_MASK                   (0xff << 0)
+
+/* DA9150_PPR_CHGCTRL_K = 0x171 */
+#define DA9150_CHG_IHOT_SHIFT                   0
+#define DA9150_CHG_IHOT_MASK                    (0xff << 0)
+
+/* DA9150_PPR_CHGCTRL_L = 0x172 */
+#define DA9150_CHG_IBAT_TRED_SHIFT              0
+#define DA9150_CHG_IBAT_TRED_MASK               (0xff << 0)
+
+/* DA9150_PPR_CHGCTRL_M = 0x173 */
+#define DA9150_CHG_VFLOAT_SHIFT                 0
+#define DA9150_CHG_VFLOAT_MASK                  (0x0f << 0)
+#define DA9150_CHG_LPM_SHIFT                    5
+#define DA9150_CHG_LPM_MASK                     BIT(5)
+#define DA9150_CHG_NBLO_SHIFT                   6
+#define DA9150_CHG_NBLO_MASK                    BIT(6)
+#define DA9150_EBS_EN_SHIFT                     7
+#define DA9150_EBS_EN_MASK                      BIT(7)
+
+/* DA9150_PPR_THYST_A = 0x174 */
+#define DA9150_TBAT_T1_SHIFT                    0
+#define DA9150_TBAT_T1_MASK                     (0xff << 0)
+
+/* DA9150_PPR_THYST_B = 0x175 */
+#define DA9150_TBAT_T2_SHIFT                    0
+#define DA9150_TBAT_T2_MASK                     (0xff << 0)
+
+/* DA9150_PPR_THYST_C = 0x176 */
+#define DA9150_TBAT_T3_SHIFT                    0
+#define DA9150_TBAT_T3_MASK                     (0xff << 0)
+
+/* DA9150_PPR_THYST_D = 0x177 */
+#define DA9150_TBAT_T4_SHIFT                    0
+#define DA9150_TBAT_T4_MASK                     (0xff << 0)
+
+/* DA9150_PPR_THYST_E = 0x178 */
+#define DA9150_TBAT_T5_SHIFT                    0
+#define DA9150_TBAT_T5_MASK                     (0xff << 0)
+
+/* DA9150_PPR_THYST_F = 0x179 */
+#define DA9150_TBAT_H1_SHIFT                    0
+#define DA9150_TBAT_H1_MASK                     (0xff << 0)
+
+/* DA9150_PPR_THYST_G = 0x17A */
+#define DA9150_TBAT_H5_SHIFT                    0
+#define DA9150_TBAT_H5_MASK                     (0xff << 0)
+
+/* DA9150_PAGE_CON_3 = 0x180 */
+#define DA9150_PAGE_SHIFT                       0
+#define DA9150_PAGE_MASK                        (0x3f << 0)
+#define DA9150_WRITE_MODE_SHIFT                 6
+#define DA9150_WRITE_MODE_MASK                  BIT(6)
+#define DA9150_REVERT_SHIFT                     7
+#define DA9150_REVERT_MASK                      BIT(7)
+
+/* DA9150_PAGE_CON_4 = 0x200 */
+#define DA9150_PAGE_SHIFT                       0
+#define DA9150_PAGE_MASK                        (0x3f << 0)
+#define DA9150_WRITE_MODE_SHIFT                 6
+#define DA9150_WRITE_MODE_MASK                  BIT(6)
+#define DA9150_REVERT_SHIFT                     7
+#define DA9150_REVERT_MASK                      BIT(7)
+
+/* DA9150_PAGE_CON_5 = 0x280 */
+#define DA9150_PAGE_SHIFT                       0
+#define DA9150_PAGE_MASK                        (0x3f << 0)
+#define DA9150_WRITE_MODE_SHIFT                 6
+#define DA9150_WRITE_MODE_MASK                  BIT(6)
+#define DA9150_REVERT_SHIFT                     7
+#define DA9150_REVERT_MASK                      BIT(7)
+
+/* DA9150_PAGE_CON_6 = 0x300 */
+#define DA9150_PAGE_SHIFT                       0
+#define DA9150_PAGE_MASK                        (0x3f << 0)
+#define DA9150_WRITE_MODE_SHIFT                 6
+#define DA9150_WRITE_MODE_MASK                  BIT(6)
+#define DA9150_REVERT_SHIFT                     7
+#define DA9150_REVERT_MASK                      BIT(7)
+
+/* DA9150_COREBTLD_STAT_A = 0x302 */
+#define DA9150_BOOTLD_STAT_SHIFT                0
+#define DA9150_BOOTLD_STAT_MASK                 (0x03 << 0)
+#define DA9150_CORE_LOCKUP_SHIFT                2
+#define DA9150_CORE_LOCKUP_MASK                 BIT(2)
+
+/* DA9150_COREBTLD_CTRL_A = 0x303 */
+#define DA9150_CORE_RESET_SHIFT                 0
+#define DA9150_CORE_RESET_MASK                  BIT(0)
+#define DA9150_CORE_STOP_SHIFT                  1
+#define DA9150_CORE_STOP_MASK                   BIT(1)
+
+/* DA9150_CORE_CONFIG_A = 0x304 */
+#define DA9150_CORE_MEMMUX_SHIFT                0
+#define DA9150_CORE_MEMMUX_MASK                 (0x03 << 0)
+#define DA9150_WDT_AUTO_START_SHIFT             2
+#define DA9150_WDT_AUTO_START_MASK              BIT(2)
+#define DA9150_WDT_AUTO_LOCK_SHIFT              3
+#define DA9150_WDT_AUTO_LOCK_MASK               BIT(3)
+#define DA9150_WDT_HLT_NO_CLK_SHIFT             4
+#define DA9150_WDT_HLT_NO_CLK_MASK              BIT(4)
+
+/* DA9150_CORE_CONFIG_C = 0x305 */
+#define DA9150_CORE_SW_SIZE_SHIFT               0
+#define DA9150_CORE_SW_SIZE_MASK                (0xff << 0)
+
+/* DA9150_CORE_CONFIG_B = 0x306 */
+#define DA9150_BOOTLD_EN_SHIFT                  0
+#define DA9150_BOOTLD_EN_MASK                   BIT(0)
+#define DA9150_CORE_EN_SHIFT                    2
+#define DA9150_CORE_EN_MASK                     BIT(2)
+#define DA9150_CORE_SW_SRC_SHIFT                3
+#define DA9150_CORE_SW_SRC_MASK                 (0x07 << 3)
+#define DA9150_DEEP_SLEEP_EN_SHIFT              7
+#define DA9150_DEEP_SLEEP_EN_MASK               BIT(7)
+
+/* DA9150_CORE_CFG_DATA_A = 0x307 */
+#define DA9150_CORE_CFG_DT_A_SHIFT              0
+#define DA9150_CORE_CFG_DT_A_MASK               (0xff << 0)
+
+/* DA9150_CORE_CFG_DATA_B = 0x308 */
+#define DA9150_CORE_CFG_DT_B_SHIFT              0
+#define DA9150_CORE_CFG_DT_B_MASK               (0xff << 0)
+
+/* DA9150_CORE_CMD_A = 0x309 */
+#define DA9150_CORE_CMD_SHIFT                   0
+#define DA9150_CORE_CMD_MASK                    (0xff << 0)
+
+/* DA9150_CORE_DATA_A = 0x30A */
+#define DA9150_CORE_DATA_0_SHIFT                0
+#define DA9150_CORE_DATA_0_MASK                 (0xff << 0)
+
+/* DA9150_CORE_DATA_B = 0x30B */
+#define DA9150_CORE_DATA_1_SHIFT                0
+#define DA9150_CORE_DATA_1_MASK                 (0xff << 0)
+
+/* DA9150_CORE_DATA_C = 0x30C */
+#define DA9150_CORE_DATA_2_SHIFT                0
+#define DA9150_CORE_DATA_2_MASK                 (0xff << 0)
+
+/* DA9150_CORE_DATA_D = 0x30D */
+#define DA9150_CORE_DATA_3_SHIFT                0
+#define DA9150_CORE_DATA_3_MASK                 (0xff << 0)
+
+/* DA9150_CORE2WIRE_STAT_A = 0x310 */
+#define DA9150_FW_FWDL_ERR_SHIFT                7
+#define DA9150_FW_FWDL_ERR_MASK                 BIT(7)
+
+/* DA9150_CORE2WIRE_CTRL_A = 0x311 */
+#define DA9150_FW_FWDL_EN_SHIFT                 0
+#define DA9150_FW_FWDL_EN_MASK                  BIT(0)
+#define DA9150_FG_QIF_EN_SHIFT                  1
+#define DA9150_FG_QIF_EN_MASK                   BIT(1)
+#define DA9150_CORE_BASE_ADDR_SHIFT             4
+#define DA9150_CORE_BASE_ADDR_MASK              (0x0f << 4)
+
+/* DA9150_FW_CTRL_A = 0x312 */
+#define DA9150_FW_SEAL_SHIFT                    0
+#define DA9150_FW_SEAL_MASK                     (0xff << 0)
+
+/* DA9150_FW_CTRL_C = 0x313 */
+#define DA9150_FW_FWDL_CRC_SHIFT                0
+#define DA9150_FW_FWDL_CRC_MASK                 (0xff << 0)
+
+/* DA9150_FW_CTRL_D = 0x314 */
+#define DA9150_FW_FWDL_BASE_SHIFT               0
+#define DA9150_FW_FWDL_BASE_MASK                (0x0f << 0)
+
+/* DA9150_FG_CTRL_A = 0x315 */
+#define DA9150_FG_QIF_CODE_SHIFT                0
+#define DA9150_FG_QIF_CODE_MASK                 (0xff << 0)
+
+/* DA9150_FG_CTRL_B = 0x316 */
+#define DA9150_FG_QIF_VALUE_SHIFT               0
+#define DA9150_FG_QIF_VALUE_MASK                (0xff << 0)
+
+/* DA9150_FW_CTRL_E = 0x317 */
+#define DA9150_FW_FWDL_SEG_SHIFT                0
+#define DA9150_FW_FWDL_SEG_MASK                 (0xff << 0)
+
+/* DA9150_FW_CTRL_B = 0x318 */
+#define DA9150_FW_FWDL_VALUE_SHIFT              0
+#define DA9150_FW_FWDL_VALUE_MASK               (0xff << 0)
+
+/* DA9150_GPADC_CMAN = 0x320 */
+#define DA9150_GPADC_CEN_SHIFT                  0
+#define DA9150_GPADC_CEN_MASK                   BIT(0)
+#define DA9150_GPADC_CMUX_SHIFT                 1
+#define DA9150_GPADC_CMUX_MASK                  (0x1f << 1)
+
+/* DA9150_GPADC_CRES_A = 0x322 */
+#define DA9150_GPADC_CRES_H_SHIFT               0
+#define DA9150_GPADC_CRES_H_MASK                (0xff << 0)
+
+/* DA9150_GPADC_CRES_B = 0x323 */
+#define DA9150_GPADC_CRUN_SHIFT                 0
+#define DA9150_GPADC_CRUN_MASK                  BIT(0)
+#define DA9150_GPADC_CRES_L_SHIFT               6
+#define DA9150_GPADC_CRES_L_MASK                (0x03 << 6)
+
+/* DA9150_CC_CFG_A = 0x328 */
+#define DA9150_CC_EN_SHIFT                      0
+#define DA9150_CC_EN_MASK                       BIT(0)
+#define DA9150_CC_TIMEBASE_SHIFT                1
+#define DA9150_CC_TIMEBASE_MASK                 (0x03 << 1)
+#define DA9150_CC_CFG_SHIFT                     5
+#define DA9150_CC_CFG_MASK                      (0x03 << 5)
+#define DA9150_CC_ENDLESS_MODE_SHIFT            7
+#define DA9150_CC_ENDLESS_MODE_MASK             BIT(7)
+
+/* DA9150_CC_CFG_B = 0x329 */
+#define DA9150_CC_OPT_SHIFT                     0
+#define DA9150_CC_OPT_MASK                      (0x03 << 0)
+#define DA9150_CC_PREAMP_SHIFT                  2
+#define DA9150_CC_PREAMP_MASK                   (0x03 << 2)
+
+/* DA9150_CC_ICHG_RES_A = 0x32A */
+#define DA9150_CC_ICHG_RES_H_SHIFT              0
+#define DA9150_CC_ICHG_RES_H_MASK               (0xff << 0)
+
+/* DA9150_CC_ICHG_RES_B = 0x32B */
+#define DA9150_CC_ICHG_RES_L_SHIFT              3
+#define DA9150_CC_ICHG_RES_L_MASK               (0x1f << 3)
+
+/* DA9150_CC_IAVG_RES_A = 0x32C */
+#define DA9150_CC_IAVG_RES_H_SHIFT              0
+#define DA9150_CC_IAVG_RES_H_MASK               (0xff << 0)
+
+/* DA9150_CC_IAVG_RES_B = 0x32D */
+#define DA9150_CC_IAVG_RES_L_SHIFT              0
+#define DA9150_CC_IAVG_RES_L_MASK               (0xff << 0)
+
+/* DA9150_TAUX_CTRL_A = 0x330 */
+#define DA9150_TAUX_EN_SHIFT                    0
+#define DA9150_TAUX_EN_MASK                     BIT(0)
+#define DA9150_TAUX_MOD_SHIFT                   1
+#define DA9150_TAUX_MOD_MASK                    BIT(1)
+#define DA9150_TAUX_UPDATE_SHIFT                2
+#define DA9150_TAUX_UPDATE_MASK                 BIT(2)
+
+/* DA9150_TAUX_RELOAD_H = 0x332 */
+#define DA9150_TAUX_RLD_H_SHIFT                 0
+#define DA9150_TAUX_RLD_H_MASK                  (0xff << 0)
+
+/* DA9150_TAUX_RELOAD_L = 0x333 */
+#define DA9150_TAUX_RLD_L_SHIFT                 3
+#define DA9150_TAUX_RLD_L_MASK                  (0x1f << 3)
+
+/* DA9150_TAUX_VALUE_H = 0x334 */
+#define DA9150_TAUX_VAL_H_SHIFT                 0
+#define DA9150_TAUX_VAL_H_MASK                  (0xff << 0)
+
+/* DA9150_TAUX_VALUE_L = 0x335 */
+#define DA9150_TAUX_VAL_L_SHIFT                 3
+#define DA9150_TAUX_VAL_L_MASK                  (0x1f << 3)
+
+/* DA9150_AUX_DATA_0 = 0x338 */
+#define DA9150_AUX_DAT_0_SHIFT                  0
+#define DA9150_AUX_DAT_0_MASK                   (0xff << 0)
+
+/* DA9150_AUX_DATA_1 = 0x339 */
+#define DA9150_AUX_DAT_1_SHIFT                  0
+#define DA9150_AUX_DAT_1_MASK                   (0xff << 0)
+
+/* DA9150_AUX_DATA_2 = 0x33A */
+#define DA9150_AUX_DAT_2_SHIFT                  0
+#define DA9150_AUX_DAT_2_MASK                   (0xff << 0)
+
+/* DA9150_AUX_DATA_3 = 0x33B */
+#define DA9150_AUX_DAT_3_SHIFT                  0
+#define DA9150_AUX_DAT_3_MASK                   (0xff << 0)
+
+/* DA9150_BIF_CTRL = 0x340 */
+#define DA9150_BIF_ISRC_EN_SHIFT                0
+#define DA9150_BIF_ISRC_EN_MASK                 BIT(0)
+
+/* DA9150_TBAT_CTRL_A = 0x342 */
+#define DA9150_TBAT_EN_SHIFT                    0
+#define DA9150_TBAT_EN_MASK                     BIT(0)
+#define DA9150_TBAT_SW1_SHIFT                   1
+#define DA9150_TBAT_SW1_MASK                    BIT(1)
+#define DA9150_TBAT_SW2_SHIFT                   2
+#define DA9150_TBAT_SW2_MASK                    BIT(2)
+
+/* DA9150_TBAT_CTRL_B = 0x343 */
+#define DA9150_TBAT_SW_FRC_SHIFT                0
+#define DA9150_TBAT_SW_FRC_MASK                 BIT(0)
+#define DA9150_TBAT_STAT_SW1_SHIFT              1
+#define DA9150_TBAT_STAT_SW1_MASK               BIT(1)
+#define DA9150_TBAT_STAT_SW2_SHIFT              2
+#define DA9150_TBAT_STAT_SW2_MASK               BIT(2)
+#define DA9150_TBAT_HIGH_CURR_SHIFT             3
+#define DA9150_TBAT_HIGH_CURR_MASK              BIT(3)
+
+/* DA9150_TBAT_RES_A = 0x344 */
+#define DA9150_TBAT_RES_H_SHIFT                 0
+#define DA9150_TBAT_RES_H_MASK                  (0xff << 0)
+
+/* DA9150_TBAT_RES_B = 0x345 */
+#define DA9150_TBAT_RES_DIS_SHIFT               0
+#define DA9150_TBAT_RES_DIS_MASK                BIT(0)
+#define DA9150_TBAT_RES_L_SHIFT                 6
+#define DA9150_TBAT_RES_L_MASK                  (0x03 << 6)
+
+#endif /* __DA9150_REGISTERS_H */
diff --git a/include/linux/mfd/max77686-private.h b/include/linux/mfd/max77686-private.h
index 960b92ad450d..f5043490d67c 100644
--- a/include/linux/mfd/max77686-private.h
+++ b/include/linux/mfd/max77686-private.h
@@ -447,7 +447,6 @@ struct max77686_dev {
         struct regmap_irq_chip_data *rtc_irq_data;
 
         int irq;
-        bool wakeup;
         struct mutex irqlock;
         int irq_masks_cur[MAX77686_IRQ_GROUP_NR];
         int irq_masks_cache[MAX77686_IRQ_GROUP_NR];
diff --git a/include/linux/mfd/max77686.h b/include/linux/mfd/max77686.h
index 553f7d09258a..bb995ab9a575 100644
--- a/include/linux/mfd/max77686.h
+++ b/include/linux/mfd/max77686.h
@@ -119,12 +119,6 @@ enum max77802_regulators {
         MAX77802_REG_MAX,
 };
 
-struct max77686_regulator_data {
-        int id;
-        struct regulator_init_data *initdata;
-        struct device_node *of_node;
-};
-
 enum max77686_opmode {
         MAX77686_OPMODE_NORMAL,
         MAX77686_OPMODE_LP,
@@ -136,26 +130,4 @@ struct max77686_opmode_data {
         int mode;
 };
 
-struct max77686_platform_data {
-        int ono;
-        int wakeup;
-
-        /* ---- PMIC ---- */
-        struct max77686_regulator_data *regulators;
-        int num_regulators;
-
-        struct max77686_opmode_data *opmode_data;
-
-        /*
-         * GPIO-DVS feature is not enabled with the current version of
-         * MAX77686 driver. Buck2/3/4_voltages[0] is used as the default
-         * voltage at probe. DVS/SELB gpios are set as OUTPUT-LOW.
-         */
-        int buck234_gpio_dvs[3]; /* GPIO of [0]DVS1, [1]DVS2, [2]DVS3 */
-        int buck234_gpio_selb[3]; /* [0]SELB2, [1]SELB3, [2]SELB4 */
-        unsigned int buck2_voltage[8]; /* buckx_voltage in uV */
-        unsigned int buck3_voltage[8];
-        unsigned int buck4_voltage[8];
-};
-
 #endif /* __LINUX_MFD_MAX77686_H */
diff --git a/include/linux/mfd/qcom_rpm.h b/include/linux/mfd/qcom_rpm.h
new file mode 100644
index 000000000000..742ebf1b76ca
--- /dev/null
+++ b/include/linux/mfd/qcom_rpm.h
@@ -0,0 +1,13 @@
+#ifndef __QCOM_RPM_H__
+#define __QCOM_RPM_H__
+
+#include <linux/types.h>
+
+struct qcom_rpm;
+
+#define QCOM_RPM_ACTIVE_STATE   0
+#define QCOM_RPM_SLEEP_STATE    1
+
+int qcom_rpm_write(struct qcom_rpm *rpm, int state, int resource, u32 *buf, size_t count);
+
+#endif
diff --git a/include/linux/mfd/rt5033-private.h b/include/linux/mfd/rt5033-private.h
new file mode 100644
index 000000000000..1b63fc2f42d1
--- /dev/null
+++ b/include/linux/mfd/rt5033-private.h
@@ -0,0 +1,260 @@
+/*
+ * MFD core driver for Richtek RT5033
+ *
+ * Copyright (C) 2014 Samsung Electronics, Co., Ltd.
+ * Author: Beomho Seo <beomho.seo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published bythe Free Software Foundation.
+ */
+
+#ifndef __RT5033_PRIVATE_H__
+#define __RT5033_PRIVATE_H__
+
+enum rt5033_reg {
+        RT5033_REG_CHG_STAT             = 0x00,
+        RT5033_REG_CHG_CTRL1            = 0x01,
+        RT5033_REG_CHG_CTRL2            = 0x02,
+        RT5033_REG_DEVICE_ID            = 0x03,
+        RT5033_REG_CHG_CTRL3            = 0x04,
+        RT5033_REG_CHG_CTRL4            = 0x05,
+        RT5033_REG_CHG_CTRL5            = 0x06,
+        RT5033_REG_RT_CTRL0             = 0x07,
+        RT5033_REG_CHG_RESET            = 0x08,
+        /* Reserved 0x09~0x18 */
+        RT5033_REG_RT_CTRL1             = 0x19,
+        /* Reserved 0x1A~0x20 */
+        RT5033_REG_FLED_FUNCTION1       = 0x21,
+        RT5033_REG_FLED_FUNCTION2       = 0x22,
+        RT5033_REG_FLED_STROBE_CTRL1    = 0x23,
+        RT5033_REG_FLED_STROBE_CTRL2    = 0x24,
+        RT5033_REG_FLED_CTRL1           = 0x25,
+        RT5033_REG_FLED_CTRL2           = 0x26,
+        RT5033_REG_FLED_CTRL3           = 0x27,
+        RT5033_REG_FLED_CTRL4           = 0x28,
+        RT5033_REG_FLED_CTRL5           = 0x29,
+        /* Reserved 0x2A~0x40 */
+        RT5033_REG_CTRL                 = 0x41,
+        RT5033_REG_BUCK_CTRL            = 0x42,
+        RT5033_REG_LDO_CTRL             = 0x43,
+        /* Reserved 0x44~0x46 */
+        RT5033_REG_MANUAL_RESET_CTRL    = 0x47,
+        /* Reserved 0x48~0x5F */
+        RT5033_REG_CHG_IRQ1             = 0x60,
+        RT5033_REG_CHG_IRQ2             = 0x61,
+        RT5033_REG_CHG_IRQ3             = 0x62,
+        RT5033_REG_CHG_IRQ1_CTRL        = 0x63,
+        RT5033_REG_CHG_IRQ2_CTRL        = 0x64,
+        RT5033_REG_CHG_IRQ3_CTRL        = 0x65,
+        RT5033_REG_LED_IRQ_STAT         = 0x66,
+        RT5033_REG_LED_IRQ_CTRL         = 0x67,
+        RT5033_REG_PMIC_IRQ_STAT        = 0x68,
+        RT5033_REG_PMIC_IRQ_CTRL        = 0x69,
+        RT5033_REG_SHDN_CTRL            = 0x6A,
+        RT5033_REG_OFF_EVENT            = 0x6B,
+
+        RT5033_REG_END,
+};
+
+/* RT5033 Charger state register */
+#define RT5033_CHG_STAT_MASK            0x20
+#define RT5033_CHG_STAT_DISCHARGING     0x00
+#define RT5033_CHG_STAT_FULL            0x10
+#define RT5033_CHG_STAT_CHARGING        0x20
+#define RT5033_CHG_STAT_NOT_CHARGING    0x30
+#define RT5033_CHG_STAT_TYPE_MASK       0x60
+#define RT5033_CHG_STAT_TYPE_PRE        0x20
+#define RT5033_CHG_STAT_TYPE_FAST       0x60
+
+/* RT5033 CHGCTRL1 register */
+#define RT5033_CHGCTRL1_IAICR_MASK      0xe0
+#define RT5033_CHGCTRL1_MODE_MASK       0x01
+
+/* RT5033 CHGCTRL2 register */
+#define RT5033_CHGCTRL2_CV_MASK         0xfc
+
+/* RT5033 CHGCTRL3 register */
+#define RT5033_CHGCTRL3_CFO_EN_MASK     0x40
+#define RT5033_CHGCTRL3_TIMER_MASK      0x38
+#define RT5033_CHGCTRL3_TIMER_EN_MASK   0x01
+
+/* RT5033 CHGCTRL4 register */
+#define RT5033_CHGCTRL4_EOC_MASK        0x07
+#define RT5033_CHGCTRL4_IPREC_MASK      0x18
+
+/* RT5033 CHGCTRL5 register */
+#define RT5033_CHGCTRL5_VPREC_MASK      0x0f
+#define RT5033_CHGCTRL5_ICHG_MASK       0xf0
+#define RT5033_CHGCTRL5_ICHG_SHIFT      0x04
+#define RT5033_CHG_MAX_CURRENT          0x0d
+
+/* RT5033 RT CTRL1 register */
+#define RT5033_RT_CTRL1_UUG_MASK        0x02
+#define RT5033_RT_HZ_MASK               0x01
+
+/* RT5033 control register */
+#define RT5033_CTRL_FCCM_BUCK_MASK              0x00
+#define RT5033_CTRL_BUCKOMS_MASK                0x01
+#define RT5033_CTRL_LDOOMS_MASK                 0x02
+#define RT5033_CTRL_SLDOOMS_MASK                0x03
+#define RT5033_CTRL_EN_BUCK_MASK                0x04
+#define RT5033_CTRL_EN_LDO_MASK                 0x05
+#define RT5033_CTRL_EN_SAFE_LDO_MASK            0x06
+#define RT5033_CTRL_LDO_SLEEP_MASK              0x07
+
+/* RT5033 BUCK control register */
+#define RT5033_BUCK_CTRL_MASK                   0x1f
+
+/* RT5033 LDO control register */
+#define RT5033_LDO_CTRL_MASK                    0x1f
+
+/* RT5033 charger property - model, manufacturer */
+
+#define RT5033_CHARGER_MODEL    "RT5033WSC Charger"
+#define RT5033_MANUFACTURER     "Richtek Technology Corporation"
+
+/*
+ * RT5033 charger fast-charge current lmits (as in CHGCTRL1 register),
+ * AICR mode limits the input current for example,
+ * the AIRC 100 mode limits the input current to 100 mA.
+ */
+#define RT5033_AICR_100_MODE                    0x20
+#define RT5033_AICR_500_MODE                    0x40
+#define RT5033_AICR_700_MODE                    0x60
+#define RT5033_AICR_900_MODE                    0x80
+#define RT5033_AICR_1500_MODE                   0xc0
+#define RT5033_AICR_2000_MODE                   0xe0
+#define RT5033_AICR_MODE_MASK                   0xe0
+
+/* RT5033 use internal timer need to set time */
+#define RT5033_FAST_CHARGE_TIMER4               0x00
+#define RT5033_FAST_CHARGE_TIMER6               0x01
+#define RT5033_FAST_CHARGE_TIMER8               0x02
+#define RT5033_FAST_CHARGE_TIMER9               0x03
+#define RT5033_FAST_CHARGE_TIMER12              0x04
+#define RT5033_FAST_CHARGE_TIMER14              0x05
+#define RT5033_FAST_CHARGE_TIMER16              0x06
+
+#define RT5033_INT_TIMER_ENABLE                 0x01
+
+/* RT5033 charger termination enable mask */
+#define RT5033_TE_ENABLE_MASK                   0x08
+
+/*
+ * RT5033 charger opa mode. RT50300 have two opa mode charger mode
+ * and boost mode for OTG
+ */
+
+#define RT5033_CHARGER_MODE                     0x00
+#define RT5033_BOOST_MODE                       0x01
+
+/* RT5033 charger termination enable */
+#define RT5033_TE_ENABLE                        0x08
+
+/* RT5033 charger CFO enable */
+#define RT5033_CFO_ENABLE                       0x40
+
+/* RT5033 charger constant charge voltage (as in CHGCTRL2 register), uV */
+#define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MIN  3650000U
+#define RT5033_CHARGER_CONST_VOLTAGE_STEP_NUM   25000U
+#define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MAX  4400000U
+
+/* RT5033 charger pre-charge current limits (as in CHGCTRL4 register), uA */
+#define RT5033_CHARGER_PRE_CURRENT_LIMIT_MIN    350000U
+#define RT5033_CHARGER_PRE_CURRENT_STEP_NUM     100000U
+#define RT5033_CHARGER_PRE_CURRENT_LIMIT_MAX    650000U
+
+/* RT5033 charger fast-charge current (as in CHGCTRL5 register), uA */
+#define RT5033_CHARGER_FAST_CURRENT_MIN         700000U
+#define RT5033_CHARGER_FAST_CURRENT_STEP_NUM    100000U
+#define RT5033_CHARGER_FAST_CURRENT_MAX         2000000U
+
+/*
+ * RT5033 charger const-charge end of charger current (
+ * as in CHGCTRL4 register), uA
+ */
+#define RT5033_CHARGER_EOC_MIN                  150000U
+#define RT5033_CHARGER_EOC_REF                  300000U
+#define RT5033_CHARGER_EOC_STEP_NUM1            50000U
+#define RT5033_CHARGER_EOC_STEP_NUM2            100000U
+#define RT5033_CHARGER_EOC_MAX                  600000U
+
+/*
+ * RT5033 charger pre-charge threshold volt limits
+ * (as in CHGCTRL5 register), uV
+ */
+
+#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MIN  2300000U
+#define RT5033_CHARGER_PRE_THRESHOLD_STEP_NUM   100000U
+#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MAX  3800000U
+
+/*
+ * RT5033 charger enable UUG, If UUG enable MOS auto control by H/W charger
+ * circuit.
+ */
+#define RT5033_CHARGER_UUG_ENABLE               0x02
+
+/* RT5033 charger High impedance mode */
+#define RT5033_CHARGER_HZ_DISABLE               0x00
+#define RT5033_CHARGER_HZ_ENABLE                0x01
+
+/* RT5033 regulator BUCK output voltage uV */
+#define RT5033_REGULATOR_BUCK_VOLTAGE_MIN               1000000U
+#define RT5033_REGULATOR_BUCK_VOLTAGE_MAX               3000000U
+#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP              100000U
+#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP_NUM          32
+
+/* RT5033 regulator LDO output voltage uV */
+#define RT5033_REGULATOR_LDO_VOLTAGE_MIN                1200000U
+#define RT5033_REGULATOR_LDO_VOLTAGE_MAX                3000000U
+#define RT5033_REGULATOR_LDO_VOLTAGE_STEP               100000U
+#define RT5033_REGULATOR_LDO_VOLTAGE_STEP_NUM           32
+
+/* RT5033 regulator SAFE LDO output voltage uV */
+#define RT5033_REGULATOR_SAFE_LDO_VOLTAGE               4900000U
+
+enum rt5033_fuel_reg {
+        RT5033_FUEL_REG_OCV_H           = 0x00,
+        RT5033_FUEL_REG_OCV_L           = 0x01,
+        RT5033_FUEL_REG_VBAT_H          = 0x02,
+        RT5033_FUEL_REG_VBAT_L          = 0x03,
+        RT5033_FUEL_REG_SOC_H           = 0x04,
+        RT5033_FUEL_REG_SOC_L           = 0x05,
+        RT5033_FUEL_REG_CTRL_H          = 0x06,
+        RT5033_FUEL_REG_CTRL_L          = 0x07,
+        RT5033_FUEL_REG_CRATE           = 0x08,
+        RT5033_FUEL_REG_DEVICE_ID       = 0x09,
+        RT5033_FUEL_REG_AVG_VOLT_H      = 0x0A,
+        RT5033_FUEL_REG_AVG_VOLT_L      = 0x0B,
+        RT5033_FUEL_REG_CONFIG_H        = 0x0C,
+        RT5033_FUEL_REG_CONFIG_L        = 0x0D,
+        /* Reserved 0x0E~0x0F */
+        RT5033_FUEL_REG_IRQ_CTRL        = 0x10,
+        RT5033_FUEL_REG_IRQ_FLAG        = 0x11,
+        RT5033_FUEL_VMIN                = 0x12,
+        RT5033_FUEL_SMIN                = 0x13,
+        /* Reserved 0x14~0x1F */
+        RT5033_FUEL_VGCOMP1             = 0x20,
+        RT5033_FUEL_VGCOMP2             = 0x21,
+        RT5033_FUEL_VGCOMP3             = 0x22,
+        RT5033_FUEL_VGCOMP4             = 0x23,
+        /* Reserved 0x24~0xFD */
+        RT5033_FUEL_MFA_H               = 0xFE,
+        RT5033_FUEL_MFA_L               = 0xFF,
+
+        RT5033_FUEL_REG_END,
+};
+
+/* RT5033 fuel gauge battery present property */
+#define RT5033_FUEL_BAT_PRESENT         0x02
+
+/* RT5033 PMIC interrupts */
+#define RT5033_PMIC_IRQ_BUCKOCP         2
+#define RT5033_PMIC_IRQ_BUCKLV          3
+#define RT5033_PMIC_IRQ_SAFELDOLV       4
+#define RT5033_PMIC_IRQ_LDOLV           5
+#define RT5033_PMIC_IRQ_OT              6
+#define RT5033_PMIC_IRQ_VDDA_UV         7
+
+#endif /* __RT5033_PRIVATE_H__ */
diff --git a/include/linux/mfd/rt5033.h b/include/linux/mfd/rt5033.h
new file mode 100644
index 000000000000..010cff49a98e
--- /dev/null
+++ b/include/linux/mfd/rt5033.h
@@ -0,0 +1,62 @@
+/*
+ * MFD core driver for the RT5033
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ * Author: Beomho Seo <beomho.seo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published bythe Free Software Foundation.
+ */
+
+#ifndef __RT5033_H__
+#define __RT5033_H__
+
+#include <linux/regulator/consumer.h>
+#include <linux/i2c.h>
+#include <linux/regmap.h>
+#include <linux/power_supply.h>
+
+/* RT5033 regulator IDs */
+enum rt5033_regulators {
+        RT5033_BUCK = 0,
+        RT5033_LDO,
+        RT5033_SAFE_LDO,
+
+        RT5033_REGULATOR_NUM,
+};
+
+struct rt5033_dev {
+        struct device *dev;
+
+        struct regmap *regmap;
+        struct regmap_irq_chip_data *irq_data;
+        int irq;
+        bool wakeup;
+};
+
+struct rt5033_battery {
+        struct i2c_client       *client;
+        struct rt5033_dev       *rt5033;
+        struct regmap           *regmap;
+        struct power_supply     psy;
+};
+
+/* RT5033 charger platform data */
+struct rt5033_charger_data {
+        unsigned int pre_uamp;
+        unsigned int pre_uvolt;
+        unsigned int const_uvolt;
+        unsigned int eoc_uamp;
+        unsigned int fast_uamp;
+};
+
+struct rt5033_charger {
+        struct device           *dev;
+        struct rt5033_dev       *rt5033;
+        struct power_supply     psy;
+
+        struct rt5033_charger_data      *chg;
+};
+
+#endif /* __RT5033_H__ */