5 files changed, 201 insertions, 8 deletions

diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 9c7f5807824b..dd7adff76e81 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -152,7 +152,7 @@ struct clk {
                 },                                              \
                 .reg = _reg,                                    \
                 .shift = _shift,                                \
-                .width = _width,                                \
+                .mask = BIT(_width) - 1,                        \
                 .flags = _mux_flags,                            \
                 .lock = _lock,                                  \
         };                                                      \
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7f197d7addb0..11860985fecb 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -45,6 +45,14 @@ struct clk_hw;
  *              undo any work done in the @prepare callback. Called with
  *              prepare_lock held.
  *
+ * @is_prepared: Queries the hardware to determine if the clock is prepared.
+ *              This function is allowed to sleep. Optional, if this op is not
+ *              set then the prepare count will be used.
+ *
+ * @unprepare_unused: Unprepare the clock atomically.  Only called from
+ *              clk_disable_unused for prepare clocks with special needs.
+ *              Called with prepare mutex held. This function may sleep.
+ *
  * @enable:     Enable the clock atomically. This must not return until the
  *              clock is generating a valid clock signal, usable by consumer
  *              devices. Called with enable_lock held. This function must not
@@ -108,6 +116,8 @@ struct clk_hw;
 struct clk_ops {
         int             (*prepare)(struct clk_hw *hw);
         void            (*unprepare)(struct clk_hw *hw);
+        int             (*is_prepared)(struct clk_hw *hw);
+        void            (*unprepare_unused)(struct clk_hw *hw);
         int             (*enable)(struct clk_hw *hw);
         void            (*disable)(struct clk_hw *hw);
         int             (*is_enabled)(struct clk_hw *hw);
@@ -239,9 +249,14 @@ struct clk_div_table {
  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
  *      register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is
  *      the raw value read from the register, with the value of zero considered
- *      invalid
+ *      invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
  *      the hardware register
+ * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
+ *      CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
+ *      Some hardware implementations gracefully handle this case and allow a
+ *      zero divisor by not modifying their input clock
+ *      (divide by one / bypass).
  */
 struct clk_divider {
         struct clk_hw   hw;
@@ -255,6 +270,7 @@ struct clk_divider {
 
 #define CLK_DIVIDER_ONE_BASED           BIT(0)
 #define CLK_DIVIDER_POWER_OF_TWO        BIT(1)
+#define CLK_DIVIDER_ALLOW_ZERO          BIT(2)
 
 extern const struct clk_ops clk_divider_ops;
 struct clk *clk_register_divider(struct device *dev, const char *name,
@@ -274,7 +290,7 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
  * @reg:        register controlling multiplexer
  * @shift:      shift to multiplexer bit field
  * @width:      width of mutliplexer bit field
- * @num_clks:   number of parent clocks
+ * @flags:      hardware-specific flags
  * @lock:       register lock
  *
  * Clock with multiple selectable parents.  Implements .get_parent, .set_parent
@@ -287,8 +303,9 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
 struct clk_mux {
         struct clk_hw   hw;
         void __iomem    *reg;
+        u32             *table;
+        u32             mask;
         u8              shift;
-        u8              width;
         u8              flags;
         spinlock_t      *lock;
 };
@@ -297,11 +314,19 @@ struct clk_mux {
 #define CLK_MUX_INDEX_BIT               BIT(1)
 
 extern const struct clk_ops clk_mux_ops;
+
 struct clk *clk_register_mux(struct device *dev, const char *name,
                 const char **parent_names, u8 num_parents, unsigned long flags,
                 void __iomem *reg, u8 shift, u8 width,
                 u8 clk_mux_flags, spinlock_t *lock);
 
+struct clk *clk_register_mux_table(struct device *dev, const char *name,
+                const char **parent_names, u8 num_parents, unsigned long flags,
+                void __iomem *reg, u8 shift, u32 mask,
+                u8 clk_mux_flags, u32 *table, spinlock_t *lock);
+
+void of_fixed_factor_clk_setup(struct device_node *node);
+
 /**
  * struct clk_fixed_factor - fixed multiplier and divider clock
  *
@@ -325,6 +350,37 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
                 const char *parent_name, unsigned long flags,
                 unsigned int mult, unsigned int div);
 
+/***
+ * struct clk_composite - aggregate clock of mux, divider and gate clocks
+ *
+ * @hw:         handle between common and hardware-specific interfaces
+ * @mux_hw:     handle between composite and hardware-specific mux clock
+ * @rate_hw:    handle between composite and hardware-specific rate clock
+ * @gate_hw:    handle between composite and hardware-specific gate clock
+ * @mux_ops:    clock ops for mux
+ * @rate_ops:   clock ops for rate
+ * @gate_ops:   clock ops for gate
+ */
+struct clk_composite {
+        struct clk_hw   hw;
+        struct clk_ops  ops;
+
+        struct clk_hw   *mux_hw;
+        struct clk_hw   *rate_hw;
+        struct clk_hw   *gate_hw;
+
+        const struct clk_ops    *mux_ops;
+        const struct clk_ops    *rate_ops;
+        const struct clk_ops    *gate_ops;
+};
+
+struct clk *clk_register_composite(struct device *dev, const char *name,
+                const char **parent_names, int num_parents,
+                struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
+                struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
+                struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
+                unsigned long flags);
+
 /**
  * clk_register - allocate a new clock, register it and return an opaque cookie
  * @dev: device that is registering this clock
@@ -351,6 +407,7 @@ unsigned int __clk_get_enable_count(struct clk *clk);
 unsigned int __clk_get_prepare_count(struct clk *clk);
 unsigned long __clk_get_rate(struct clk *clk);
 unsigned long __clk_get_flags(struct clk *clk);
+bool __clk_is_prepared(struct clk *clk);
 bool __clk_is_enabled(struct clk *clk);
 struct clk *__clk_lookup(const char *name);
 
diff --git a/include/linux/clk.h b/include/linux/clk.h
index b3ac22d0fc1f..9a6d04524b1a 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -28,16 +28,16 @@ struct clk;
  * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
  *     to indicate that the rate change will proceed.  Drivers must
  *     immediately terminate any operations that will be affected by the
- *     rate change.  Callbacks may either return NOTIFY_DONE or
- *     NOTIFY_STOP.
+ *     rate change.  Callbacks may either return NOTIFY_DONE, NOTIFY_OK,
+ *     NOTIFY_STOP or NOTIFY_BAD.
  *
  * ABORT_RATE_CHANGE: called if the rate change failed for some reason
  *     after PRE_RATE_CHANGE.  In this case, all registered notifiers on
  *     the clk will be called with ABORT_RATE_CHANGE. Callbacks must
- *     always return NOTIFY_DONE.
+ *     always return NOTIFY_DONE or NOTIFY_OK.
  *
  * POST_RATE_CHANGE - called after the clk rate change has successfully
- *     completed.  Callbacks must always return NOTIFY_DONE.
+ *     completed.  Callbacks must always return NOTIFY_DONE or NOTIFY_OK.
  *
  */
 #define PRE_RATE_CHANGE                 BIT(0)
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
new file mode 100644
index 000000000000..e074fdd5a236
--- /dev/null
+++ b/include/linux/clk/sunxi.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_CLK_SUNXI_H_
+#define __LINUX_CLK_SUNXI_H_
+
+void __init sunxi_init_clocks(void);
+
+#endif
diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h
new file mode 100644
index 000000000000..92dabcaf6499
--- /dev/null
+++ b/include/linux/platform_data/si5351.h
@@ -0,0 +1,114 @@
+/*
+ * Si5351A/B/C programmable clock generator platform_data.
+ */
+
+#ifndef __LINUX_PLATFORM_DATA_SI5351_H__
+#define __LINUX_PLATFORM_DATA_SI5351_H__
+
+struct clk;
+
+/**
+ * enum si5351_variant - SiLabs Si5351 chip variant
+ * @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input)
+ * @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input)
+ * @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input)
+ * @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input)
+ */
+enum si5351_variant {
+        SI5351_VARIANT_A = 1,
+        SI5351_VARIANT_A3 = 2,
+        SI5351_VARIANT_B = 3,
+        SI5351_VARIANT_C = 4,
+};
+
+/**
+ * enum si5351_pll_src - Si5351 pll clock source
+ * @SI5351_PLL_SRC_DEFAULT: default, do not change eeprom config
+ * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input
+ * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only)
+ */
+enum si5351_pll_src {
+        SI5351_PLL_SRC_DEFAULT = 0,
+        SI5351_PLL_SRC_XTAL = 1,
+        SI5351_PLL_SRC_CLKIN = 2,
+};
+
+/**
+ * enum si5351_multisynth_src - Si5351 multisynth clock source
+ * @SI5351_MULTISYNTH_SRC_DEFAULT: default, do not change eeprom config
+ * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0
+ * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO
+ */
+enum si5351_multisynth_src {
+        SI5351_MULTISYNTH_SRC_DEFAULT = 0,
+        SI5351_MULTISYNTH_SRC_VCO0 = 1,
+        SI5351_MULTISYNTH_SRC_VCO1 = 2,
+};
+
+/**
+ * enum si5351_clkout_src - Si5351 clock output clock source
+ * @SI5351_CLKOUT_SRC_DEFAULT: default, do not change eeprom config
+ * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
+ * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4)
+ *                                or 4 (N>=4)
+ * @SI5351_CLKOUT_SRC_XTAL: clkout N source clock is XTAL
+ * @SI5351_CLKOUT_SRC_CLKIN: clkout N source clock is CLKIN (Si5351C only)
+ */
+enum si5351_clkout_src {
+        SI5351_CLKOUT_SRC_DEFAULT = 0,
+        SI5351_CLKOUT_SRC_MSYNTH_N = 1,
+        SI5351_CLKOUT_SRC_MSYNTH_0_4 = 2,
+        SI5351_CLKOUT_SRC_XTAL = 3,
+        SI5351_CLKOUT_SRC_CLKIN = 4,
+};
+
+/**
+ * enum si5351_drive_strength - Si5351 clock output drive strength
+ * @SI5351_DRIVE_DEFAULT: default, do not change eeprom config
+ * @SI5351_DRIVE_2MA: 2mA clock output drive strength
+ * @SI5351_DRIVE_4MA: 4mA clock output drive strength
+ * @SI5351_DRIVE_6MA: 6mA clock output drive strength
+ * @SI5351_DRIVE_8MA: 8mA clock output drive strength
+ */
+enum si5351_drive_strength {
+        SI5351_DRIVE_DEFAULT = 0,
+        SI5351_DRIVE_2MA = 2,
+        SI5351_DRIVE_4MA = 4,
+        SI5351_DRIVE_6MA = 6,
+        SI5351_DRIVE_8MA = 8,
+};
+
+/**
+ * struct si5351_clkout_config - Si5351 clock output configuration
+ * @clkout: clkout number
+ * @multisynth_src: multisynth source clock
+ * @clkout_src: clkout source clock
+ * @pll_master: if true, clkout can also change pll rate
+ * @drive: output drive strength
+ * @rate: initial clkout rate, or default if 0
+ */
+struct si5351_clkout_config {
+        enum si5351_multisynth_src multisynth_src;
+        enum si5351_clkout_src clkout_src;
+        enum si5351_drive_strength drive;
+        bool pll_master;
+        unsigned long rate;
+};
+
+/**
+ * struct si5351_platform_data - Platform data for the Si5351 clock driver
+ * @variant: Si5351 chip variant
+ * @clk_xtal: xtal input clock
+ * @clk_clkin: clkin input clock
+ * @pll_src: array of pll source clock setting
+ * @clkout: array of clkout configuration
+ */
+struct si5351_platform_data {
+        enum si5351_variant variant;
+        struct clk *clk_xtal;
+        struct clk *clk_clkin;
+        enum si5351_pll_src pll_src[2];
+        struct si5351_clkout_config clkout[8];
+};
+
+#endif