12 files changed, 303 insertions, 64 deletions

diff --git a/include/dt-bindings/clock/bcm21664.h b/include/dt-bindings/clock/bcm21664.h
new file mode 100644
index 000000000000..5a7f0e4750a8
--- /dev/null
+++ b/include/dt-bindings/clock/bcm21664.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ * Copyright 2013 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CLOCK_BCM21664_H
+#define _CLOCK_BCM21664_H
+
+/*
+ * This file defines the values used to specify clocks provided by
+ * the clock control units (CCUs) on Broadcom BCM21664 family SoCs.
+ */
+
+/* bcm21664 CCU device tree "compatible" strings */
+#define BCM21664_DT_ROOT_CCU_COMPAT     "brcm,bcm21664-root-ccu"
+#define BCM21664_DT_AON_CCU_COMPAT      "brcm,bcm21664-aon-ccu"
+#define BCM21664_DT_MASTER_CCU_COMPAT   "brcm,bcm21664-master-ccu"
+#define BCM21664_DT_SLAVE_CCU_COMPAT    "brcm,bcm21664-slave-ccu"
+
+/* root CCU clock ids */
+
+#define BCM21664_ROOT_CCU_FRAC_1M               0
+#define BCM21664_ROOT_CCU_CLOCK_COUNT           1
+
+/* aon CCU clock ids */
+
+#define BCM21664_AON_CCU_HUB_TIMER              0
+#define BCM21664_AON_CCU_CLOCK_COUNT            1
+
+/* master CCU clock ids */
+
+#define BCM21664_MASTER_CCU_SDIO1               0
+#define BCM21664_MASTER_CCU_SDIO2               1
+#define BCM21664_MASTER_CCU_SDIO3               2
+#define BCM21664_MASTER_CCU_SDIO4               3
+#define BCM21664_MASTER_CCU_SDIO1_SLEEP         4
+#define BCM21664_MASTER_CCU_SDIO2_SLEEP         5
+#define BCM21664_MASTER_CCU_SDIO3_SLEEP         6
+#define BCM21664_MASTER_CCU_SDIO4_SLEEP         7
+#define BCM21664_MASTER_CCU_CLOCK_COUNT         8
+
+/* slave CCU clock ids */
+
+#define BCM21664_SLAVE_CCU_UARTB                0
+#define BCM21664_SLAVE_CCU_UARTB2               1
+#define BCM21664_SLAVE_CCU_UARTB3               2
+#define BCM21664_SLAVE_CCU_BSC1                 3
+#define BCM21664_SLAVE_CCU_BSC2                 4
+#define BCM21664_SLAVE_CCU_BSC3                 5
+#define BCM21664_SLAVE_CCU_BSC4                 6
+#define BCM21664_SLAVE_CCU_CLOCK_COUNT          7
+
+#endif /* _CLOCK_BCM21664_H */
diff --git a/include/dt-bindings/clock/bcm281xx.h b/include/dt-bindings/clock/bcm281xx.h
index e0096940886d..a763460cf1af 100644
--- a/include/dt-bindings/clock/bcm281xx.h
+++ b/include/dt-bindings/clock/bcm281xx.h
@@ -20,6 +20,18 @@
  * the clock control units (CCUs) on Broadcom BCM281XX family SoCs.
  */
 
+/*
+ * These are the bcm281xx CCU device tree "compatible" strings.
+ * We're stuck with using "bcm11351" in the string because wild
+ * cards aren't allowed, and that name was the first one defined
+ * in this family of devices.
+ */
+#define BCM281XX_DT_ROOT_CCU_COMPAT     "brcm,bcm11351-root-ccu"
+#define BCM281XX_DT_AON_CCU_COMPAT      "brcm,bcm11351-aon-ccu"
+#define BCM281XX_DT_HUB_CCU_COMPAT      "brcm,bcm11351-hub-ccu"
+#define BCM281XX_DT_MASTER_CCU_COMPAT   "brcm,bcm11351-master-ccu"
+#define BCM281XX_DT_SLAVE_CCU_COMPAT    "brcm,bcm11351-slave-ccu"
+
 /* root CCU clock ids */
 
 #define BCM281XX_ROOT_CCU_FRAC_1M               0
diff --git a/include/dt-bindings/clock/hix5hd2-clock.h b/include/dt-bindings/clock/hix5hd2-clock.h
new file mode 100644
index 000000000000..aad579a75802
--- /dev/null
+++ b/include/dt-bindings/clock/hix5hd2-clock.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2014 Linaro Ltd.
+ * Copyright (c) 2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef __DTS_HIX5HD2_CLOCK_H
+#define __DTS_HIX5HD2_CLOCK_H
+
+/* fixed rate */
+#define HIX5HD2_FIXED_1200M             1
+#define HIX5HD2_FIXED_400M              2
+#define HIX5HD2_FIXED_48M               3
+#define HIX5HD2_FIXED_24M               4
+#define HIX5HD2_FIXED_600M              5
+#define HIX5HD2_FIXED_300M              6
+#define HIX5HD2_FIXED_75M               7
+#define HIX5HD2_FIXED_200M              8
+#define HIX5HD2_FIXED_100M              9
+#define HIX5HD2_FIXED_40M               10
+#define HIX5HD2_FIXED_150M              11
+#define HIX5HD2_FIXED_1728M             12
+#define HIX5HD2_FIXED_28P8M             13
+#define HIX5HD2_FIXED_432M              14
+#define HIX5HD2_FIXED_345P6M            15
+#define HIX5HD2_FIXED_288M              16
+#define HIX5HD2_FIXED_60M               17
+#define HIX5HD2_FIXED_750M              18
+#define HIX5HD2_FIXED_500M              19
+#define HIX5HD2_FIXED_54M               20
+#define HIX5HD2_FIXED_27M               21
+#define HIX5HD2_FIXED_1500M             22
+#define HIX5HD2_FIXED_375M              23
+#define HIX5HD2_FIXED_187M              24
+#define HIX5HD2_FIXED_250M              25
+#define HIX5HD2_FIXED_125M              26
+#define HIX5HD2_FIXED_2P02M             27
+#define HIX5HD2_FIXED_50M               28
+#define HIX5HD2_FIXED_25M               29
+#define HIX5HD2_FIXED_83M               30
+
+/* mux clocks */
+#define HIX5HD2_SFC_MUX                 64
+#define HIX5HD2_MMC_MUX                 65
+#define HIX5HD2_FEPHY_MUX               66
+
+/* gate clocks */
+#define HIX5HD2_SFC_RST                 128
+#define HIX5HD2_SFC_CLK                 129
+#define HIX5HD2_MMC_CIU_CLK             130
+#define HIX5HD2_MMC_BIU_CLK             131
+#define HIX5HD2_MMC_CIU_RST             132
+
+#define HIX5HD2_NR_CLKS                 256
+#endif  /* __DTS_HIX5HD2_CLOCK_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8960.h b/include/dt-bindings/clock/qcom,gcc-msm8960.h
index 03bbf49d43b7..f9f547146a15 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8960.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h
@@ -51,7 +51,7 @@
 #define QDSS_TSCTR_CLK                          34
 #define SFAB_ADM0_M0_A_CLK                      35
 #define SFAB_ADM0_M1_A_CLK                      36
-#define SFAB_ADM0_M2_A_CLK                      37
+#define SFAB_ADM0_M2_H_CLK                      37
 #define ADM0_CLK                                38
 #define ADM0_PBUS_CLK                           39
 #define MSS_XPU_CLK                             40
@@ -99,7 +99,7 @@
 #define CFPB2_H_CLK                             82
 #define SFAB_CFPB_M_H_CLK                       83
 #define CFPB_MASTER_H_CLK                       84
-#define SFAB_CFPB_S_HCLK                        85
+#define SFAB_CFPB_S_H_CLK                       85
 #define CFPB_SPLITTER_H_CLK                     86
 #define TSIF_H_CLK                              87
 #define TSIF_INACTIVITY_TIMERS_CLK              88
@@ -110,7 +110,6 @@
 #define CE1_SLEEP_CLK                           93
 #define CE2_H_CLK                               94
 #define CE2_CORE_CLK                            95
-#define CE2_SLEEP_CLK                           96
 #define SFPB_H_CLK_SRC                          97
 #define SFPB_H_CLK                              98
 #define SFAB_SFPB_M_H_CLK                       99
@@ -252,7 +251,7 @@
 #define MSS_S_H_CLK                             235
 #define MSS_CXO_SRC_CLK                         236
 #define SATA_H_CLK                              237
-#define SATA_SRC_CLK                            238
+#define SATA_CLK_SRC                            238
 #define SATA_RXOOB_CLK                          239
 #define SATA_PMALIVE_CLK                        240
 #define SATA_PHY_REF_CLK                        241
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8974.h b/include/dt-bindings/clock/qcom,gcc-msm8974.h
index 223ca174d9d3..51e51c860fe6 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8974.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8974.h
@@ -316,5 +316,9 @@
 #define GCC_CE2_CLK_SLEEP_ENA                                   299
 #define GCC_CE2_AXI_CLK_SLEEP_ENA                               300
 #define GCC_CE2_AHB_CLK_SLEEP_ENA                               301
+#define GPLL4                                                   302
+#define GPLL4_VOTE                                              303
+#define GCC_SDCC1_CDCCAL_SLEEP_CLK                              304
+#define GCC_SDCC1_CDCCAL_FF_CLK                                 305
 
 #endif
diff --git a/include/dt-bindings/clock/r8a7779-clock.h b/include/dt-bindings/clock/r8a7779-clock.h
new file mode 100644
index 000000000000..381a6114237a
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7779-clock.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2013  Horms Solutions Ltd.
+ *
+ * Contact: Simon Horman <horms@verge.net.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__
+#define __DT_BINDINGS_CLOCK_R8A7779_H__
+
+/* CPG */
+#define R8A7779_CLK_PLLA        0
+#define R8A7779_CLK_Z           1
+#define R8A7779_CLK_ZS          2
+#define R8A7779_CLK_S           3
+#define R8A7779_CLK_S1          4
+#define R8A7779_CLK_P           5
+#define R8A7779_CLK_B           6
+#define R8A7779_CLK_OUT         7
+
+/* MSTP 0 */
+#define R8A7779_CLK_HSPI        7
+#define R8A7779_CLK_TMU2        14
+#define R8A7779_CLK_TMU1        15
+#define R8A7779_CLK_TMU0        16
+#define R8A7779_CLK_HSCIF1      18
+#define R8A7779_CLK_HSCIF0      19
+#define R8A7779_CLK_SCIF5       21
+#define R8A7779_CLK_SCIF4       22
+#define R8A7779_CLK_SCIF3       23
+#define R8A7779_CLK_SCIF2       24
+#define R8A7779_CLK_SCIF1       25
+#define R8A7779_CLK_SCIF0       26
+#define R8A7779_CLK_I2C3        27
+#define R8A7779_CLK_I2C2        28
+#define R8A7779_CLK_I2C1        29
+#define R8A7779_CLK_I2C0        30
+
+/* MSTP 1 */
+#define R8A7779_CLK_USB01       0
+#define R8A7779_CLK_USB2        1
+#define R8A7779_CLK_DU          3
+#define R8A7779_CLK_VIN2        8
+#define R8A7779_CLK_VIN1        9
+#define R8A7779_CLK_VIN0        10
+#define R8A7779_CLK_ETHER       14
+#define R8A7779_CLK_SATA        15
+#define R8A7779_CLK_PCIE        16
+#define R8A7779_CLK_VIN3        20
+
+/* MSTP 3 */
+#define R8A7779_CLK_SDHI3       20
+#define R8A7779_CLK_SDHI2       21
+#define R8A7779_CLK_SDHI1       22
+#define R8A7779_CLK_SDHI0       23
+#define R8A7779_CLK_MMC1        30
+#define R8A7779_CLK_MMC0        31
+
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index 6d0d8d8ef31e..fc12621fb432 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -337,6 +337,7 @@
 #define TEGRA114_CLK_CLK_OUT_3_MUX 308
 #define TEGRA114_CLK_DSIA_MUX 309
 #define TEGRA114_CLK_DSIB_MUX 310
-#define TEGRA114_CLK_CLK_MAX 311
+#define TEGRA114_CLK_XUSB_SS_DIV2 311
+#define TEGRA114_CLK_CLK_MAX 312
 
 #endif  /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
index 433528ab5161..8a4c5892890f 100644
--- a/include/dt-bindings/clock/tegra124-car.h
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -336,6 +336,7 @@
 #define TEGRA124_CLK_DSIA_MUX 309
 #define TEGRA124_CLK_DSIB_MUX 310
 #define TEGRA124_CLK_SOR0_LVDS 311
-#define TEGRA124_CLK_CLK_MAX 312
+#define TEGRA124_CLK_XUSB_SS_DIV2 312
+#define TEGRA124_CLK_CLK_MAX 313
 
 #endif  /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8960.h b/include/dt-bindings/reset/qcom,gcc-msm8960.h
index a840e680323c..07edd0e65eed 100644
--- a/include/dt-bindings/reset/qcom,gcc-msm8960.h
+++ b/include/dt-bindings/reset/qcom,gcc-msm8960.h
@@ -58,7 +58,7 @@
 #define PPSS_PROC_RESET                                 41
 #define PPSS_RESET                                      42
 #define DMA_BAM_RESET                                   43
-#define SIC_TIC_RESET                                   44
+#define SPS_TIC_H_RESET                                 44
 #define SLIMBUS_H_RESET                                 45
 #define SFAB_CFPB_M_RESET                               46
 #define SFAB_CFPB_S_RESET                               47
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index f295bab1865d..0c287dbbb144 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -40,14 +40,14 @@ struct dentry;
  * through the clk_* api.
  *
  * @prepare:    Prepare the clock for enabling. This must not return until
- *              the clock is fully prepared, and it's safe to call clk_enable.
- *              This callback is intended to allow clock implementations to
- *              do any initialisation that may sleep. Called with
- *              prepare_lock held.
+ *              the clock is fully prepared, and it's safe to call clk_enable.
+ *              This callback is intended to allow clock implementations to
+ *              do any initialisation that may sleep. Called with
+ *              prepare_lock held.
  *
  * @unprepare:  Release the clock from its prepared state. This will typically
- *              undo any work done in the @prepare callback. Called with
- *              prepare_lock held.
+ *              undo any work done in the @prepare callback. Called with
+ *              prepare_lock held.
  *
  * @is_prepared: Queries the hardware to determine if the clock is prepared.
  *              This function is allowed to sleep. Optional, if this op is not
@@ -58,16 +58,16 @@ struct dentry;
  *              Called with prepare mutex held. This function may sleep.
  *
  * @enable:     Enable the clock atomically. This must not return until the
- *              clock is generating a valid clock signal, usable by consumer
- *              devices. Called with enable_lock held. This function must not
- *              sleep.
+ *              clock is generating a valid clock signal, usable by consumer
+ *              devices. Called with enable_lock held. This function must not
+ *              sleep.
  *
  * @disable:    Disable the clock atomically. Called with enable_lock held.
- *              This function must not sleep.
+ *              This function must not sleep.
  *
  * @is_enabled: Queries the hardware to determine if the clock is enabled.
- *              This function must not sleep. Optional, if this op is not
- *              set then the enable count will be used.
+ *              This function must not sleep. Optional, if this op is not
+ *              set then the enable count will be used.
  *
  * @disable_unused: Disable the clock atomically.  Only called from
  *              clk_disable_unused for gate clocks with special needs.
@@ -75,34 +75,35 @@ struct dentry;
  *              sleep.
  *
  * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
- *              parent rate is an input parameter.  It is up to the caller to
- *              ensure that the prepare_mutex is held across this call.
- *              Returns the calculated rate.  Optional, but recommended - if
- *              this op is not set then clock rate will be initialized to 0.
+ *              parent rate is an input parameter.  It is up to the caller to
+ *              ensure that the prepare_mutex is held across this call.
+ *              Returns the calculated rate.  Optional, but recommended - if
+ *              this op is not set then clock rate will be initialized to 0.
  *
  * @round_rate: Given a target rate as input, returns the closest rate actually
- *              supported by the clock.
+ *              supported by the clock. The parent rate is an input/output
+ *              parameter.
  *
  * @determine_rate: Given a target rate as input, returns the closest rate
  *              actually supported by the clock, and optionally the parent clock
  *              that should be used to provide the clock rate.
  *
- * @get_parent: Queries the hardware to determine the parent of a clock.  The
- *              return value is a u8 which specifies the index corresponding to
- *              the parent clock.  This index can be applied to either the
- *              .parent_names or .parents arrays.  In short, this function
- *              translates the parent value read from hardware into an array
- *              index.  Currently only called when the clock is initialized by
- *              __clk_init.  This callback is mandatory for clocks with
- *              multiple parents.  It is optional (and unnecessary) for clocks
- *              with 0 or 1 parents.
- *
  * @set_parent: Change the input source of this clock; for clocks with multiple
- *              possible parents specify a new parent by passing in the index
- *              as a u8 corresponding to the parent in either the .parent_names
- *              or .parents arrays.  This function in affect translates an
- *              array index into the value programmed into the hardware.
- *              Returns 0 on success, -EERROR otherwise.
+ *              possible parents specify a new parent by passing in the index
+ *              as a u8 corresponding to the parent in either the .parent_names
+ *              or .parents arrays.  This function in affect translates an
+ *              array index into the value programmed into the hardware.
+ *              Returns 0 on success, -EERROR otherwise.
+ *
+ * @get_parent: Queries the hardware to determine the parent of a clock.  The
+ *              return value is a u8 which specifies the index corresponding to
+ *              the parent clock.  This index can be applied to either the
+ *              .parent_names or .parents arrays.  In short, this function
+ *              translates the parent value read from hardware into an array
+ *              index.  Currently only called when the clock is initialized by
+ *              __clk_init.  This callback is mandatory for clocks with
+ *              multiple parents.  It is optional (and unnecessary) for clocks
+ *              with 0 or 1 parents.
  *
  * @set_rate:   Change the rate of this clock. The requested rate is specified
  *              by the second argument, which should typically be the return
@@ -110,13 +111,6 @@ struct dentry;
  *              which is likely helpful for most .set_rate implementation.
  *              Returns 0 on success, -EERROR otherwise.
  *
- * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
- *              is expressed in ppb (parts per billion). The parent accuracy is
- *              an input parameter.
- *              Returns the calculated accuracy.  Optional - if this op is not
- *              set then clock accuracy will be initialized to parent accuracy
- *              or 0 (perfect clock) if clock has no parent.
- *
  * @set_rate_and_parent: Change the rate and the parent of this clock. The
  *              requested rate is specified by the second argument, which
  *              should typically be the return of .round_rate call.  The
@@ -128,6 +122,18 @@ struct dentry;
  *              separately via calls to .set_parent and .set_rate.
  *              Returns 0 on success, -EERROR otherwise.
  *
+ * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
+ *              is expressed in ppb (parts per billion). The parent accuracy is
+ *              an input parameter.
+ *              Returns the calculated accuracy.  Optional - if this op is not
+ *              set then clock accuracy will be initialized to parent accuracy
+ *              or 0 (perfect clock) if clock has no parent.
+ *
+ * @init:       Perform platform-specific initialization magic.
+ *              This is not not used by any of the basic clock types.
+ *              Please consider other ways of solving initialization problems
+ *              before using this callback, as its use is discouraged.
+ *
  * @debug_init: Set up type-specific debugfs entries for this clock.  This
  *              is called once, after the debugfs directory entry for this
  *              clock has been created.  The dentry pointer representing that
@@ -157,15 +163,15 @@ struct clk_ops {
         void            (*disable_unused)(struct clk_hw *hw);
         unsigned long   (*recalc_rate)(struct clk_hw *hw,
                                         unsigned long parent_rate);
-        long            (*round_rate)(struct clk_hw *hw, unsigned long,
-                                        unsigned long *);
+        long            (*round_rate)(struct clk_hw *hw, unsigned long rate,
+                                        unsigned long *parent_rate);
         long            (*determine_rate)(struct clk_hw *hw, unsigned long rate,
                                         unsigned long *best_parent_rate,
                                         struct clk **best_parent_clk);
         int             (*set_parent)(struct clk_hw *hw, u8 index);
         u8              (*get_parent)(struct clk_hw *hw);
-        int             (*set_rate)(struct clk_hw *hw, unsigned long,
-                                    unsigned long);
+        int             (*set_rate)(struct clk_hw *hw, unsigned long rate,
+                                    unsigned long parent_rate);
         int             (*set_rate_and_parent)(struct clk_hw *hw,
                                     unsigned long rate,
                                     unsigned long parent_rate, u8 index);
@@ -254,12 +260,12 @@ void of_fixed_clk_setup(struct device_node *np);
  *
  * Flags:
  * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
- *      enable the clock.  Setting this flag does the opposite: setting the bit
- *      disable the clock and clearing it enables the clock
+ *      enable the clock.  Setting this flag does the opposite: setting the bit
+ *      disable the clock and clearing it enables the clock
  * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
- *   of this register, and mask of gate bits are in higher 16-bit of this
- *   register.  While setting the gate bits, higher 16-bit should also be
- *   updated to indicate changing gate bits.
+ *      of this register, and mask of gate bits are in higher 16-bit of this
+ *      register.  While setting the gate bits, higher 16-bit should also be
+ *      updated to indicate changing gate bits.
  */
 struct clk_gate {
         struct clk_hw hw;
@@ -298,20 +304,24 @@ struct clk_div_table {
  *
  * Flags:
  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
- *      register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is
- *      the raw value read from the register, with the value of zero considered
+ *      register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is
+ *      the raw value read from the register, with the value of zero considered
  *      invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
- *      the hardware register
+ *      the hardware register
  * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
  *      CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
  *      Some hardware implementations gracefully handle this case and allow a
  *      zero divisor by not modifying their input clock
  *      (divide by one / bypass).
  * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
- *   of this register, and mask of divider bits are in higher 16-bit of this
- *   register.  While setting the divider bits, higher 16-bit should also be
- *   updated to indicate changing divider bits.
+ *      of this register, and mask of divider bits are in higher 16-bit of this
+ *      register.  While setting the divider bits, higher 16-bit should also be
+ *      updated to indicate changing divider bits.
+ * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
+ *      to the closest integer instead of the up one.
+ * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
+ *      not be changed by the clock framework.
  */
 struct clk_divider {
         struct clk_hw   hw;
@@ -327,8 +337,11 @@ struct clk_divider {
 #define CLK_DIVIDER_POWER_OF_TWO        BIT(1)
 #define CLK_DIVIDER_ALLOW_ZERO          BIT(2)
 #define CLK_DIVIDER_HIWORD_MASK         BIT(3)
+#define CLK_DIVIDER_ROUND_CLOSEST       BIT(4)
+#define CLK_DIVIDER_READ_ONLY           BIT(5)
 
 extern const struct clk_ops clk_divider_ops;
+extern const struct clk_ops clk_divider_ro_ops;
 struct clk *clk_register_divider(struct device *dev, const char *name,
                 const char *parent_name, unsigned long flags,
                 void __iomem *reg, u8 shift, u8 width,
@@ -356,9 +369,9 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
  * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
  * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
- *   register, and mask of mux bits are in higher 16-bit of this register.
- *   While setting the mux bits, higher 16-bit should also be updated to
- *   indicate changing mux bits.
+ *      register, and mask of mux bits are in higher 16-bit of this register.
+ *      While setting the mux bits, higher 16-bit should also be updated to
+ *      indicate changing mux bits.
  */
 struct clk_mux {
         struct clk_hw   hw;
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
index f9bf080a1123..9f8a14041dd5 100644
--- a/include/linux/clk/shmobile.h
+++ b/include/linux/clk/shmobile.h
@@ -1,7 +1,9 @@
 /*
  * Copyright 2013 Ideas On Board SPRL
+ * Copyright 2013, 2014 Horms Solutions Ltd.
  *
  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ * Contact: Simon Horman <horms@verge.net.au>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,6 +16,7 @@
 
 #include <linux/types.h>
 
+void r8a7779_clocks_init(u32 mode);
 void rcar_gen2_clocks_init(u32 mode);
 
 #endif
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
new file mode 100644
index 000000000000..aed28c4451d9
--- /dev/null
+++ b/include/linux/clk/sunxi.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_CLK_SUNXI_H_
+#define __LINUX_CLK_SUNXI_H_
+
+#include <linux/clk.h>
+
+void clk_sunxi_mmc_phase_control(struct clk *clk, u8 sample, u8 output);
+
+#endif