diff options
Diffstat (limited to 'include/video')
| -rw-r--r-- | include/video/epson1355.h | 64 |
1 files changed, 0 insertions, 64 deletions
diff --git a/include/video/epson1355.h b/include/video/epson1355.h deleted file mode 100644 index 9759f299499e..000000000000 --- a/include/video/epson1355.h +++ /dev/null | |||
| @@ -1,64 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/video/epson13xx.h -- Epson 13xx frame buffer | ||
| 3 | * | ||
| 4 | * Copyright (C) Hewlett-Packard Company. All rights reserved. | ||
| 5 | * | ||
| 6 | * Written by Christopher Hoover <ch@hpl.hp.com> | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef _EPSON13XX_H_ | ||
| 11 | #define _EPSON13XX_H_ | ||
| 12 | |||
| 13 | #define REG_REVISION_CODE 0x00 | ||
| 14 | #define REG_MEMORY_CONFIG 0x01 | ||
| 15 | #define REG_PANEL_TYPE 0x02 | ||
| 16 | #define REG_MOD_RATE 0x03 | ||
| 17 | #define REG_HORZ_DISP_WIDTH 0x04 | ||
| 18 | #define REG_HORZ_NONDISP_PERIOD 0x05 | ||
| 19 | #define REG_HRTC_START_POSITION 0x06 | ||
| 20 | #define REG_HRTC_PULSE_WIDTH 0x07 | ||
| 21 | #define REG_VERT_DISP_HEIGHT0 0x08 | ||
| 22 | #define REG_VERT_DISP_HEIGHT1 0x09 | ||
| 23 | #define REG_VERT_NONDISP_PERIOD 0x0A | ||
| 24 | #define REG_VRTC_START_POSITION 0x0B | ||
| 25 | #define REG_VRTC_PULSE_WIDTH 0x0C | ||
| 26 | #define REG_DISPLAY_MODE 0x0D | ||
| 27 | #define REG_SCRN1_LINE_COMPARE0 0x0E | ||
| 28 | #define REG_SCRN1_LINE_COMPARE1 0x0F | ||
| 29 | #define REG_SCRN1_DISP_START_ADDR0 0x10 | ||
| 30 | #define REG_SCRN1_DISP_START_ADDR1 0x11 | ||
| 31 | #define REG_SCRN1_DISP_START_ADDR2 0x12 | ||
| 32 | #define REG_SCRN2_DISP_START_ADDR0 0x13 | ||
| 33 | #define REG_SCRN2_DISP_START_ADDR1 0x14 | ||
| 34 | #define REG_SCRN2_DISP_START_ADDR2 0x15 | ||
| 35 | #define REG_MEM_ADDR_OFFSET0 0x16 | ||
| 36 | #define REG_MEM_ADDR_OFFSET1 0x17 | ||
| 37 | #define REG_PIXEL_PANNING 0x18 | ||
| 38 | #define REG_CLOCK_CONFIG 0x19 | ||
| 39 | #define REG_POWER_SAVE_CONFIG 0x1A | ||
| 40 | #define REG_MISC 0x1B | ||
| 41 | #define REG_MD_CONFIG_READBACK0 0x1C | ||
| 42 | #define REG_MD_CONFIG_READBACK1 0x1D | ||
| 43 | #define REG_GPIO_CONFIG0 0x1E | ||
| 44 | #define REG_GPIO_CONFIG1 0x1F | ||
| 45 | #define REG_GPIO_CONTROL0 0x20 | ||
| 46 | #define REG_GPIO_CONTROL1 0x21 | ||
| 47 | #define REG_PERF_ENHANCEMENT0 0x22 | ||
| 48 | #define REG_PERF_ENHANCEMENT1 0x23 | ||
| 49 | #define REG_LUT_ADDR 0x24 | ||
| 50 | #define REG_RESERVED_1 0x25 | ||
| 51 | #define REG_LUT_DATA 0x26 | ||
| 52 | #define REG_INK_CURSOR_CONTROL 0x27 | ||
| 53 | #define REG_CURSOR_X_POSITION0 0x28 | ||
| 54 | #define REG_CURSOR_X_POSITION1 0x29 | ||
| 55 | #define REG_CURSOR_Y_POSITION0 0x2A | ||
| 56 | #define REG_CURSOR_Y_POSITION1 0x2B | ||
| 57 | #define REG_INK_CURSOR_COLOR0_0 0x2C | ||
| 58 | #define REG_INK_CURSOR_COLOR0_1 0x2D | ||
| 59 | #define REG_INK_CURSOR_COLOR1_0 0x2E | ||
| 60 | #define REG_INK_CURSOR_COLOR1_1 0x2F | ||
| 61 | #define REG_INK_CURSOR_START_ADDR 0x30 | ||
| 62 | #define REG_ALTERNATE_FRM 0x31 | ||
| 63 | |||
| 64 | #endif | ||