diff options
Diffstat (limited to 'include/uapi/linux')
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 4a98e85438a7..5eefacd93e18 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h | |||
| @@ -678,16 +678,33 @@ | |||
| 678 | 678 | ||
| 679 | /* Virtual Channel */ | 679 | /* Virtual Channel */ |
| 680 | #define PCI_VC_PORT_REG1 4 | 680 | #define PCI_VC_PORT_REG1 4 |
| 681 | #define PCI_VC_REG1_EVCC 0x7 /* extended VC count */ | 681 | #define PCI_VC_REG1_EVCC 0x00000007 /* extended VC count */ |
| 682 | #define PCI_VC_REG1_LPEVCC 0x00000070 /* low prio extended VC count */ | ||
| 683 | #define PCI_VC_REG1_ARB_SIZE 0x00000c00 | ||
| 682 | #define PCI_VC_PORT_REG2 8 | 684 | #define PCI_VC_PORT_REG2 8 |
| 683 | #define PCI_VC_REG2_32_PHASE 0x2 | 685 | #define PCI_VC_REG2_32_PHASE 0x00000002 |
| 684 | #define PCI_VC_REG2_64_PHASE 0x4 | 686 | #define PCI_VC_REG2_64_PHASE 0x00000004 |
| 685 | #define PCI_VC_REG2_128_PHASE 0x8 | 687 | #define PCI_VC_REG2_128_PHASE 0x00000008 |
| 688 | #define PCI_VC_REG2_ARB_OFF 0xff000000 | ||
| 686 | #define PCI_VC_PORT_CTRL 12 | 689 | #define PCI_VC_PORT_CTRL 12 |
| 690 | #define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 | ||
| 687 | #define PCI_VC_PORT_STATUS 14 | 691 | #define PCI_VC_PORT_STATUS 14 |
| 692 | #define PCI_VC_PORT_STATUS_TABLE 0x00000001 | ||
| 688 | #define PCI_VC_RES_CAP 16 | 693 | #define PCI_VC_RES_CAP 16 |
| 694 | #define PCI_VC_RES_CAP_32_PHASE 0x00000002 | ||
| 695 | #define PCI_VC_RES_CAP_64_PHASE 0x00000004 | ||
| 696 | #define PCI_VC_RES_CAP_128_PHASE 0x00000008 | ||
| 697 | #define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 | ||
| 698 | #define PCI_VC_RES_CAP_256_PHASE 0x00000020 | ||
| 699 | #define PCI_VC_RES_CAP_ARB_OFF 0xff000000 | ||
| 689 | #define PCI_VC_RES_CTRL 20 | 700 | #define PCI_VC_RES_CTRL 20 |
| 701 | #define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 | ||
| 702 | #define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 | ||
| 703 | #define PCI_VC_RES_CTRL_ID 0x07000000 | ||
| 704 | #define PCI_VC_RES_CTRL_ENABLE 0x80000000 | ||
| 690 | #define PCI_VC_RES_STATUS 26 | 705 | #define PCI_VC_RES_STATUS 26 |
| 706 | #define PCI_VC_RES_STATUS_TABLE 0x00000001 | ||
| 707 | #define PCI_VC_RES_STATUS_NEGO 0x00000002 | ||
| 691 | #define PCI_CAP_VC_BASE_SIZEOF 0x10 | 708 | #define PCI_CAP_VC_BASE_SIZEOF 0x10 |
| 692 | #define PCI_CAP_VC_PER_VC_SIZEOF 0x0C | 709 | #define PCI_CAP_VC_PER_VC_SIZEOF 0x0C |
| 693 | 710 | ||
