1 files changed, 70 insertions, 1 deletions

diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 9fa9c622a7f4..fb104e51496e 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -132,8 +132,10 @@ enum perf_event_sample_format {
         PERF_SAMPLE_BRANCH_STACK                = 1U << 11,
         PERF_SAMPLE_REGS_USER                   = 1U << 12,
         PERF_SAMPLE_STACK_USER                  = 1U << 13,
+        PERF_SAMPLE_WEIGHT                      = 1U << 14,
+        PERF_SAMPLE_DATA_SRC                    = 1U << 15,
 
-        PERF_SAMPLE_MAX = 1U << 14,             /* non-ABI */
+        PERF_SAMPLE_MAX = 1U << 16,             /* non-ABI */
 };
 
 /*
@@ -443,6 +445,7 @@ struct perf_event_mmap_page {
 #define PERF_RECORD_MISC_GUEST_KERNEL           (4 << 0)
 #define PERF_RECORD_MISC_GUEST_USER             (5 << 0)
 
+#define PERF_RECORD_MISC_MMAP_DATA              (1 << 13)
 /*
  * Indicates that the content of PERF_SAMPLE_IP points to
  * the actual instruction that triggered the event. See also
@@ -588,6 +591,9 @@ enum perf_event_type {
          *      { u64                   size;
          *        char                  data[size];
          *        u64                   dyn_size; } && PERF_SAMPLE_STACK_USER
+         *
+         *      { u64                   weight;   } && PERF_SAMPLE_WEIGHT
+         *      { u64                   data_src;     } && PERF_SAMPLE_DATA_SRC
          * };
          */
         PERF_RECORD_SAMPLE                      = 9,
@@ -613,4 +619,67 @@ enum perf_callchain_context {
 #define PERF_FLAG_FD_OUTPUT             (1U << 1)
 #define PERF_FLAG_PID_CGROUP            (1U << 2) /* pid=cgroup id, per-cpu mode only */
 
+union perf_mem_data_src {
+        __u64 val;
+        struct {
+                __u64   mem_op:5,       /* type of opcode */
+                        mem_lvl:14,     /* memory hierarchy level */
+                        mem_snoop:5,    /* snoop mode */
+                        mem_lock:2,     /* lock instr */
+                        mem_dtlb:7,     /* tlb access */
+                        mem_rsvd:31;
+        };
+};
+
+/* type of opcode (load/store/prefetch,code) */
+#define PERF_MEM_OP_NA          0x01 /* not available */
+#define PERF_MEM_OP_LOAD        0x02 /* load instruction */
+#define PERF_MEM_OP_STORE       0x04 /* store instruction */
+#define PERF_MEM_OP_PFETCH      0x08 /* prefetch */
+#define PERF_MEM_OP_EXEC        0x10 /* code (execution) */
+#define PERF_MEM_OP_SHIFT       0
+
+/* memory hierarchy (memory level, hit or miss) */
+#define PERF_MEM_LVL_NA         0x01  /* not available */
+#define PERF_MEM_LVL_HIT        0x02  /* hit level */
+#define PERF_MEM_LVL_MISS       0x04  /* miss level  */
+#define PERF_MEM_LVL_L1         0x08  /* L1 */
+#define PERF_MEM_LVL_LFB        0x10  /* Line Fill Buffer */
+#define PERF_MEM_LVL_L2         0x20  /* L2 */
+#define PERF_MEM_LVL_L3         0x40  /* L3 */
+#define PERF_MEM_LVL_LOC_RAM    0x80  /* Local DRAM */
+#define PERF_MEM_LVL_REM_RAM1   0x100 /* Remote DRAM (1 hop) */
+#define PERF_MEM_LVL_REM_RAM2   0x200 /* Remote DRAM (2 hops) */
+#define PERF_MEM_LVL_REM_CCE1   0x400 /* Remote Cache (1 hop) */
+#define PERF_MEM_LVL_REM_CCE2   0x800 /* Remote Cache (2 hops) */
+#define PERF_MEM_LVL_IO         0x1000 /* I/O memory */
+#define PERF_MEM_LVL_UNC        0x2000 /* Uncached memory */
+#define PERF_MEM_LVL_SHIFT      5
+
+/* snoop mode */
+#define PERF_MEM_SNOOP_NA       0x01 /* not available */
+#define PERF_MEM_SNOOP_NONE     0x02 /* no snoop */
+#define PERF_MEM_SNOOP_HIT      0x04 /* snoop hit */
+#define PERF_MEM_SNOOP_MISS     0x08 /* snoop miss */
+#define PERF_MEM_SNOOP_HITM     0x10 /* snoop hit modified */
+#define PERF_MEM_SNOOP_SHIFT    19
+
+/* locked instruction */
+#define PERF_MEM_LOCK_NA        0x01 /* not available */
+#define PERF_MEM_LOCK_LOCKED    0x02 /* locked transaction */
+#define PERF_MEM_LOCK_SHIFT     24
+
+/* TLB access */
+#define PERF_MEM_TLB_NA         0x01 /* not available */
+#define PERF_MEM_TLB_HIT        0x02 /* hit level */
+#define PERF_MEM_TLB_MISS       0x04 /* miss level */
+#define PERF_MEM_TLB_L1         0x08 /* L1 */
+#define PERF_MEM_TLB_L2         0x10 /* L2 */
+#define PERF_MEM_TLB_WK         0x20 /* Hardware Walker*/
+#define PERF_MEM_TLB_OS         0x40 /* OS fault handler */
+#define PERF_MEM_TLB_SHIFT      26
+
+#define PERF_MEM_S(a, s) \
+        (((u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
+
 #endif /* _UAPI_LINUX_PERF_EVENT_H */