7 files changed, 165 insertions, 84 deletions

diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 78199151c00b..d047f846c3ed 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -257,6 +257,40 @@ void __init acpi_no_s4_hw_signature(void);
 void __init acpi_old_suspend_ordering(void);
 void __init acpi_s4_no_nvs(void);
 #endif /* CONFIG_PM_SLEEP */
+
+#define OSC_QUERY_TYPE                  0
+#define OSC_SUPPORT_TYPE                1
+#define OSC_CONTROL_TYPE                2
+#define OSC_SUPPORT_MASKS               0x1f
+
+/* _OSC DW0 Definition */
+#define OSC_QUERY_ENABLE                1
+#define OSC_REQUEST_ERROR               2
+#define OSC_INVALID_UUID_ERROR          4
+#define OSC_INVALID_REVISION_ERROR      8
+#define OSC_CAPABILITIES_MASK_ERROR     16
+
+/* _OSC DW1 Definition (OS Support Fields) */
+#define OSC_EXT_PCI_CONFIG_SUPPORT              1
+#define OSC_ACTIVE_STATE_PWR_SUPPORT            2
+#define OSC_CLOCK_PWR_CAPABILITY_SUPPORT        4
+#define OSC_PCI_SEGMENT_GROUPS_SUPPORT          8
+#define OSC_MSI_SUPPORT                         16
+
+/* _OSC DW1 Definition (OS Control Fields) */
+#define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL       1
+#define OSC_SHPC_NATIVE_HP_CONTROL              2
+#define OSC_PCI_EXPRESS_PME_CONTROL             4
+#define OSC_PCI_EXPRESS_AER_CONTROL             8
+#define OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL   16
+
+#define OSC_CONTROL_MASKS       (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL |    \
+                                OSC_SHPC_NATIVE_HP_CONTROL |            \
+                                OSC_PCI_EXPRESS_PME_CONTROL |           \
+                                OSC_PCI_EXPRESS_AER_CONTROL |           \
+                                OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL)
+
+extern acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 flags);
 #else   /* CONFIG_ACPI */
 
 static inline int early_acpi_boot_init(void)
diff --git a/include/linux/msi.h b/include/linux/msi.h
index d2b8a1e8ca11..6991ab5b24d1 100644
--- a/include/linux/msi.h
+++ b/include/linux/msi.h
@@ -20,20 +20,23 @@ extern void write_msi_msg(unsigned int irq, struct msi_msg *msg);
 
 struct msi_desc {
         struct {
-                __u8    type    : 5;    /* {0: unused, 5h:MSI, 11h:MSI-X} */
+                __u8    is_msix : 1;
+                __u8    multiple: 3;    /* log2 number of messages */
                 __u8    maskbit : 1;    /* mask-pending bit supported ?   */
-                __u8    masked  : 1;
                 __u8    is_64   : 1;    /* Address size: 0=32bit 1=64bit  */
                 __u8    pos;            /* Location of the msi capability */
-                __u32   maskbits_mask;  /* mask bits mask */
                 __u16   entry_nr;       /* specific enabled entry         */
                 unsigned default_irq;   /* default pre-assigned irq       */
-        }msi_attrib;
+        } msi_attrib;
 
+        u32 masked;                     /* mask bits */
         unsigned int irq;
         struct list_head list;
 
-        void __iomem *mask_base;
+        union {
+                void __iomem *mask_base;
+                u8 mask_pos;
+        };
         struct pci_dev *dev;
 
         /* Last set MSI message */
diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h
index 042c166f65d5..092e82e0048c 100644
--- a/include/linux/pci-acpi.h
+++ b/include/linux/pci-acpi.h
@@ -10,72 +10,25 @@
 
 #include <linux/acpi.h>
 
-#define OSC_QUERY_TYPE                  0
-#define OSC_SUPPORT_TYPE                1
-#define OSC_CONTROL_TYPE                2
-#define OSC_SUPPORT_MASKS               0x1f
-
-/*
- * _OSC DW0 Definition 
- */
-#define OSC_QUERY_ENABLE                1
-#define OSC_REQUEST_ERROR               2
-#define OSC_INVALID_UUID_ERROR          4
-#define OSC_INVALID_REVISION_ERROR      8
-#define OSC_CAPABILITIES_MASK_ERROR     16
-
-/*
- * _OSC DW1 Definition (OS Support Fields)
- */
-#define OSC_EXT_PCI_CONFIG_SUPPORT              1
-#define OSC_ACTIVE_STATE_PWR_SUPPORT            2
-#define OSC_CLOCK_PWR_CAPABILITY_SUPPORT        4
-#define OSC_PCI_SEGMENT_GROUPS_SUPPORT          8
-#define OSC_MSI_SUPPORT                         16
-
-/*
- * _OSC DW1 Definition (OS Control Fields)
- */
-#define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL       1
-#define OSC_SHPC_NATIVE_HP_CONTROL              2
-#define OSC_PCI_EXPRESS_PME_CONTROL             4
-#define OSC_PCI_EXPRESS_AER_CONTROL             8
-#define OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL   16
-
-#define OSC_CONTROL_MASKS       (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL |    \
-                                OSC_SHPC_NATIVE_HP_CONTROL |            \
-                                OSC_PCI_EXPRESS_PME_CONTROL |           \
-                                OSC_PCI_EXPRESS_AER_CONTROL |           \
-                                OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL)
-
 #ifdef CONFIG_ACPI
-extern acpi_status pci_osc_control_set(acpi_handle handle, u32 flags);
-int pci_acpi_osc_support(acpi_handle handle, u32 flags);
 static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
 {
-        /* Find root host bridge */
-        while (pdev->bus->self)
-                pdev = pdev->bus->self;
-
-        return acpi_get_pci_rootbridge_handle(pci_domain_nr(pdev->bus),
-                        pdev->bus->number);
+        struct pci_bus *pbus = pdev->bus;
+        /* Find a PCI root bus */
+        while (pbus->parent)
+                pbus = pbus->parent;
+        return acpi_get_pci_rootbridge_handle(pci_domain_nr(pbus),
+                                              pbus->number);
 }
 
 static inline acpi_handle acpi_pci_get_bridge_handle(struct pci_bus *pbus)
 {
-        int seg = pci_domain_nr(pbus), busnr = pbus->number;
-        struct pci_dev *bridge = pbus->self;
-        if (bridge)
-                return DEVICE_ACPI_HANDLE(&(bridge->dev));
-        return acpi_get_pci_rootbridge_handle(seg, busnr);
+        if (pbus->parent)
+                return DEVICE_ACPI_HANDLE(&(pbus->self->dev));
+        return acpi_get_pci_rootbridge_handle(pci_domain_nr(pbus),
+                                              pbus->number);
 }
 #else
-#if !defined(AE_ERROR)
-typedef u32             acpi_status;
-#define AE_ERROR        (acpi_status) (0x0001)
-#endif    
-static inline acpi_status pci_osc_control_set(acpi_handle handle, u32 flags)
-{return AE_ERROR;}
 static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
 { return NULL; }
 #endif
diff --git a/include/linux/pci.h b/include/linux/pci.h
index df3644132617..a7fe4bbd7ff1 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -52,6 +52,7 @@
 #include <asm/atomic.h>
 #include <linux/device.h>
 #include <linux/io.h>
+#include <linux/irqreturn.h>
 
 /* Include the ID list */
 #include <linux/pci_ids.h>
@@ -93,6 +94,12 @@ enum {
         /* #6: expansion ROM resource */
         PCI_ROM_RESOURCE,
 
+        /* device specific resources */
+#ifdef CONFIG_PCI_IOV
+        PCI_IOV_RESOURCES,
+        PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
+#endif
+
         /* resources assigned to buses behind the bridge */
 #define PCI_BRIDGE_RESOURCE_NUM 4
 
@@ -180,6 +187,7 @@ struct pci_cap_saved_state {
 
 struct pcie_link_state;
 struct pci_vpd;
+struct pci_sriov;
 
 /*
  * The pci_dev structure is used to describe PCI devices.
@@ -257,6 +265,8 @@ struct pci_dev {
         unsigned int    is_managed:1;
         unsigned int    is_pcie:1;
         unsigned int    state_saved:1;
+        unsigned int    is_physfn:1;
+        unsigned int    is_virtfn:1;
         pci_dev_flags_t dev_flags;
         atomic_t        enable_cnt;     /* pci_enable_device has been called */
 
@@ -270,6 +280,12 @@ struct pci_dev {
         struct list_head msi_list;
 #endif
         struct pci_vpd *vpd;
+#ifdef CONFIG_PCI_IOV
+        union {
+                struct pci_sriov *sriov;        /* SR-IOV capability related */
+                struct pci_dev *physfn; /* the PF this VF is associated with */
+        };
+#endif
 };
 
 extern struct pci_dev *alloc_pci_dev(void);
@@ -341,6 +357,15 @@ struct pci_bus {
 #define pci_bus_b(n)    list_entry(n, struct pci_bus, node)
 #define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
 
+/*
+ * Returns true if the pci bus is root (behind host-pci bridge),
+ * false otherwise
+ */
+static inline bool pci_is_root_bus(struct pci_bus *pbus)
+{
+        return !(pbus->parent);
+}
+
 #ifdef CONFIG_PCI_MSI
 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
 {
@@ -528,7 +553,7 @@ void pcibios_update_irq(struct pci_dev *, int irq);
 /* Generic PCI functions used internally */
 
 extern struct pci_bus *pci_find_bus(int domain, int busnr);
-void pci_bus_add_devices(struct pci_bus *bus);
+void pci_bus_add_devices(const struct pci_bus *bus);
 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
                                       struct pci_ops *ops, void *sysdata);
 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
@@ -702,6 +727,9 @@ int pci_back_from_sleep(struct pci_dev *dev);
 
 /* Functions for PCI Hotplug drivers to use */
 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
+#ifdef CONFIG_HOTPLUG
+unsigned int pci_rescan_bus(struct pci_bus *bus);
+#endif
 
 /* Vital product data routines */
 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
@@ -709,7 +737,7 @@ ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void
 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
 
 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
-void pci_bus_assign_resources(struct pci_bus *bus);
+void pci_bus_assign_resources(const struct pci_bus *bus);
 void pci_bus_size_bridges(struct pci_bus *bus);
 int pci_claim_resource(struct pci_dev *, int);
 void pci_assign_unassigned_resources(void);
@@ -790,7 +818,7 @@ struct msix_entry {
 
 
 #ifndef CONFIG_PCI_MSI
-static inline int pci_enable_msi(struct pci_dev *dev)
+static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
 {
         return -1;
 }
@@ -800,6 +828,10 @@ static inline void pci_msi_shutdown(struct pci_dev *dev)
 static inline void pci_disable_msi(struct pci_dev *dev)
 { }
 
+static inline int pci_msix_table_size(struct pci_dev *dev)
+{
+        return 0;
+}
 static inline int pci_enable_msix(struct pci_dev *dev,
                                   struct msix_entry *entries, int nvec)
 {
@@ -821,9 +853,10 @@ static inline int pci_msi_enabled(void)
         return 0;
 }
 #else
-extern int pci_enable_msi(struct pci_dev *dev);
+extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
 extern void pci_msi_shutdown(struct pci_dev *dev);
 extern void pci_disable_msi(struct pci_dev *dev);
+extern int pci_msix_table_size(struct pci_dev *dev);
 extern int pci_enable_msix(struct pci_dev *dev,
         struct msix_entry *entries, int nvec);
 extern void pci_msix_shutdown(struct pci_dev *dev);
@@ -842,6 +875,8 @@ static inline int pcie_aspm_enabled(void)
 extern int pcie_aspm_enabled(void);
 #endif
 
+#define pci_enable_msi(pdev)    pci_enable_msi_block(pdev, 1)
+
 #ifdef CONFIG_HT_IRQ
 /* The functions a driver should call */
 int  ht_create_irq(struct pci_dev *dev, int idx);
@@ -1195,5 +1230,23 @@ int pci_ext_cfg_avail(struct pci_dev *dev);
 
 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
 
+#ifdef CONFIG_PCI_IOV
+extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
+extern void pci_disable_sriov(struct pci_dev *dev);
+extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
+#else
+static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
+{
+        return -ENODEV;
+}
+static inline void pci_disable_sriov(struct pci_dev *dev)
+{
+}
+static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
+{
+        return IRQ_NONE;
+}
+#endif
+
 #endif /* __KERNEL__ */
 #endif /* LINUX_PCI_H */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index e5816dd33371..cb14fd260837 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2396,6 +2396,7 @@
 #define PCI_DEVICE_ID_INTEL_82801CA_12  0x248c
 #define PCI_DEVICE_ID_INTEL_82801DB_0   0x24c0
 #define PCI_DEVICE_ID_INTEL_82801DB_1   0x24c1
+#define PCI_DEVICE_ID_INTEL_82801DB_2   0x24c2
 #define PCI_DEVICE_ID_INTEL_82801DB_3   0x24c3
 #define PCI_DEVICE_ID_INTEL_82801DB_5   0x24c5
 #define PCI_DEVICE_ID_INTEL_82801DB_6   0x24c6
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 027815b4635e..e4d08c1b2e0b 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -235,7 +235,7 @@
 #define  PCI_PM_CAP_PME_SHIFT   11      /* Start of the PME Mask in PMC */
 #define PCI_PM_CTRL             4       /* PM control and status register */
 #define  PCI_PM_CTRL_STATE_MASK 0x0003  /* Current power state (D0 to D3) */
-#define  PCI_PM_CTRL_NO_SOFT_RESET      0x0004  /* No reset for D3hot->D0 */
+#define  PCI_PM_CTRL_NO_SOFT_RESET      0x0008  /* No reset for D3hot->D0 */
 #define  PCI_PM_CTRL_PME_ENABLE 0x0100  /* PME pin enable */
 #define  PCI_PM_CTRL_DATA_SEL_MASK      0x1e00  /* Data select (??) */
 #define  PCI_PM_CTRL_DATA_SCALE_MASK    0x6000  /* Data scale (??) */
@@ -375,6 +375,7 @@
 #define  PCI_EXP_TYPE_UPSTREAM  0x5     /* Upstream Port */
 #define  PCI_EXP_TYPE_DOWNSTREAM 0x6    /* Downstream Port */
 #define  PCI_EXP_TYPE_PCI_BRIDGE 0x7    /* PCI/PCI-X Bridge */
+#define  PCI_EXP_TYPE_RC_END    0x9     /* Root Complex Integrated Endpoint */
 #define PCI_EXP_FLAGS_SLOT      0x0100  /* Slot implemented */
 #define PCI_EXP_FLAGS_IRQ       0x3e00  /* Interrupt message number */
 #define PCI_EXP_DEVCAP          4       /* Device capabilities */
@@ -487,6 +488,8 @@
 #define  PCI_EXP_DEVCAP2_ARI    0x20    /* Alternative Routing-ID */
 #define PCI_EXP_DEVCTL2         40      /* Device Control 2 */
 #define  PCI_EXP_DEVCTL2_ARI    0x20    /* Alternative Routing-ID */
+#define PCI_EXP_LNKCTL2         48      /* Link Control 2 */
+#define PCI_EXP_SLTCTL2         56      /* Slot Control 2 */
 
 /* Extended Capabilities (PCI-X 2.0 and Express) */
 #define PCI_EXT_CAP_ID(header)          (header & 0x0000ffff)
@@ -498,6 +501,7 @@
 #define PCI_EXT_CAP_ID_DSN      3
 #define PCI_EXT_CAP_ID_PWR      4
 #define PCI_EXT_CAP_ID_ARI      14
+#define PCI_EXT_CAP_ID_SRIOV    16
 
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS    4       /* Uncorrectable Error Status */
@@ -615,4 +619,35 @@
 #define  PCI_ARI_CTRL_ACS       0x0002  /* ACS Function Groups Enable */
 #define  PCI_ARI_CTRL_FG(x)     (((x) >> 4) & 7) /* Function Group */
 
+/* Single Root I/O Virtualization */
+#define PCI_SRIOV_CAP           0x04    /* SR-IOV Capabilities */
+#define  PCI_SRIOV_CAP_VFM      0x01    /* VF Migration Capable */
+#define  PCI_SRIOV_CAP_INTR(x)  ((x) >> 21) /* Interrupt Message Number */
+#define PCI_SRIOV_CTRL          0x08    /* SR-IOV Control */
+#define  PCI_SRIOV_CTRL_VFE     0x01    /* VF Enable */
+#define  PCI_SRIOV_CTRL_VFM     0x02    /* VF Migration Enable */
+#define  PCI_SRIOV_CTRL_INTR    0x04    /* VF Migration Interrupt Enable */
+#define  PCI_SRIOV_CTRL_MSE     0x08    /* VF Memory Space Enable */
+#define  PCI_SRIOV_CTRL_ARI     0x10    /* ARI Capable Hierarchy */
+#define PCI_SRIOV_STATUS        0x0a    /* SR-IOV Status */
+#define  PCI_SRIOV_STATUS_VFM   0x01    /* VF Migration Status */
+#define PCI_SRIOV_INITIAL_VF    0x0c    /* Initial VFs */
+#define PCI_SRIOV_TOTAL_VF      0x0e    /* Total VFs */
+#define PCI_SRIOV_NUM_VF        0x10    /* Number of VFs */
+#define PCI_SRIOV_FUNC_LINK     0x12    /* Function Dependency Link */
+#define PCI_SRIOV_VF_OFFSET     0x14    /* First VF Offset */
+#define PCI_SRIOV_VF_STRIDE     0x16    /* Following VF Stride */
+#define PCI_SRIOV_VF_DID        0x1a    /* VF Device ID */
+#define PCI_SRIOV_SUP_PGSIZE    0x1c    /* Supported Page Sizes */
+#define PCI_SRIOV_SYS_PGSIZE    0x20    /* System Page Size */
+#define PCI_SRIOV_BAR           0x24    /* VF BAR0 */
+#define  PCI_SRIOV_NUM_BARS     6       /* Number of VF BARs */
+#define PCI_SRIOV_VFM           0x3c    /* VF Migration State Array Offset*/
+#define  PCI_SRIOV_VFM_BIR(x)   ((x) & 7)       /* State BIR */
+#define  PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7)     /* State Offset */
+#define  PCI_SRIOV_VFM_UA       0x0     /* Inactive.Unavailable */
+#define  PCI_SRIOV_VFM_MI       0x1     /* Dormant.MigrateIn */
+#define  PCI_SRIOV_VFM_MO       0x2     /* Active.MigrateOut */
+#define  PCI_SRIOV_VFM_AV       0x3     /* Active.Available */
+
 #endif /* LINUX_PCI_REGS_H */
diff --git a/include/linux/pcieport_if.h b/include/linux/pcieport_if.h
index 6cd91e3f9820..b4c79545330b 100644
--- a/include/linux/pcieport_if.h
+++ b/include/linux/pcieport_if.h
@@ -16,29 +16,30 @@
 #define PCIE_ANY_PORT                   7
 
 /* Service Type */
-#define PCIE_PORT_SERVICE_PME           1       /* Power Management Event */
-#define PCIE_PORT_SERVICE_AER           2       /* Advanced Error Reporting */
-#define PCIE_PORT_SERVICE_HP            4       /* Native Hotplug */
-#define PCIE_PORT_SERVICE_VC            8       /* Virtual Channel */
+#define PCIE_PORT_SERVICE_PME_SHIFT     0       /* Power Management Event */
+#define PCIE_PORT_SERVICE_PME           (1 << PCIE_PORT_SERVICE_PME_SHIFT)
+#define PCIE_PORT_SERVICE_AER_SHIFT     1       /* Advanced Error Reporting */
+#define PCIE_PORT_SERVICE_AER           (1 << PCIE_PORT_SERVICE_AER_SHIFT)
+#define PCIE_PORT_SERVICE_HP_SHIFT      2       /* Native Hotplug */
+#define PCIE_PORT_SERVICE_HP            (1 << PCIE_PORT_SERVICE_HP_SHIFT)
+#define PCIE_PORT_SERVICE_VC_SHIFT      3       /* Virtual Channel */
+#define PCIE_PORT_SERVICE_VC            (1 << PCIE_PORT_SERVICE_VC_SHIFT)
 
 /* Root/Upstream/Downstream Port's Interrupt Mode */
+#define PCIE_PORT_NO_IRQ                (-1)
 #define PCIE_PORT_INTx_MODE             0
 #define PCIE_PORT_MSI_MODE              1
 #define PCIE_PORT_MSIX_MODE             2
 
-struct pcie_port_service_id {
-        __u32 vendor, device;           /* Vendor and device ID or PCI_ANY_ID*/
-        __u32 subvendor, subdevice;     /* Subsystem ID's or PCI_ANY_ID */
-        __u32 class, class_mask;        /* (class,subclass,prog-if) triplet */
-        __u32 port_type, service_type;  /* Port Entity */
-        kernel_ulong_t driver_data;
+struct pcie_port_data {
+        int port_type;          /* Type of the port */
+        int port_irq_mode;      /* [0:INTx | 1:MSI | 2:MSI-X] */
 };
 
 struct pcie_device {
         int             irq;        /* Service IRQ/MSI/MSI-X Vector */
-        int             interrupt_mode; /* [0:INTx | 1:MSI | 2:MSI-X] */        
-        struct pcie_port_service_id id; /* Service ID */
-        struct pci_dev  *port;      /* Root/Upstream/Downstream Port */
+        struct pci_dev *port;       /* Root/Upstream/Downstream Port */
+        u32             service;    /* Port service this device represents */
         void            *priv_data; /* Service Private Data */
         struct device   device;     /* Generic Device Interface */
 };
@@ -56,10 +57,9 @@ static inline void* get_service_data(struct pcie_device *dev)
 
 struct pcie_port_service_driver {
         const char *name;
-        int (*probe) (struct pcie_device *dev, 
-                const struct pcie_port_service_id *id);
+        int (*probe) (struct pcie_device *dev);
         void (*remove) (struct pcie_device *dev);
-        int (*suspend) (struct pcie_device *dev, pm_message_t state);
+        int (*suspend) (struct pcie_device *dev);
         int (*resume) (struct pcie_device *dev);
 
         /* Service Error Recovery Handler */
@@ -68,7 +68,9 @@ struct pcie_port_service_driver {
         /* Link Reset Capability - AER service driver specific */
         pci_ers_result_t (*reset_link) (struct pci_dev *dev);
 
-        const struct pcie_port_service_id *id_table;
+        int port_type;  /* Type of the port this driver can handle */
+        u32 service;    /* Port service this device represents */
+
         struct device_driver driver;
 };
 #define to_service_driver(d) \