11 files changed, 93 insertions, 12 deletions

diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index 74af192ef7ae..4cd59b95858f 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -270,6 +270,7 @@ header-y += netfilter_ipv4.h
 header-y += netfilter_ipv6.h
 header-y += netlink.h
 header-y += netrom.h
+header-y += nfc.h
 header-y += nfs.h
 header-y += nfs2.h
 header-y += nfs3.h
diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h
index 98bb2901d7b7..8deaf6d050c3 100644
--- a/include/linux/bcma/bcma.h
+++ b/include/linux/bcma/bcma.h
@@ -26,6 +26,11 @@ struct bcma_chipinfo {
         u8 pkg;
 };
 
+struct bcma_boardinfo {
+        u16 vendor;
+        u16 type;
+};
+
 enum bcma_clkmode {
         BCMA_CLKMODE_FAST,
         BCMA_CLKMODE_DYNAMIC,
@@ -199,6 +204,8 @@ struct bcma_bus {
 
         struct bcma_chipinfo chipinfo;
 
+        struct bcma_boardinfo boardinfo;
+
         struct bcma_device *mapped_core;
         struct list_head cores;
         u8 nr_cores;
diff --git a/include/linux/bcma/bcma_driver_pci.h b/include/linux/bcma/bcma_driver_pci.h
index 46c71e27d31f..41da581e1612 100644
--- a/include/linux/bcma/bcma_driver_pci.h
+++ b/include/linux/bcma/bcma_driver_pci.h
@@ -87,6 +87,13 @@ struct pci_dev;
 #define BCMA_CORE_PCI_PCICFG2                   0x0600  /* PCI config space 2 (rev >= 8) */
 #define BCMA_CORE_PCI_PCICFG3                   0x0700  /* PCI config space 3 (rev >= 8) */
 #define BCMA_CORE_PCI_SPROM(wordoffset)         (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
+#define  BCMA_CORE_PCI_SPROM_PI_OFFSET          0       /* first word */
+#define   BCMA_CORE_PCI_SPROM_PI_MASK           0xf000  /* bit 15:12 */
+#define   BCMA_CORE_PCI_SPROM_PI_SHIFT          12      /* bit 15:12 */
+#define  BCMA_CORE_PCI_SPROM_MISC_CONFIG        5       /* word 5 */
+#define   BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST     0x8000  /* bit 15 */
+#define   BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5        20      /* word 20 for srom rev <= 5 */
+#define   BCMA_CORE_PCI_SPROM_CLKREQ_ENB        0x0800  /* bit 11 */
 
 /* SBtoPCIx */
 #define BCMA_CORE_PCI_SBTOPCI_MEM               0x00000000
@@ -133,6 +140,7 @@ struct pci_dev;
 #define BCMA_CORE_PCI_DLLP_LRREG                0x120   /* Link Replay */
 #define BCMA_CORE_PCI_DLLP_LACKTOREG            0x124   /* Link Ack Timeout */
 #define BCMA_CORE_PCI_DLLP_PMTHRESHREG          0x128   /* Power Management Threshold */
+#define  BCMA_CORE_PCI_ASPMTIMER_EXTEND         0x01000000 /* > rev7: enable extend ASPM timer */
 #define BCMA_CORE_PCI_DLLP_RTRYWPREG            0x12C   /* Retry buffer write ptr */
 #define BCMA_CORE_PCI_DLLP_RTRYRPREG            0x130   /* Retry buffer Read ptr */
 #define BCMA_CORE_PCI_DLLP_RTRYPPREG            0x134   /* Retry buffer Purged ptr */
@@ -201,12 +209,15 @@ struct bcma_drv_pci {
 };
 
 /* Register access */
+#define pcicore_read16(pc, offset)              bcma_read16((pc)->core, offset)
 #define pcicore_read32(pc, offset)              bcma_read32((pc)->core, offset)
+#define pcicore_write16(pc, offset, val)        bcma_write16((pc)->core, offset, val)
 #define pcicore_write32(pc, offset, val)        bcma_write32((pc)->core, offset, val)
 
 extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
                                  struct bcma_device *core, bool enable);
+extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
 
 extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
 extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
diff --git a/include/linux/bootmem.h b/include/linux/bootmem.h
index 66d3e954eb6c..1a0cd270bb7a 100644
--- a/include/linux/bootmem.h
+++ b/include/linux/bootmem.h
@@ -154,7 +154,8 @@ extern void *alloc_large_system_hash(const char *tablename,
                                      int flags,
                                      unsigned int *_hash_shift,
                                      unsigned int *_hash_mask,
-                                     unsigned long limit);
+                                     unsigned long low_limit,
+                                     unsigned long high_limit);
 
 #define HASH_EARLY      0x00000001      /* Allocating during early boot? */
 #define HASH_SMALL      0x00000002      /* sub-page allocation allowed, min
diff --git a/include/linux/if_arp.h b/include/linux/if_arp.h
index 26cb3c2c5c71..f0e69c6e8208 100644
--- a/include/linux/if_arp.h
+++ b/include/linux/if_arp.h
@@ -82,7 +82,7 @@
 #define ARPHRD_FCPL     786             /* Fibrechannel public loop     */
 #define ARPHRD_FCFABRIC 787             /* Fibrechannel fabric          */
         /* 787->799 reserved for fibrechannel media types */
-/* 800 used to be used for token ring */
+#define ARPHRD_IEEE802_TR 800           /* Magic type ident for TR      */
 #define ARPHRD_IEEE80211 801            /* IEEE 802.11                  */
 #define ARPHRD_IEEE80211_PRISM 802      /* IEEE 802.11 + Prism2 header  */
 #define ARPHRD_IEEE80211_RADIOTAP 803   /* IEEE 802.11 + radiotap header */
diff --git a/include/linux/ipx.h b/include/linux/ipx.h
index 8f0243982eb6..3d48014cdd71 100644
--- a/include/linux/ipx.h
+++ b/include/linux/ipx.h
@@ -38,7 +38,7 @@ struct ipx_interface_definition {
 #define IPX_FRAME_8022          2
 #define IPX_FRAME_ETHERII       3
 #define IPX_FRAME_8023          4
-/* obsolete token ring was      5 */
+#define IPX_FRAME_TR_8022       5 /* obsolete */
         unsigned char ipx_special;
 #define IPX_SPECIAL_NONE        0
 #define IPX_PRIMARY             1
diff --git a/include/linux/micrel_phy.h b/include/linux/micrel_phy.h
index dd8da342a991..61f0905bdc48 100644
--- a/include/linux/micrel_phy.h
+++ b/include/linux/micrel_phy.h
@@ -3,7 +3,7 @@
 
 #define MICREL_PHY_ID_MASK      0x00fffff0
 
-#define PHY_ID_KSZ9021          0x00221611
+#define PHY_ID_KSZ9021          0x00221610
 #define PHY_ID_KS8737           0x00221720
 #define PHY_ID_KS8041           0x00221510
 #define PHY_ID_KS8051           0x00221550
diff --git a/include/linux/nfc/pn544.h b/include/linux/nfc/pn544.h
index 7ab8521f2347..9890bbaf4328 100644
--- a/include/linux/nfc/pn544.h
+++ b/include/linux/nfc/pn544.h
@@ -84,6 +84,12 @@ struct pn544_fw_packet {
 };
 
 #ifdef __KERNEL__
+enum {
+        NFC_GPIO_ENABLE,
+        NFC_GPIO_FW_RESET,
+        NFC_GPIO_IRQ
+};
+
 /* board config */
 struct pn544_nfc_platform_data {
         int (*request_resources) (struct i2c_client *client);
@@ -91,6 +97,7 @@ struct pn544_nfc_platform_data {
         void (*enable) (int fw);
         int (*test) (void);
         void (*disable) (void);
+        int (*get_gpio)(int type);
 };
 #endif /* __KERNEL__ */
 
diff --git a/include/linux/nl80211.h b/include/linux/nl80211.h
index 2540e86d99ab..a6959f72745e 100644
--- a/include/linux/nl80211.h
+++ b/include/linux/nl80211.h
@@ -1594,6 +1594,8 @@ enum nl80211_sta_flags {
         NL80211_STA_FLAG_MAX = __NL80211_STA_FLAG_AFTER_LAST - 1
 };
 
+#define NL80211_STA_FLAG_MAX_OLD_API    NL80211_STA_FLAG_TDLS_PEER
+
 /**
  * struct nl80211_sta_flag_update - station flags mask/set
  * @mask: mask of station flags to set
@@ -1994,9 +1996,9 @@ enum nl80211_reg_rule_flags {
  * enum nl80211_dfs_regions - regulatory DFS regions
  *
  * @NL80211_DFS_UNSET: Country has no DFS master region specified
- * @NL80211_DFS_FCC_: Country follows DFS master rules from FCC
- * @NL80211_DFS_FCC_: Country follows DFS master rules from ETSI
- * @NL80211_DFS_JP_: Country follows DFS master rules from JP/MKK/Telec
+ * @NL80211_DFS_FCC: Country follows DFS master rules from FCC
+ * @NL80211_DFS_ETSI: Country follows DFS master rules from ETSI
+ * @NL80211_DFS_JP: Country follows DFS master rules from JP/MKK/Telec
  */
 enum nl80211_dfs_regions {
         NL80211_DFS_UNSET       = 0,
diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h
index d27683180025..bc14bd738ade 100644
--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
@@ -188,7 +188,6 @@ struct ssb_sprom {
 struct ssb_boardinfo {
         u16 vendor;
         u16 type;
-        u8  rev;
 };
 
 
diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h
index 40b1ef8595ee..a0525019e1d1 100644
--- a/include/linux/ssb/ssb_regs.h
+++ b/include/linux/ssb/ssb_regs.h
@@ -228,6 +228,7 @@
 #define  SSB_SPROM1_AGAIN_BG_SHIFT      0
 #define  SSB_SPROM1_AGAIN_A             0xFF00  /* A-PHY */
 #define  SSB_SPROM1_AGAIN_A_SHIFT       8
+#define SSB_SPROM1_CCODE                0x0076
 
 /* SPROM Revision 2 (inherits from rev 1) */
 #define SSB_SPROM2_BFLHI                0x0038  /* Boardflags (high 16 bits) */
@@ -267,6 +268,7 @@
 #define  SSB_SPROM3_OFDMGPO             0x107A  /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
 
 /* SPROM Revision 4 */
+#define SSB_SPROM4_BOARDREV             0x0042  /* Board revision */
 #define SSB_SPROM4_BFLLO                0x0044  /* Boardflags (low 16 bits) */
 #define SSB_SPROM4_BFLHI                0x0046  /* Board Flags Hi */
 #define SSB_SPROM4_BFL2LO               0x0048  /* Board flags 2 (low 16 bits) */
@@ -389,6 +391,11 @@
 #define  SSB_SPROM8_GPIOB_P2            0x00FF  /* Pin 2 */
 #define  SSB_SPROM8_GPIOB_P3            0xFF00  /* Pin 3 */
 #define  SSB_SPROM8_GPIOB_P3_SHIFT      8
+#define SSB_SPROM8_LEDDC                0x009A
+#define  SSB_SPROM8_LEDDC_ON            0xFF00  /* oncount */
+#define  SSB_SPROM8_LEDDC_ON_SHIFT      8
+#define  SSB_SPROM8_LEDDC_OFF           0x00FF  /* offcount */
+#define  SSB_SPROM8_LEDDC_OFF_SHIFT     0
 #define SSB_SPROM8_ANTAVAIL             0x009C  /* Antenna available bitfields*/
 #define  SSB_SPROM8_ANTAVAIL_A          0xFF00  /* A-PHY bitfield */
 #define  SSB_SPROM8_ANTAVAIL_A_SHIFT    8
@@ -404,6 +411,13 @@
 #define  SSB_SPROM8_AGAIN2_SHIFT        0
 #define  SSB_SPROM8_AGAIN3              0xFF00  /* Antenna 3 */
 #define  SSB_SPROM8_AGAIN3_SHIFT        8
+#define SSB_SPROM8_TXRXC                0x00A2
+#define  SSB_SPROM8_TXRXC_TXCHAIN       0x000f
+#define  SSB_SPROM8_TXRXC_TXCHAIN_SHIFT 0
+#define  SSB_SPROM8_TXRXC_RXCHAIN       0x00f0
+#define  SSB_SPROM8_TXRXC_RXCHAIN_SHIFT 4
+#define  SSB_SPROM8_TXRXC_SWITCH        0xff00
+#define  SSB_SPROM8_TXRXC_SWITCH_SHIFT  8
 #define SSB_SPROM8_RSSIPARM2G           0x00A4  /* RSSI params for 2GHz */
 #define  SSB_SPROM8_RSSISMF2G           0x000F
 #define  SSB_SPROM8_RSSISMC2G           0x00F0
@@ -430,6 +444,7 @@
 #define  SSB_SPROM8_TRI5GH_SHIFT        8
 #define SSB_SPROM8_RXPO                 0x00AC  /* RX power offsets */
 #define  SSB_SPROM8_RXPO2G              0x00FF  /* 2GHz RX power offset */
+#define  SSB_SPROM8_RXPO2G_SHIFT        0
 #define  SSB_SPROM8_RXPO5G              0xFF00  /* 5GHz RX power offset */
 #define  SSB_SPROM8_RXPO5G_SHIFT        8
 #define SSB_SPROM8_FEM2G                0x00AE
@@ -445,10 +460,38 @@
 #define  SSB_SROM8_FEM_ANTSWLUT         0xF800
 #define  SSB_SROM8_FEM_ANTSWLUT_SHIFT   11
 #define SSB_SPROM8_THERMAL              0x00B2
-#define SSB_SPROM8_MPWR_RAWTS           0x00B4
-#define SSB_SPROM8_TS_SLP_OPT_CORRX     0x00B6
-#define SSB_SPROM8_FOC_HWIQ_IQSWP       0x00B8
-#define SSB_SPROM8_PHYCAL_TEMPDELTA     0x00BA
+#define  SSB_SPROM8_THERMAL_OFFSET      0x00ff
+#define  SSB_SPROM8_THERMAL_OFFSET_SHIFT        0
+#define  SSB_SPROM8_THERMAL_TRESH       0xff00
+#define  SSB_SPROM8_THERMAL_TRESH_SHIFT 8
+/* Temp sense related entries */
+#define SSB_SPROM8_RAWTS                0x00B4
+#define  SSB_SPROM8_RAWTS_RAWTEMP       0x01ff
+#define  SSB_SPROM8_RAWTS_RAWTEMP_SHIFT 0
+#define  SSB_SPROM8_RAWTS_MEASPOWER     0xfe00
+#define  SSB_SPROM8_RAWTS_MEASPOWER_SHIFT       9
+#define SSB_SPROM8_OPT_CORRX            0x00B6
+#define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE        0x00ff
+#define  SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT  0
+#define  SSB_SPROM8_OPT_CORRX_TEMPCORRX 0xfc00
+#define  SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT   10
+#define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION       0x0300
+#define  SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT 8
+/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
+#define SSB_SPROM8_HWIQ_IQSWP           0x00B8
+#define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR        0x000f
+#define  SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT  0
+#define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP        0x0010
+#define  SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT  4
+#define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
+#define  SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT   5
+#define SSB_SPROM8_TEMPDELTA            0x00BA
+#define  SSB_SPROM8_TEMPDELTA_PHYCAL    0x00ff
+#define  SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT      0
+#define  SSB_SPROM8_TEMPDELTA_PERIOD    0x0f00
+#define  SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT      8
+#define  SSB_SPROM8_TEMPDELTA_HYSTERESIS        0xf000
+#define  SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT  12
 
 /* There are 4 blocks with power info sharing the same layout */
 #define SSB_SROM8_PWR_INFO_CORE0        0x00C0
@@ -513,6 +556,16 @@
 #define SSB_SPROM8_OFDM5GLPO            0x014A  /* 5.2GHz OFDM power offset */
 #define SSB_SPROM8_OFDM5GHPO            0x014E  /* 5.8GHz OFDM power offset */
 
+#define SSB_SPROM8_2G_MCSPO             0x0152
+#define SSB_SPROM8_5G_MCSPO             0x0162
+#define SSB_SPROM8_5GL_MCSPO            0x0172
+#define SSB_SPROM8_5GH_MCSPO            0x0182
+
+#define SSB_SPROM8_CDDPO                0x0192
+#define SSB_SPROM8_STBCPO               0x0194
+#define SSB_SPROM8_BW40PO               0x0196
+#define SSB_SPROM8_BWDUPPO              0x0198
+
 /* Values for boardflags_lo read from SPROM */
 #define SSB_BFL_BTCOEXIST               0x0001  /* implements Bluetooth coexistance */
 #define SSB_BFL_PACTRL                  0x0002  /* GPIO 9 controlling the PA */