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-rw-r--r--include/linux/usb/msm_hsusb.h79
1 files changed, 76 insertions, 3 deletions
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 3657403eac18..00311fe9d0df 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -2,7 +2,7 @@
2 * 2 *
3 * Copyright (C) 2008 Google, Inc. 3 * Copyright (C) 2008 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com> 4 * Author: Brian Swetland <swetland@google.com>
5 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. 5 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
6 * 6 *
7 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
@@ -54,6 +54,64 @@ enum otg_control_type {
54}; 54};
55 55
56/** 56/**
57 * PHY used in
58 *
59 * INVALID_PHY Unsupported PHY
60 * CI_45NM_INTEGRATED_PHY Chipidea 45nm integrated PHY
61 * SNPS_28NM_INTEGRATED_PHY Synopsis 28nm integrated PHY
62 *
63 */
64enum msm_usb_phy_type {
65 INVALID_PHY = 0,
66 CI_45NM_INTEGRATED_PHY,
67 SNPS_28NM_INTEGRATED_PHY,
68};
69
70#define IDEV_CHG_MAX 1500
71#define IUNIT 100
72
73/**
74 * Different states involved in USB charger detection.
75 *
76 * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
77 * process is not yet started.
78 * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
79 * USB_CHG_STATE_DCD_DONE Data pin contact is detected.
80 * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
81 * between SDP and DCP/CDP).
82 * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
83 * between DCP and CDP).
84 * USB_CHG_STATE_DETECTED USB charger type is determined.
85 *
86 */
87enum usb_chg_state {
88 USB_CHG_STATE_UNDEFINED = 0,
89 USB_CHG_STATE_WAIT_FOR_DCD,
90 USB_CHG_STATE_DCD_DONE,
91 USB_CHG_STATE_PRIMARY_DONE,
92 USB_CHG_STATE_SECONDARY_DONE,
93 USB_CHG_STATE_DETECTED,
94};
95
96/**
97 * USB charger types
98 *
99 * USB_INVALID_CHARGER Invalid USB charger.
100 * USB_SDP_CHARGER Standard downstream port. Refers to a downstream port
101 * on USB2.0 compliant host/hub.
102 * USB_DCP_CHARGER Dedicated charger port (AC charger/ Wall charger).
103 * USB_CDP_CHARGER Charging downstream port. Enumeration can happen and
104 * IDEV_CHG_MAX can be drawn irrespective of USB state.
105 *
106 */
107enum usb_chg_type {
108 USB_INVALID_CHARGER = 0,
109 USB_SDP_CHARGER,
110 USB_DCP_CHARGER,
111 USB_CDP_CHARGER,
112};
113
114/**
57 * struct msm_otg_platform_data - platform device data 115 * struct msm_otg_platform_data - platform device data
58 * for msm_otg driver. 116 * for msm_otg driver.
59 * @phy_init_seq: PHY configuration sequence. val, reg pairs 117 * @phy_init_seq: PHY configuration sequence. val, reg pairs
@@ -64,7 +122,8 @@ enum otg_control_type {
64 * @otg_control: OTG switch controlled by user/Id pin 122 * @otg_control: OTG switch controlled by user/Id pin
65 * @default_mode: Default operational mode. Applicable only if 123 * @default_mode: Default operational mode. Applicable only if
66 * OTG switch is controller by user. 124 * OTG switch is controller by user.
67 * 125 * @pclk_src_name: pclk is derived from ebi1_usb_clk in case of 7x27 and 8k
126 * dfab_usb_hs_clk in case of 8660 and 8960.
68 */ 127 */
69struct msm_otg_platform_data { 128struct msm_otg_platform_data {
70 int *phy_init_seq; 129 int *phy_init_seq;
@@ -73,7 +132,9 @@ struct msm_otg_platform_data {
73 enum usb_mode_type mode; 132 enum usb_mode_type mode;
74 enum otg_control_type otg_control; 133 enum otg_control_type otg_control;
75 enum usb_mode_type default_mode; 134 enum usb_mode_type default_mode;
135 enum msm_usb_phy_type phy_type;
76 void (*setup_gpio)(enum usb_otg_state state); 136 void (*setup_gpio)(enum usb_otg_state state);
137 char *pclk_src_name;
77}; 138};
78 139
79/** 140/**
@@ -83,6 +144,7 @@ struct msm_otg_platform_data {
83 * @irq: IRQ number assigned for HSUSB controller. 144 * @irq: IRQ number assigned for HSUSB controller.
84 * @clk: clock struct of usb_hs_clk. 145 * @clk: clock struct of usb_hs_clk.
85 * @pclk: clock struct of usb_hs_pclk. 146 * @pclk: clock struct of usb_hs_pclk.
147 * @pclk_src: pclk source for voting.
86 * @phy_reset_clk: clock struct of usb_phy_clk. 148 * @phy_reset_clk: clock struct of usb_phy_clk.
87 * @core_clk: clock struct of usb_hs_core_clk. 149 * @core_clk: clock struct of usb_hs_core_clk.
88 * @regs: ioremapped register base address. 150 * @regs: ioremapped register base address.
@@ -90,7 +152,12 @@ struct msm_otg_platform_data {
90 * @sm_work: OTG state machine work. 152 * @sm_work: OTG state machine work.
91 * @in_lpm: indicates low power mode (LPM) state. 153 * @in_lpm: indicates low power mode (LPM) state.
92 * @async_int: Async interrupt arrived. 154 * @async_int: Async interrupt arrived.
93 * 155 * @cur_power: The amount of mA available from downstream port.
156 * @chg_work: Charger detection work.
157 * @chg_state: The state of charger detection process.
158 * @chg_type: The type of charger attached.
159 * @dcd_retires: The retry count used to track Data contact
160 * detection process.
94 */ 161 */
95struct msm_otg { 162struct msm_otg {
96 struct otg_transceiver otg; 163 struct otg_transceiver otg;
@@ -98,6 +165,7 @@ struct msm_otg {
98 int irq; 165 int irq;
99 struct clk *clk; 166 struct clk *clk;
100 struct clk *pclk; 167 struct clk *pclk;
168 struct clk *pclk_src;
101 struct clk *phy_reset_clk; 169 struct clk *phy_reset_clk;
102 struct clk *core_clk; 170 struct clk *core_clk;
103 void __iomem *regs; 171 void __iomem *regs;
@@ -107,6 +175,11 @@ struct msm_otg {
107 struct work_struct sm_work; 175 struct work_struct sm_work;
108 atomic_t in_lpm; 176 atomic_t in_lpm;
109 int async_int; 177 int async_int;
178 unsigned cur_power;
179 struct delayed_work chg_work;
180 enum usb_chg_state chg_state;
181 enum usb_chg_type chg_type;
182 u8 dcd_retries;
110}; 183};
111 184
112#endif 185#endif