diff options
Diffstat (limited to 'include/linux/serial_reg.h')
-rw-r--r-- | include/linux/serial_reg.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h index c7a0ce11cd47..c75bda37c18e 100644 --- a/include/linux/serial_reg.h +++ b/include/linux/serial_reg.h | |||
@@ -57,6 +57,7 @@ | |||
57 | * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 | 57 | * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 |
58 | * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 | 58 | * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 |
59 | * TI16C752: 8 16 56 60 8 16 32 56 | 59 | * TI16C752: 8 16 56 60 8 16 32 56 |
60 | * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA | ||
60 | */ | 61 | */ |
61 | #define UART_FCR_R_TRIG_00 0x00 | 62 | #define UART_FCR_R_TRIG_00 0x00 |
62 | #define UART_FCR_R_TRIG_01 0x40 | 63 | #define UART_FCR_R_TRIG_01 0x40 |
@@ -99,6 +100,13 @@ | |||
99 | #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ | 100 | #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ |
100 | #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ | 101 | #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ |
101 | 102 | ||
103 | /* | ||
104 | * Access to some registers depends on register access / configuration | ||
105 | * mode. | ||
106 | */ | ||
107 | #define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */ | ||
108 | #define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */ | ||
109 | |||
102 | #define UART_MCR 4 /* Out: Modem Control Register */ | 110 | #define UART_MCR 4 /* Out: Modem Control Register */ |
103 | #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ | 111 | #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ |
104 | #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ | 112 | #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ |
@@ -111,6 +119,7 @@ | |||
111 | #define UART_MCR_DTR 0x01 /* DTR complement */ | 119 | #define UART_MCR_DTR 0x01 /* DTR complement */ |
112 | 120 | ||
113 | #define UART_LSR 5 /* In: Line Status Register */ | 121 | #define UART_LSR 5 /* In: Line Status Register */ |
122 | #define UART_LSR_FIFOE 0x80 /* Fifo error */ | ||
114 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ | 123 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
115 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ | 124 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
116 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ | 125 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
@@ -341,5 +350,17 @@ | |||
341 | #define UART_OMAP_SYSS 0x16 /* System status register */ | 350 | #define UART_OMAP_SYSS 0x16 /* System status register */ |
342 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ | 351 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ |
343 | 352 | ||
353 | /* | ||
354 | * These are the definitions for the MDR1 register | ||
355 | */ | ||
356 | #define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */ | ||
357 | #define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */ | ||
358 | #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */ | ||
359 | #define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */ | ||
360 | #define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */ | ||
361 | #define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */ | ||
362 | #define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */ | ||
363 | #define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ | ||
364 | |||
344 | #endif /* _LINUX_SERIAL_REG_H */ | 365 | #endif /* _LINUX_SERIAL_REG_H */ |
345 | 366 | ||