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diff --git a/include/linux/rio_regs.h b/include/linux/rio_regs.h
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1/*
2 * RapidIO register definitions
3 *
4 * Copyright 2005 MontaVista Software, Inc.
5 * Matt Porter <mporter@kernel.crashing.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef LINUX_RIO_REGS_H
14#define LINUX_RIO_REGS_H
15
16/*
17 * In RapidIO, each device has a 2MB configuration space that is
18 * accessed via maintenance transactions. Portions of configuration
19 * space are standardized and/or reserved.
20 */
21#define RIO_DEV_ID_CAR 0x00 /* [I] Device Identity CAR */
22#define RIO_DEV_INFO_CAR 0x04 /* [I] Device Information CAR */
23#define RIO_ASM_ID_CAR 0x08 /* [I] Assembly Identity CAR */
24#define RIO_ASM_ID_MASK 0xffff0000 /* [I] Asm ID Mask */
25#define RIO_ASM_VEN_ID_MASK 0x0000ffff /* [I] Asm Vend Mask */
26
27#define RIO_ASM_INFO_CAR 0x0c /* [I] Assembly Information CAR */
28#define RIO_ASM_REV_MASK 0xffff0000 /* [I] Asm Rev Mask */
29#define RIO_EXT_FTR_PTR_MASK 0x0000ffff /* [I] EF_PTR Mask */
30
31#define RIO_PEF_CAR 0x10 /* [I] Processing Element Features CAR */
32#define RIO_PEF_BRIDGE 0x80000000 /* [I] Bridge */
33#define RIO_PEF_MEMORY 0x40000000 /* [I] MMIO */
34#define RIO_PEF_PROCESSOR 0x20000000 /* [I] Processor */
35#define RIO_PEF_SWITCH 0x10000000 /* [I] Switch */
36#define RIO_PEF_INB_MBOX 0x00f00000 /* [II] Mailboxes */
37#define RIO_PEF_INB_MBOX0 0x00800000 /* [II] Mailbox 0 */
38#define RIO_PEF_INB_MBOX1 0x00400000 /* [II] Mailbox 1 */
39#define RIO_PEF_INB_MBOX2 0x00200000 /* [II] Mailbox 2 */
40#define RIO_PEF_INB_MBOX3 0x00100000 /* [II] Mailbox 3 */
41#define RIO_PEF_INB_DOORBELL 0x00080000 /* [II] Doorbells */
42#define RIO_PEF_CTLS 0x00000010 /* [III] CTLS */
43#define RIO_PEF_EXT_FEATURES 0x00000008 /* [I] EFT_PTR valid */
44#define RIO_PEF_ADDR_66 0x00000004 /* [I] 66 bits */
45#define RIO_PEF_ADDR_50 0x00000002 /* [I] 50 bits */
46#define RIO_PEF_ADDR_34 0x00000001 /* [I] 34 bits */
47
48#define RIO_SWP_INFO_CAR 0x14 /* [I] Switch Port Information CAR */
49#define RIO_SWP_INFO_PORT_TOTAL_MASK 0x0000ff00 /* [I] Total number of ports */
50#define RIO_SWP_INFO_PORT_NUM_MASK 0x000000ff /* [I] Maintenance transaction port number */
51#define RIO_GET_TOTAL_PORTS(x) ((x & RIO_SWP_INFO_PORT_TOTAL_MASK) >> 8)
52
53#define RIO_SRC_OPS_CAR 0x18 /* [I] Source Operations CAR */
54#define RIO_SRC_OPS_READ 0x00008000 /* [I] Read op */
55#define RIO_SRC_OPS_WRITE 0x00004000 /* [I] Write op */
56#define RIO_SRC_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
57#define RIO_SRC_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */
58#define RIO_SRC_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */
59#define RIO_SRC_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */
60#define RIO_SRC_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */
61#define RIO_SRC_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */
62#define RIO_SRC_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */
63#define RIO_SRC_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */
64#define RIO_SRC_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */
65#define RIO_SRC_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
66
67#define RIO_DST_OPS_CAR 0x1c /* Destination Operations CAR */
68#define RIO_DST_OPS_READ 0x00008000 /* [I] Read op */
69#define RIO_DST_OPS_WRITE 0x00004000 /* [I] Write op */
70#define RIO_DST_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
71#define RIO_DST_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */
72#define RIO_DST_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */
73#define RIO_DST_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */
74#define RIO_DST_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */
75#define RIO_DST_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */
76#define RIO_DST_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */
77#define RIO_DST_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */
78#define RIO_DST_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */
79#define RIO_DST_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
80
81#define RIO_OPS_READ 0x00008000 /* [I] Read op */
82#define RIO_OPS_WRITE 0x00004000 /* [I] Write op */
83#define RIO_OPS_STREAM_WRITE 0x00002000 /* [I] Str-write op */
84#define RIO_OPS_WRITE_RESPONSE 0x00001000 /* [I] Write/resp op */
85#define RIO_OPS_DATA_MSG 0x00000800 /* [II] Data msg op */
86#define RIO_OPS_DOORBELL 0x00000400 /* [II] Doorbell op */
87#define RIO_OPS_ATOMIC_TST_SWP 0x00000100 /* [I] Atomic TAS op */
88#define RIO_OPS_ATOMIC_INC 0x00000080 /* [I] Atomic inc op */
89#define RIO_OPS_ATOMIC_DEC 0x00000040 /* [I] Atomic dec op */
90#define RIO_OPS_ATOMIC_SET 0x00000020 /* [I] Atomic set op */
91#define RIO_OPS_ATOMIC_CLR 0x00000010 /* [I] Atomic clr op */
92#define RIO_OPS_PORT_WRITE 0x00000004 /* [I] Port-write op */
93
94 /* 0x20-0x3c *//* Reserved */
95
96#define RIO_MBOX_CSR 0x40 /* [II] Mailbox CSR */
97#define RIO_MBOX0_AVAIL 0x80000000 /* [II] Mbox 0 avail */
98#define RIO_MBOX0_FULL 0x40000000 /* [II] Mbox 0 full */
99#define RIO_MBOX0_EMPTY 0x20000000 /* [II] Mbox 0 empty */
100#define RIO_MBOX0_BUSY 0x10000000 /* [II] Mbox 0 busy */
101#define RIO_MBOX0_FAIL 0x08000000 /* [II] Mbox 0 fail */
102#define RIO_MBOX0_ERROR 0x04000000 /* [II] Mbox 0 error */
103#define RIO_MBOX1_AVAIL 0x00800000 /* [II] Mbox 1 avail */
104#define RIO_MBOX1_FULL 0x00200000 /* [II] Mbox 1 full */
105#define RIO_MBOX1_EMPTY 0x00200000 /* [II] Mbox 1 empty */
106#define RIO_MBOX1_BUSY 0x00100000 /* [II] Mbox 1 busy */
107#define RIO_MBOX1_FAIL 0x00080000 /* [II] Mbox 1 fail */
108#define RIO_MBOX1_ERROR 0x00040000 /* [II] Mbox 1 error */
109#define RIO_MBOX2_AVAIL 0x00008000 /* [II] Mbox 2 avail */
110#define RIO_MBOX2_FULL 0x00004000 /* [II] Mbox 2 full */
111#define RIO_MBOX2_EMPTY 0x00002000 /* [II] Mbox 2 empty */
112#define RIO_MBOX2_BUSY 0x00001000 /* [II] Mbox 2 busy */
113#define RIO_MBOX2_FAIL 0x00000800 /* [II] Mbox 2 fail */
114#define RIO_MBOX2_ERROR 0x00000400 /* [II] Mbox 2 error */
115#define RIO_MBOX3_AVAIL 0x00000080 /* [II] Mbox 3 avail */
116#define RIO_MBOX3_FULL 0x00000040 /* [II] Mbox 3 full */
117#define RIO_MBOX3_EMPTY 0x00000020 /* [II] Mbox 3 empty */
118#define RIO_MBOX3_BUSY 0x00000010 /* [II] Mbox 3 busy */
119#define RIO_MBOX3_FAIL 0x00000008 /* [II] Mbox 3 fail */
120#define RIO_MBOX3_ERROR 0x00000004 /* [II] Mbox 3 error */
121
122#define RIO_WRITE_PORT_CSR 0x44 /* [I] Write Port CSR */
123#define RIO_DOORBELL_CSR 0x44 /* [II] Doorbell CSR */
124#define RIO_DOORBELL_AVAIL 0x80000000 /* [II] Doorbell avail */
125#define RIO_DOORBELL_FULL 0x40000000 /* [II] Doorbell full */
126#define RIO_DOORBELL_EMPTY 0x20000000 /* [II] Doorbell empty */
127#define RIO_DOORBELL_BUSY 0x10000000 /* [II] Doorbell busy */
128#define RIO_DOORBELL_FAILED 0x08000000 /* [II] Doorbell failed */
129#define RIO_DOORBELL_ERROR 0x04000000 /* [II] Doorbell error */
130#define RIO_WRITE_PORT_AVAILABLE 0x00000080 /* [I] Write Port Available */
131#define RIO_WRITE_PORT_FULL 0x00000040 /* [I] Write Port Full */
132#define RIO_WRITE_PORT_EMPTY 0x00000020 /* [I] Write Port Empty */
133#define RIO_WRITE_PORT_BUSY 0x00000010 /* [I] Write Port Busy */
134#define RIO_WRITE_PORT_FAILED 0x00000008 /* [I] Write Port Failed */
135#define RIO_WRITE_PORT_ERROR 0x00000004 /* [I] Write Port Error */
136
137 /* 0x48 *//* Reserved */
138
139#define RIO_PELL_CTRL_CSR 0x4c /* [I] PE Logical Layer Control CSR */
140#define RIO_PELL_ADDR_66 0x00000004 /* [I] 66-bit addr */
141#define RIO_PELL_ADDR_50 0x00000002 /* [I] 50-bit addr */
142#define RIO_PELL_ADDR_34 0x00000001 /* [I] 34-bit addr */
143
144 /* 0x50-0x54 *//* Reserved */
145
146#define RIO_LCSH_BA 0x58 /* [I] LCS High Base Address */
147#define RIO_LCSL_BA 0x5c /* [I] LCS Base Address */
148
149#define RIO_DID_CSR 0x60 /* [III] Base Device ID CSR */
150
151 /* 0x64 *//* Reserved */
152
153#define RIO_HOST_DID_LOCK_CSR 0x68 /* [III] Host Base Device ID Lock CSR */
154#define RIO_COMPONENT_TAG_CSR 0x6c /* [III] Component Tag CSR */
155
156 /* 0x70-0xf8 *//* Reserved */
157 /* 0x100-0xfff8 *//* [I] Extended Features Space */
158 /* 0x10000-0xfffff8 *//* [I] Implementation-defined Space */
159
160/*
161 * Extended Features Space is a configuration space area where
162 * functionality is mapped into extended feature blocks via a
163 * singly linked list of extended feature pointers (EFT_PTR).
164 *
165 * Each extended feature block can be identified/located in
166 * Extended Features Space by walking the extended feature
167 * list starting with the Extended Feature Pointer located
168 * in the Assembly Information CAR.
169 *
170 * Extended Feature Blocks (EFBs) are identified with an assigned
171 * EFB ID. Extended feature block offsets in the definitions are
172 * relative to the offset of the EFB within the Extended Features
173 * Space.
174 */
175
176/* Helper macros to parse the Extended Feature Block header */
177#define RIO_EFB_PTR_MASK 0xffff0000
178#define RIO_EFB_ID_MASK 0x0000ffff
179#define RIO_GET_BLOCK_PTR(x) ((x & RIO_EFB_PTR_MASK) >> 16)
180#define RIO_GET_BLOCK_ID(x) (x & RIO_EFB_ID_MASK)
181
182/* Extended Feature Block IDs */
183#define RIO_EFB_PAR_EP_ID 0x0001 /* [IV] LP/LVDS EP Devices */
184#define RIO_EFB_PAR_EP_REC_ID 0x0002 /* [IV] LP/LVDS EP Recovery Devices */
185#define RIO_EFB_PAR_EP_FREE_ID 0x0003 /* [IV] LP/LVDS EP Free Devices */
186#define RIO_EFB_SER_EP_ID 0x0004 /* [VI] LP/Serial EP Devices */
187#define RIO_EFB_SER_EP_REC_ID 0x0005 /* [VI] LP/Serial EP Recovery Devices */
188#define RIO_EFB_SER_EP_FREE_ID 0x0006 /* [VI] LP/Serial EP Free Devices */
189
190/*
191 * Physical 8/16 LP-LVDS
192 * ID=0x0001, Generic End Point Devices
193 * ID=0x0002, Generic End Point Devices, software assisted recovery option
194 * ID=0x0003, Generic End Point Free Devices
195 *
196 * Physical LP-Serial
197 * ID=0x0004, Generic End Point Devices
198 * ID=0x0005, Generic End Point Devices, software assisted recovery option
199 * ID=0x0006, Generic End Point Free Devices
200 */
201#define RIO_PORT_MNT_HEADER 0x0000
202#define RIO_PORT_REQ_CTL_CSR 0x0020
203#define RIO_PORT_RSP_CTL_CSR 0x0024 /* 0x0001/0x0002 */
204#define RIO_PORT_GEN_CTL_CSR 0x003c
205#define RIO_PORT_GEN_HOST 0x80000000
206#define RIO_PORT_GEN_MASTER 0x40000000
207#define RIO_PORT_GEN_DISCOVERED 0x20000000
208#define RIO_PORT_N_MNT_REQ_CSR(x) (0x0040 + x*0x20) /* 0x0002 */
209#define RIO_PORT_N_MNT_RSP_CSR(x) (0x0044 + x*0x20) /* 0x0002 */
210#define RIO_PORT_N_ACK_STS_CSR(x) (0x0048 + x*0x20) /* 0x0002 */
211#define RIO_PORT_N_ERR_STS_CSR(x) (0x58 + x*0x20)
212#define PORT_N_ERR_STS_PORT_OK 0x00000002
213#define RIO_PORT_N_CTL_CSR(x) (0x5c + x*0x20)
214
215#endif /* LINUX_RIO_REGS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 11:25:18 -0500