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-rw-r--r--include/linux/pci_regs.h38
1 files changed, 37 insertions, 1 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 027815b4635e..616bf8b3c8b5 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -235,7 +235,7 @@
235#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ 235#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */
236#define PCI_PM_CTRL 4 /* PM control and status register */ 236#define PCI_PM_CTRL 4 /* PM control and status register */
237#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 237#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
238#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */ 238#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
239#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 239#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
240#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 240#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
241#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 241#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
@@ -375,6 +375,8 @@
375#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ 375#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
376#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ 376#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
377#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ 377#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
378#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
379#define PCI_EXP_TYPE_RC_EC 0x10 /* Root Complex Event Collector */
378#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ 380#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
379#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ 381#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
380#define PCI_EXP_DEVCAP 4 /* Device capabilities */ 382#define PCI_EXP_DEVCAP 4 /* Device capabilities */
@@ -487,6 +489,8 @@
487#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */ 489#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
488#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ 490#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
489#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */ 491#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */
492#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
493#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
490 494
491/* Extended Capabilities (PCI-X 2.0 and Express) */ 495/* Extended Capabilities (PCI-X 2.0 and Express) */
492#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 496#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
@@ -498,6 +502,7 @@
498#define PCI_EXT_CAP_ID_DSN 3 502#define PCI_EXT_CAP_ID_DSN 3
499#define PCI_EXT_CAP_ID_PWR 4 503#define PCI_EXT_CAP_ID_PWR 4
500#define PCI_EXT_CAP_ID_ARI 14 504#define PCI_EXT_CAP_ID_ARI 14
505#define PCI_EXT_CAP_ID_SRIOV 16
501 506
502/* Advanced Error Reporting */ 507/* Advanced Error Reporting */
503#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ 508#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
@@ -615,4 +620,35 @@
615#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ 620#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
616#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ 621#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
617 622
623/* Single Root I/O Virtualization */
624#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
625#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */
626#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */
627#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
628#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
629#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */
630#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */
631#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
632#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
633#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
634#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */
635#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
636#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
637#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
638#define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */
639#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */
640#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */
641#define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */
642#define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */
643#define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */
644#define PCI_SRIOV_BAR 0x24 /* VF BAR0 */
645#define PCI_SRIOV_NUM_BARS 6 /* Number of VF BARs */
646#define PCI_SRIOV_VFM 0x3c /* VF Migration State Array Offset*/
647#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) /* State BIR */
648#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */
649#define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */
650#define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */
651#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */
652#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */
653
618#endif /* LINUX_PCI_REGS_H */ 654#endif /* LINUX_PCI_REGS_H */