1 files changed, 19 insertions, 17 deletions

diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index b5d9657f3100..e41a10f5ae83 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -392,7 +392,7 @@
 #define  PCI_EXP_TYPE_DOWNSTREAM 0x6    /* Downstream Port */
 #define  PCI_EXP_TYPE_PCI_BRIDGE 0x7    /* PCI/PCI-X Bridge */
 #define  PCI_EXP_TYPE_RC_END    0x9     /* Root Complex Integrated Endpoint */
-#define  PCI_EXP_TYPE_RC_EC     0x10    /* Root Complex Event Collector */
+#define  PCI_EXP_TYPE_RC_EC     0xa     /* Root Complex Event Collector */
 #define PCI_EXP_FLAGS_SLOT      0x0100  /* Slot implemented */
 #define PCI_EXP_FLAGS_IRQ       0x3e00  /* Interrupt message number */
 #define PCI_EXP_DEVCAP          4       /* Device capabilities */
@@ -537,7 +537,9 @@
 #define PCI_EXT_CAP_ID_ARI      14
 #define PCI_EXT_CAP_ID_ATS      15
 #define PCI_EXT_CAP_ID_SRIOV    16
+#define PCI_EXT_CAP_ID_PRI      19
 #define PCI_EXT_CAP_ID_LTR      24
+#define PCI_EXT_CAP_ID_PASID    27
 
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS    4       /* Uncorrectable Error Status */
@@ -664,24 +666,24 @@
 #define  PCI_ATS_MIN_STU        12      /* shift of minimum STU block */
 
 /* Page Request Interface */
-#define PCI_PRI_CAP             0x13    /* PRI capability ID */
-#define PCI_PRI_CONTROL_OFF     0x04    /* Offset of control register */
-#define PCI_PRI_STATUS_OFF      0x06    /* Offset of status register */
-#define PCI_PRI_ENABLE          0x0001  /* Enable mask */
-#define PCI_PRI_RESET           0x0002  /* Reset bit mask */
-#define PCI_PRI_STATUS_RF       0x0001  /* Request Failure */
-#define PCI_PRI_STATUS_UPRGI    0x0002  /* Unexpected PRG index */
-#define PCI_PRI_STATUS_STOPPED  0x0100  /* PRI Stopped */
-#define PCI_PRI_MAX_REQ_OFF     0x08    /* Cap offset for max reqs supported */
-#define PCI_PRI_ALLOC_REQ_OFF   0x0c    /* Cap offset for max reqs allowed */
+#define PCI_PRI_CTRL            0x04    /* PRI control register */
+#define  PCI_PRI_CTRL_ENABLE    0x01    /* Enable */
+#define  PCI_PRI_CTRL_RESET     0x02    /* Reset */
+#define PCI_PRI_STATUS          0x06    /* PRI status register */
+#define  PCI_PRI_STATUS_RF      0x001   /* Response Failure */
+#define  PCI_PRI_STATUS_UPRGI   0x002   /* Unexpected PRG index */
+#define  PCI_PRI_STATUS_STOPPED 0x100   /* PRI Stopped */
+#define PCI_PRI_MAX_REQ         0x08    /* PRI max reqs supported */
+#define PCI_PRI_ALLOC_REQ       0x0c    /* PRI max reqs allowed */
 
 /* PASID capability */
-#define PCI_PASID_CAP           0x1b    /* PASID capability ID */
-#define PCI_PASID_CAP_OFF       0x04    /* PASID feature register */
-#define PCI_PASID_CONTROL_OFF   0x06    /* PASID control register */
-#define PCI_PASID_ENABLE        0x01    /* Enable/Supported bit */
-#define PCI_PASID_EXEC          0x02    /* Exec permissions Enable/Supported */
-#define PCI_PASID_PRIV          0x04    /* Priviledge Mode Enable/Support */
+#define PCI_PASID_CAP           0x04    /* PASID feature register */
+#define  PCI_PASID_CAP_EXEC     0x02    /* Exec permissions Supported */
+#define  PCI_PASID_CAP_PRIV     0x04    /* Priviledge Mode Supported */
+#define PCI_PASID_CTRL          0x06    /* PASID control register */
+#define  PCI_PASID_CTRL_ENABLE  0x01    /* Enable bit */
+#define  PCI_PASID_CTRL_EXEC    0x02    /* Exec permissions Enable */
+#define  PCI_PASID_CTRL_PRIV    0x04    /* Priviledge Mode Enable */
 
 /* Single Root I/O Virtualization */
 #define PCI_SRIOV_CAP           0x04    /* SR-IOV Capabilities */