1 files changed, 33 insertions, 4 deletions

diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 455b9ccdfca7..e8840964aca1 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -223,7 +223,7 @@
 #define  PCI_PM_CAP_PME_CLOCK   0x0008  /* PME clock required */
 #define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
 #define  PCI_PM_CAP_DSI         0x0020  /* Device specific initialization */
-#define  PCI_PM_CAP_AUX_POWER   0x01C0  /* Auxilliary power support mask */
+#define  PCI_PM_CAP_AUX_POWER   0x01C0  /* Auxiliary power support mask */
 #define  PCI_PM_CAP_D1          0x0200  /* D1 power state support */
 #define  PCI_PM_CAP_D2          0x0400  /* D2 power state support */
 #define  PCI_PM_CAP_PME         0x0800  /* PME pin supported */
@@ -300,12 +300,22 @@
 #define PCI_MSI_DATA_64         12      /* 16 bits of data for 64-bit devices */
 #define PCI_MSI_MASK_64         16      /* Mask bits register for 64-bit devices */
 
-/* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */
+/* MSI-X registers */
 #define PCI_MSIX_FLAGS          2
 #define  PCI_MSIX_FLAGS_QSIZE   0x7FF
 #define  PCI_MSIX_FLAGS_ENABLE  (1 << 15)
 #define  PCI_MSIX_FLAGS_MASKALL (1 << 14)
-#define PCI_MSIX_FLAGS_BIRMASK  (7 << 0)
+#define PCI_MSIX_TABLE          4
+#define PCI_MSIX_PBA            8
+#define  PCI_MSIX_FLAGS_BIRMASK (7 << 0)
+
+/* MSI-X entry's format */
+#define PCI_MSIX_ENTRY_SIZE             16
+#define  PCI_MSIX_ENTRY_LOWER_ADDR      0
+#define  PCI_MSIX_ENTRY_UPPER_ADDR      4
+#define  PCI_MSIX_ENTRY_DATA            8
+#define  PCI_MSIX_ENTRY_VECTOR_CTRL     12
+#define   PCI_MSIX_ENTRY_CTRL_MASKBIT   1
 
 /* CompactPCI Hotswap Register */
 
@@ -425,7 +435,7 @@
 #define  PCI_EXP_LNKCAP_L0SEL   0x00007000 /* L0s Exit Latency */
 #define  PCI_EXP_LNKCAP_L1EL    0x00038000 /* L1 Exit Latency */
 #define  PCI_EXP_LNKCAP_CLKPM   0x00040000 /* L1 Clock Power Management */
-#define  PCI_EXP_LNKCAP_SDERC   0x00080000 /* Suprise Down Error Reporting Capable */
+#define  PCI_EXP_LNKCAP_SDERC   0x00080000 /* Surprise Down Error Reporting Capable */
 #define  PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
 #define  PCI_EXP_LNKCAP_LBNC    0x00200000 /* Link Bandwidth Notification Capability */
 #define  PCI_EXP_LNKCAP_PN      0xff000000 /* Port Number */
@@ -494,10 +504,22 @@
 #define  PCI_EXP_RTCTL_CRSSVE   0x10    /* CRS Software Visibility Enable */
 #define PCI_EXP_RTCAP           30      /* Root Capabilities */
 #define PCI_EXP_RTSTA           32      /* Root Status */
+#define PCI_EXP_RTSTA_PME       0x10000 /* PME status */
+#define PCI_EXP_RTSTA_PENDING   0x20000 /* PME pending */
 #define PCI_EXP_DEVCAP2         36      /* Device Capabilities 2 */
 #define  PCI_EXP_DEVCAP2_ARI    0x20    /* Alternative Routing-ID */
+#define  PCI_EXP_DEVCAP2_LTR    0x800   /* Latency tolerance reporting */
+#define  PCI_EXP_OBFF_MASK      0xc0000 /* OBFF support mechanism */
+#define  PCI_EXP_OBFF_MSG       0x40000 /* New message signaling */
+#define  PCI_EXP_OBFF_WAKE      0x80000 /* Re-use WAKE# for OBFF */
 #define PCI_EXP_DEVCTL2         40      /* Device Control 2 */
 #define  PCI_EXP_DEVCTL2_ARI    0x20    /* Alternative Routing-ID */
+#define  PCI_EXP_IDO_REQ_EN     0x100   /* ID-based ordering request enable */
+#define  PCI_EXP_IDO_CMP_EN     0x200   /* ID-based ordering completion enable */
+#define  PCI_EXP_LTR_EN         0x400   /* Latency tolerance reporting */
+#define  PCI_EXP_OBFF_MSGA_EN   0x2000  /* OBFF enable with Message type A */
+#define  PCI_EXP_OBFF_MSGB_EN   0x4000  /* OBFF enable with Message type B */
+#define  PCI_EXP_OBFF_WAKE_EN   0x6000  /* OBFF using WAKE# signaling */
 #define PCI_EXP_LNKCTL2         48      /* Link Control 2 */
 #define PCI_EXP_SLTCTL2         56      /* Slot Control 2 */
 
@@ -515,6 +537,7 @@
 #define PCI_EXT_CAP_ID_ARI      14
 #define PCI_EXT_CAP_ID_ATS      15
 #define PCI_EXT_CAP_ID_SRIOV    16
+#define PCI_EXT_CAP_ID_LTR      24
 
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS    4       /* Uncorrectable Error Status */
@@ -671,6 +694,12 @@
 #define  PCI_SRIOV_VFM_MO       0x2     /* Active.MigrateOut */
 #define  PCI_SRIOV_VFM_AV       0x3     /* Active.Available */
 
+#define PCI_LTR_MAX_SNOOP_LAT   0x4
+#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
+#define  PCI_LTR_VALUE_MASK     0x000003ff
+#define  PCI_LTR_SCALE_MASK     0x00001c00
+#define  PCI_LTR_SCALE_SHIFT    10
+
 /* Access Control Service */
 #define PCI_ACS_CAP             0x04    /* ACS Capability Register */
 #define  PCI_ACS_SV             0x01    /* Source Validation */