1 files changed, 214 insertions, 0 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
new file mode 100644
index 000000000000..53241842a7ab
--- /dev/null
+++ b/include/linux/mtd/spi-nor.h
@@ -0,0 +1,214 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __LINUX_MTD_SPI_NOR_H
+#define __LINUX_MTD_SPI_NOR_H
+/*
+ * Note on opcode nomenclature: some opcodes have a format like
+ * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
+ * of I/O lines used for the opcode, address, and data (respectively). The
+ * FUNCTION has an optional suffix of '4', to represent an opcode which
+ * requires a 4-byte (32-bit) address.
+ */
+/* Flash opcodes. */
+#define SPINOR_OP_WREN          0x06    /* Write enable */
+#define SPINOR_OP_RDSR          0x05    /* Read status register */
+#define SPINOR_OP_WRSR          0x01    /* Write status register 1 byte */
+#define SPINOR_OP_READ          0x03    /* Read data bytes (low frequency) */
+#define SPINOR_OP_READ_FAST     0x0b    /* Read data bytes (high frequency) */
+#define SPINOR_OP_READ_1_1_2    0x3b    /* Read data bytes (Dual SPI) */
+#define SPINOR_OP_READ_1_1_4    0x6b    /* Read data bytes (Quad SPI) */
+#define SPINOR_OP_PP            0x02    /* Page program (up to 256 bytes) */
+#define SPINOR_OP_BE_4K         0x20    /* Erase 4KiB block */
+#define SPINOR_OP_BE_4K_PMC     0xd7    /* Erase 4KiB block on PMC chips */
+#define SPINOR_OP_BE_32K        0x52    /* Erase 32KiB block */
+#define SPINOR_OP_CHIP_ERASE    0xc7    /* Erase whole flash chip */
+#define SPINOR_OP_SE            0xd8    /* Sector erase (usually 64KiB) */
+#define SPINOR_OP_RDID          0x9f    /* Read JEDEC ID */
+#define SPINOR_OP_RDCR          0x35    /* Read configuration register */
+/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
+#define SPINOR_OP_READ4         0x13    /* Read data bytes (low frequency) */
+#define SPINOR_OP_READ4_FAST    0x0c    /* Read data bytes (high frequency) */
+#define SPINOR_OP_READ4_1_1_2   0x3c    /* Read data bytes (Dual SPI) */
+#define SPINOR_OP_READ4_1_1_4   0x6c    /* Read data bytes (Quad SPI) */
+#define SPINOR_OP_PP_4B         0x12    /* Page program (up to 256 bytes) */
+#define SPINOR_OP_SE_4B         0xdc    /* Sector erase (usually 64KiB) */
+/* Used for SST flashes only. */
+#define SPINOR_OP_BP            0x02    /* Byte program */
+#define SPINOR_OP_WRDI          0x04    /* Write disable */
+#define SPINOR_OP_AAI_WP        0xad    /* Auto address increment word program */
+/* Used for Macronix and Winbond flashes. */
+#define SPINOR_OP_EN4B          0xb7    /* Enter 4-byte mode */
+#define SPINOR_OP_EX4B          0xe9    /* Exit 4-byte mode */
+/* Used for Spansion flashes only. */
+#define SPINOR_OP_BRWR          0x17    /* Bank register write */
+/* Status Register bits. */
+#define SR_WIP                  1       /* Write in progress */
+#define SR_WEL                  2       /* Write enable latch */
+/* meaning of other SR_* bits may differ between vendors */
+#define SR_BP0                  4       /* Block protect 0 */
+#define SR_BP1                  8       /* Block protect 1 */
+#define SR_BP2                  0x10    /* Block protect 2 */
+#define SR_SRWD                 0x80    /* SR write protect */
+#define SR_QUAD_EN_MX           0x40    /* Macronix Quad I/O */
+/* Configuration Register bits. */
+#define CR_QUAD_EN_SPAN         0x2     /* Spansion Quad I/O */
+enum read_mode {
+        SPI_NOR_NORMAL = 0,
+        SPI_NOR_FAST,
+        SPI_NOR_DUAL,
+        SPI_NOR_QUAD,
+};
+/**
+ * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer
+ * @wren:               command for "Write Enable", or 0x00 for not required
+ * @cmd:                command for operation
+ * @cmd_pins:           number of pins to send @cmd (1, 2, 4)
+ * @addr:               address for operation
+ * @addr_pins:          number of pins to send @addr (1, 2, 4)
+ * @addr_width:         number of address bytes
+ *                      (3,4, or 0 for address not required)
+ * @mode:               mode data
+ * @mode_pins:          number of pins to send @mode (1, 2, 4)
+ * @mode_cycles:        number of mode cycles (0 for mode not required)
+ * @dummy_cycles:       number of dummy cycles (0 for dummy not required)
+ */
+struct spi_nor_xfer_cfg {
+        u8              wren;
+        u8              cmd;
+        u8              cmd_pins;
+        u32             addr;
+        u8              addr_pins;
+        u8              addr_width;
+        u8              mode;
+        u8              mode_pins;
+        u8              mode_cycles;
+        u8              dummy_cycles;
+};
+#define SPI_NOR_MAX_CMD_SIZE    8
+enum spi_nor_ops {
+        SPI_NOR_OPS_READ = 0,
+        SPI_NOR_OPS_WRITE,
+        SPI_NOR_OPS_ERASE,
+        SPI_NOR_OPS_LOCK,
+        SPI_NOR_OPS_UNLOCK,
+};
+/**
+ * struct spi_nor - Structure for defining a the SPI NOR layer
+ * @mtd:                point to a mtd_info structure
+ * @lock:               the lock for the read/write/erase/lock/unlock operations
+ * @dev:                point to a spi device, or a spi nor controller device.
+ * @page_size:          the page size of the SPI NOR
+ * @addr_width:         number of address bytes
+ * @erase_opcode:       the opcode for erasing a sector
+ * @read_opcode:        the read opcode
+ * @read_dummy:         the dummy needed by the read operation
+ * @program_opcode:     the program opcode
+ * @flash_read:         the mode of the read
+ * @sst_write_second:   used by the SST write operation
+ * @cfg:                used by the read_xfer/write_xfer
+ * @cmd_buf:            used by the write_reg
+ * @prepare:            [OPTIONAL] do some preparations for the
+ *                      read/write/erase/lock/unlock operations
+ * @unprepare:          [OPTIONAL] do some post work after the
+ *                      read/write/erase/lock/unlock operations
+ * @read_xfer:          [OPTIONAL] the read fundamental primitive
+ * @write_xfer:         [OPTIONAL] the writefundamental primitive
+ * @read_reg:           [DRIVER-SPECIFIC] read out the register
+ * @write_reg:          [DRIVER-SPECIFIC] write data to the register
+ * @read_id:            [REPLACEABLE] read out the ID data, and find
+ *                      the proper spi_device_id
+ * @wait_till_ready:    [REPLACEABLE] wait till the NOR becomes ready
+ * @read:               [DRIVER-SPECIFIC] read data from the SPI NOR
+ * @write:              [DRIVER-SPECIFIC] write data to the SPI NOR
+ * @erase:              [DRIVER-SPECIFIC] erase a sector of the SPI NOR
+ *                      at the offset @offs
+ * @priv:               the private data
+ */
+struct spi_nor {
+        struct mtd_info         *mtd;
+        struct mutex            lock;
+        struct device           *dev;
+        u32                     page_size;
+        u8                      addr_width;
+        u8                      erase_opcode;
+        u8                      read_opcode;
+        u8                      read_dummy;
+        u8                      program_opcode;
+        enum read_mode          flash_read;
+        bool                    sst_write_second;
+        struct spi_nor_xfer_cfg cfg;
+        u8                      cmd_buf[SPI_NOR_MAX_CMD_SIZE];
+        int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
+        void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
+        int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
+                         u8 *buf, size_t len);
+        int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
+                          u8 *buf, size_t len);
+        int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
+        int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
+                        int write_enable);
+        const struct spi_device_id *(*read_id)(struct spi_nor *nor);
+        int (*wait_till_ready)(struct spi_nor *nor);
+        int (*read)(struct spi_nor *nor, loff_t from,
+                        size_t len, size_t *retlen, u_char *read_buf);
+        void (*write)(struct spi_nor *nor, loff_t to,
+                        size_t len, size_t *retlen, const u_char *write_buf);
+        int (*erase)(struct spi_nor *nor, loff_t offs);
+        void *priv;
+};
+/**
+ * spi_nor_scan() - scan the SPI NOR
+ * @nor:        the spi_nor structure
+ * @id:         the spi_device_id provided by the driver
+ * @mode:       the read mode supported by the driver
+ *
+ * The drivers can use this fuction to scan the SPI NOR.
+ * In the scanning, it will try to get all the necessary information to
+ * fill the mtd_info{} and the spi_nor{}.
+ *
+ * The board may assigns a spi_device_id with @id which be used to compared with
+ * the spi_device_id detected by the scanning.
+ *
+ * Return: 0 for success, others for failure.
+ */
+int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id,
+                        enum read_mode mode);
+extern const struct spi_device_id spi_nor_ids[];
+/**
+ * spi_nor_match_id() - find the spi_device_id by the name
+ * @name:       the name of the spi_device_id
+ *
+ * The drivers use this function to find the spi_device_id
+ * specified by the @name.
+ *
+ * Return: returns the right spi_device_id pointer on success,
+ *         and returns NULL on failure.
+ */
+const struct spi_device_id *spi_nor_match_id(char *name);
+#endif

diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h new file mode 100644 index 000000000000..53241842a7ab --- /dev/null +++ b/include/linux/mtd/spi-nor.h
@@ -0,0 +1,214 @@
	1	/*
	2	* Copyright (C) 2014 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
	10	#ifndef __LINUX_MTD_SPI_NOR_H
	11	#define __LINUX_MTD_SPI_NOR_H
	12
	13	/*
	14	* Note on opcode nomenclature: some opcodes have a format like
	15	* SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
	16	* of I/O lines used for the opcode, address, and data (respectively). The
	17	* FUNCTION has an optional suffix of '4', to represent an opcode which
	18	* requires a 4-byte (32-bit) address.
	19	*/
	20
	21	/* Flash opcodes. */
	22	#define SPINOR_OP_WREN 0x06 /* Write enable */
	23	#define SPINOR_OP_RDSR 0x05 /* Read status register */
	24	#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
	25	#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
	26	#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
	27	#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
	28	#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
	29	#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
	30	#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
	31	#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
	32	#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
	33	#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
	34	#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
	35	#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
	36	#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
	37
	38	/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
	39	#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
	40	#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
	41	#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
	42	#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
	43	#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
	44	#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
	45
	46	/* Used for SST flashes only. */
	47	#define SPINOR_OP_BP 0x02 /* Byte program */
	48	#define SPINOR_OP_WRDI 0x04 /* Write disable */
	49	#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
	50
	51	/* Used for Macronix and Winbond flashes. */
	52	#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
	53	#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
	54
	55	/* Used for Spansion flashes only. */
	56	#define SPINOR_OP_BRWR 0x17 /* Bank register write */
	57
	58	/* Status Register bits. */
	59	#define SR_WIP 1 /* Write in progress */
	60	#define SR_WEL 2 /* Write enable latch */
	61	/* meaning of other SR_* bits may differ between vendors */
	62	#define SR_BP0 4 /* Block protect 0 */
	63	#define SR_BP1 8 /* Block protect 1 */
	64	#define SR_BP2 0x10 /* Block protect 2 */
	65	#define SR_SRWD 0x80 /* SR write protect */
	66
	67	#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
	68
	69	/* Configuration Register bits. */
	70	#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
	71
	72	enum read_mode {
	73	SPI_NOR_NORMAL = 0,
	74	SPI_NOR_FAST,
	75	SPI_NOR_DUAL,
	76	SPI_NOR_QUAD,
	77	};
	78
	79	/**
	80	* struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer
	81	* @wren: command for "Write Enable", or 0x00 for not required
	82	* @cmd: command for operation
	83	* @cmd_pins: number of pins to send @cmd (1, 2, 4)
	84	* @addr: address for operation
	85	* @addr_pins: number of pins to send @addr (1, 2, 4)
	86	* @addr_width: number of address bytes
	87	* (3,4, or 0 for address not required)
	88	* @mode: mode data
	89	* @mode_pins: number of pins to send @mode (1, 2, 4)
	90	* @mode_cycles: number of mode cycles (0 for mode not required)
	91	* @dummy_cycles: number of dummy cycles (0 for dummy not required)
	92	*/
	93	struct spi_nor_xfer_cfg {
	94	u8 wren;
	95	u8 cmd;
	96	u8 cmd_pins;
	97	u32 addr;
	98	u8 addr_pins;
	99	u8 addr_width;
	100	u8 mode;
	101	u8 mode_pins;
	102	u8 mode_cycles;
	103	u8 dummy_cycles;
	104	};
	105
	106	#define SPI_NOR_MAX_CMD_SIZE 8
	107	enum spi_nor_ops {
	108	SPI_NOR_OPS_READ = 0,
	109	SPI_NOR_OPS_WRITE,
	110	SPI_NOR_OPS_ERASE,
	111	SPI_NOR_OPS_LOCK,
	112	SPI_NOR_OPS_UNLOCK,
	113	};
	114
	115	/**
	116	* struct spi_nor - Structure for defining a the SPI NOR layer
	117	* @mtd: point to a mtd_info structure
	118	* @lock: the lock for the read/write/erase/lock/unlock operations
	119	* @dev: point to a spi device, or a spi nor controller device.
	120	* @page_size: the page size of the SPI NOR
	121	* @addr_width: number of address bytes
	122	* @erase_opcode: the opcode for erasing a sector
	123	* @read_opcode: the read opcode
	124	* @read_dummy: the dummy needed by the read operation
	125	* @program_opcode: the program opcode
	126	* @flash_read: the mode of the read
	127	* @sst_write_second: used by the SST write operation
	128	* @cfg: used by the read_xfer/write_xfer
	129	* @cmd_buf: used by the write_reg
	130	* @prepare: [OPTIONAL] do some preparations for the
	131	* read/write/erase/lock/unlock operations
	132	* @unprepare: [OPTIONAL] do some post work after the
	133	* read/write/erase/lock/unlock operations
	134	* @read_xfer: [OPTIONAL] the read fundamental primitive
	135	* @write_xfer: [OPTIONAL] the writefundamental primitive
	136	* @read_reg: [DRIVER-SPECIFIC] read out the register
	137	* @write_reg: [DRIVER-SPECIFIC] write data to the register
	138	* @read_id: [REPLACEABLE] read out the ID data, and find
	139	* the proper spi_device_id
	140	* @wait_till_ready: [REPLACEABLE] wait till the NOR becomes ready
	141	* @read: [DRIVER-SPECIFIC] read data from the SPI NOR
	142	* @write: [DRIVER-SPECIFIC] write data to the SPI NOR
	143	* @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
	144	* at the offset @offs
	145	* @priv: the private data
	146	*/
	147	struct spi_nor {
	148	struct mtd_info *mtd;
	149	struct mutex lock;
	150	struct device *dev;
	151	u32 page_size;
	152	u8 addr_width;
	153	u8 erase_opcode;
	154	u8 read_opcode;
	155	u8 read_dummy;
	156	u8 program_opcode;
	157	enum read_mode flash_read;
	158	bool sst_write_second;
	159	struct spi_nor_xfer_cfg cfg;
	160	u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
	161
	162	int (prepare)(struct spi_nor nor, enum spi_nor_ops ops);
	163	void (unprepare)(struct spi_nor nor, enum spi_nor_ops ops);
	164	int (read_xfer)(struct spi_nor nor, struct spi_nor_xfer_cfg *cfg,
	165	u8 *buf, size_t len);
	166	int (write_xfer)(struct spi_nor nor, struct spi_nor_xfer_cfg *cfg,
	167	u8 *buf, size_t len);
	168	int (read_reg)(struct spi_nor nor, u8 opcode, u8 *buf, int len);
	169	int (write_reg)(struct spi_nor nor, u8 opcode, u8 *buf, int len,
	170	int write_enable);
	171	const struct spi_device_id (read_id)(struct spi_nor *nor);
	172	int (wait_till_ready)(struct spi_nor nor);
	173
	174	int (read)(struct spi_nor nor, loff_t from,
	175	size_t len, size_t retlen, u_char read_buf);
	176	void (write)(struct spi_nor nor, loff_t to,
	177	size_t len, size_t retlen, const u_char write_buf);
	178	int (erase)(struct spi_nor nor, loff_t offs);
	179
	180	void *priv;
	181	};
	182
	183	/**
	184	* spi_nor_scan() - scan the SPI NOR
	185	* @nor: the spi_nor structure
	186	* @id: the spi_device_id provided by the driver
	187	* @mode: the read mode supported by the driver
	188	*
	189	* The drivers can use this fuction to scan the SPI NOR.
	190	* In the scanning, it will try to get all the necessary information to
	191	* fill the mtd_info{} and the spi_nor{}.
	192	*
	193	* The board may assigns a spi_device_id with @id which be used to compared with
	194	* the spi_device_id detected by the scanning.
	195	*
	196	* Return: 0 for success, others for failure.
	197	*/
	198	int spi_nor_scan(struct spi_nor nor, const struct spi_device_id id,
	199	enum read_mode mode);
	200	extern const struct spi_device_id spi_nor_ids[];
	201
	202	/**
	203	* spi_nor_match_id() - find the spi_device_id by the name
	204	* @name: the name of the spi_device_id
	205	*
	206	* The drivers use this function to find the spi_device_id
	207	* specified by the @name.
	208	*
	209	* Return: returns the right spi_device_id pointer on success,
	210	* and returns NULL on failure.
	211	*/
	212	const struct spi_device_id spi_nor_match_id(char name);
	213
	214	#endif