1 files changed, 16 insertions, 2 deletions

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index e4d451e4600b..3d4ea7eb2b68 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -455,8 +455,21 @@ struct nand_hw_control {
  *              be provided if an hardware ECC is available
  * @calculate:  function for ECC calculation or readback from ECC hardware
  * @correct:    function for ECC correction, matching to ECC generator (sw/hw)
- * @read_page_raw:      function to read a raw page without ECC
- * @write_page_raw:     function to write a raw page without ECC
+ * @read_page_raw:      function to read a raw page without ECC. This function
+ *                      should hide the specific layout used by the ECC
+ *                      controller and always return contiguous in-band and
+ *                      out-of-band data even if they're not stored
+ *                      contiguously on the NAND chip (e.g.
+ *                      NAND_ECC_HW_SYNDROME interleaves in-band and
+ *                      out-of-band data).
+ * @write_page_raw:     function to write a raw page without ECC. This function
+ *                      should hide the specific layout used by the ECC
+ *                      controller and consider the passed data as contiguous
+ *                      in-band and out-of-band data. ECC controller is
+ *                      responsible for doing the appropriate transformations
+ *                      to adapt to its specific layout (e.g.
+ *                      NAND_ECC_HW_SYNDROME interleaves in-band and
+ *                      out-of-band data).
  * @read_page:  function to read a page according to the ECC generator
  *              requirements; returns maximum number of bitflips corrected in
  *              any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
@@ -723,6 +736,7 @@ struct nand_chip {
 #define NAND_MFR_EON            0x92
 #define NAND_MFR_SANDISK        0x45
 #define NAND_MFR_INTEL          0x89
+#define NAND_MFR_ATO            0x9b
 
 /* The maximum expected count of bytes in the NAND ID sequence */
 #define NAND_MAX_ID_LEN 8