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-rw-r--r--include/linux/mtd/fsmc.h169
1 files changed, 91 insertions, 78 deletions
diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h
index 6987995ad3cf..b20029221fb1 100644
--- a/include/linux/mtd/fsmc.h
+++ b/include/linux/mtd/fsmc.h
@@ -26,95 +26,83 @@
26#define FSMC_NAND_BW8 1 26#define FSMC_NAND_BW8 1
27#define FSMC_NAND_BW16 2 27#define FSMC_NAND_BW16 2
28 28
29/*
30 * The placement of the Command Latch Enable (CLE) and
31 * Address Latch Enable (ALE) is twisted around in the
32 * SPEAR310 implementation.
33 */
34#if defined(CONFIG_MACH_SPEAR310)
35#define PLAT_NAND_CLE (1 << 17)
36#define PLAT_NAND_ALE (1 << 16)
37#else
38#define PLAT_NAND_CLE (1 << 16)
39#define PLAT_NAND_ALE (1 << 17)
40#endif
41
42#define FSMC_MAX_NOR_BANKS 4 29#define FSMC_MAX_NOR_BANKS 4
43#define FSMC_MAX_NAND_BANKS 4 30#define FSMC_MAX_NAND_BANKS 4
44 31
45#define FSMC_FLASH_WIDTH8 1 32#define FSMC_FLASH_WIDTH8 1
46#define FSMC_FLASH_WIDTH16 2 33#define FSMC_FLASH_WIDTH16 2
47 34
48struct fsmc_nor_bank_regs { 35/* fsmc controller registers for NOR flash */
49 uint32_t ctrl; 36#define CTRL 0x0
50 uint32_t ctrl_tim; 37 /* ctrl register definitions */
51}; 38 #define BANK_ENABLE (1 << 0)
52 39 #define MUXED (1 << 1)
53/* ctrl register definitions */ 40 #define NOR_DEV (2 << 2)
54#define BANK_ENABLE (1 << 0) 41 #define WIDTH_8 (0 << 4)
55#define MUXED (1 << 1) 42 #define WIDTH_16 (1 << 4)
56#define NOR_DEV (2 << 2) 43 #define RSTPWRDWN (1 << 6)
57#define WIDTH_8 (0 << 4) 44 #define WPROT (1 << 7)
58#define WIDTH_16 (1 << 4) 45 #define WRT_ENABLE (1 << 12)
59#define RSTPWRDWN (1 << 6) 46 #define WAIT_ENB (1 << 13)
60#define WPROT (1 << 7) 47
61#define WRT_ENABLE (1 << 12) 48#define CTRL_TIM 0x4
62#define WAIT_ENB (1 << 13) 49 /* ctrl_tim register definitions */
63 50
64/* ctrl_tim register definitions */ 51#define FSMC_NOR_BANK_SZ 0x8
65
66struct fsmc_nand_bank_regs {
67 uint32_t pc;
68 uint32_t sts;
69 uint32_t comm;
70 uint32_t attrib;
71 uint32_t ioata;
72 uint32_t ecc1;
73 uint32_t ecc2;
74 uint32_t ecc3;
75};
76
77#define FSMC_NOR_REG_SIZE 0x40 52#define FSMC_NOR_REG_SIZE 0x40
78 53
79struct fsmc_regs { 54#define FSMC_NOR_REG(base, bank, reg) (base + \
80 struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS]; 55 FSMC_NOR_BANK_SZ * (bank) + \
81 uint8_t reserved_1[0x40 - 0x20]; 56 reg)
82 struct fsmc_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS]; 57
83 uint8_t reserved_2[0xfe0 - 0xc0]; 58/* fsmc controller registers for NAND flash */
84 uint32_t peripid0; /* 0xfe0 */ 59#define PC 0x00
85 uint32_t peripid1; /* 0xfe4 */ 60 /* pc register definitions */
86 uint32_t peripid2; /* 0xfe8 */ 61 #define FSMC_RESET (1 << 0)
87 uint32_t peripid3; /* 0xfec */ 62 #define FSMC_WAITON (1 << 1)
88 uint32_t pcellid0; /* 0xff0 */ 63 #define FSMC_ENABLE (1 << 2)
89 uint32_t pcellid1; /* 0xff4 */ 64 #define FSMC_DEVTYPE_NAND (1 << 3)
90 uint32_t pcellid2; /* 0xff8 */ 65 #define FSMC_DEVWID_8 (0 << 4)
91 uint32_t pcellid3; /* 0xffc */ 66 #define FSMC_DEVWID_16 (1 << 4)
92}; 67 #define FSMC_ECCEN (1 << 6)
68 #define FSMC_ECCPLEN_512 (0 << 7)
69 #define FSMC_ECCPLEN_256 (1 << 7)
70 #define FSMC_TCLR_1 (1)
71 #define FSMC_TCLR_SHIFT (9)
72 #define FSMC_TCLR_MASK (0xF)
73 #define FSMC_TAR_1 (1)
74 #define FSMC_TAR_SHIFT (13)
75 #define FSMC_TAR_MASK (0xF)
76#define STS 0x04
77 /* sts register definitions */
78 #define FSMC_CODE_RDY (1 << 15)
79#define COMM 0x08
80 /* comm register definitions */
81 #define FSMC_TSET_0 0
82 #define FSMC_TSET_SHIFT 0
83 #define FSMC_TSET_MASK 0xFF
84 #define FSMC_TWAIT_6 6
85 #define FSMC_TWAIT_SHIFT 8
86 #define FSMC_TWAIT_MASK 0xFF
87 #define FSMC_THOLD_4 4
88 #define FSMC_THOLD_SHIFT 16
89 #define FSMC_THOLD_MASK 0xFF
90 #define FSMC_THIZ_1 1
91 #define FSMC_THIZ_SHIFT 24
92 #define FSMC_THIZ_MASK 0xFF
93#define ATTRIB 0x0C
94#define IOATA 0x10
95#define ECC1 0x14
96#define ECC2 0x18
97#define ECC3 0x1C
98#define FSMC_NAND_BANK_SZ 0x20
99
100#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
101 (FSMC_NAND_BANK_SZ * (bank)) + \
102 reg)
93 103
94#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ) 104#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
95 105
96/* pc register definitions */
97#define FSMC_RESET (1 << 0)
98#define FSMC_WAITON (1 << 1)
99#define FSMC_ENABLE (1 << 2)
100#define FSMC_DEVTYPE_NAND (1 << 3)
101#define FSMC_DEVWID_8 (0 << 4)
102#define FSMC_DEVWID_16 (1 << 4)
103#define FSMC_ECCEN (1 << 6)
104#define FSMC_ECCPLEN_512 (0 << 7)
105#define FSMC_ECCPLEN_256 (1 << 7)
106#define FSMC_TCLR_1 (1 << 9)
107#define FSMC_TAR_1 (1 << 13)
108
109/* sts register definitions */
110#define FSMC_CODE_RDY (1 << 15)
111
112/* comm register definitions */
113#define FSMC_TSET_0 (0 << 0)
114#define FSMC_TWAIT_6 (6 << 8)
115#define FSMC_THOLD_4 (4 << 16)
116#define FSMC_THIZ_1 (1 << 24)
117
118/* 106/*
119 * There are 13 bytes of ecc for every 512 byte block in FSMC version 8 107 * There are 13 bytes of ecc for every 512 byte block in FSMC version 8
120 * and it has to be read consecutively and immediately after the 512 108 * and it has to be read consecutively and immediately after the 512
@@ -133,6 +121,20 @@ struct fsmc_eccplace {
133 struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES]; 121 struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];
134}; 122};
135 123
124struct fsmc_nand_timings {
125 uint8_t tclr;
126 uint8_t tar;
127 uint8_t thiz;
128 uint8_t thold;
129 uint8_t twait;
130 uint8_t tset;
131};
132
133enum access_mode {
134 USE_DMA_ACCESS = 1,
135 USE_WORD_ACCESS,
136};
137
136/** 138/**
137 * fsmc_nand_platform_data - platform specific NAND controller config 139 * fsmc_nand_platform_data - platform specific NAND controller config
138 * @partitions: partition table for the platform, use a default fallback 140 * @partitions: partition table for the platform, use a default fallback
@@ -146,12 +148,23 @@ struct fsmc_eccplace {
146 * this may be set to NULL 148 * this may be set to NULL
147 */ 149 */
148struct fsmc_nand_platform_data { 150struct fsmc_nand_platform_data {
151 struct fsmc_nand_timings *nand_timings;
149 struct mtd_partition *partitions; 152 struct mtd_partition *partitions;
150 unsigned int nr_partitions; 153 unsigned int nr_partitions;
151 unsigned int options; 154 unsigned int options;
152 unsigned int width; 155 unsigned int width;
153 unsigned int bank; 156 unsigned int bank;
157
158 /* CLE, ALE offsets */
159 unsigned int cle_off;
160 unsigned int ale_off;
161 enum access_mode mode;
162
154 void (*select_bank)(uint32_t bank, uint32_t busw); 163 void (*select_bank)(uint32_t bank, uint32_t busw);
164
165 /* priv structures for dma accesses */
166 void *read_dma_priv;
167 void *write_dma_priv;
155}; 168};
156 169
157extern int __init fsmc_nor_init(struct platform_device *pdev, 170extern int __init fsmc_nor_init(struct platform_device *pdev,
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-19 04:00:16 -0400