aboutsummaryrefslogtreecommitdiffstats
path: root/include/linux/mmc/sh_mmcif.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/linux/mmc/sh_mmcif.h')
-rw-r--r--include/linux/mmc/sh_mmcif.h109
1 files changed, 66 insertions, 43 deletions
diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h
index d4a2ebbdab4b..9eb9b4b96f55 100644
--- a/include/linux/mmc/sh_mmcif.h
+++ b/include/linux/mmc/sh_mmcif.h
@@ -14,8 +14,9 @@
14#ifndef __SH_MMCIF_H__ 14#ifndef __SH_MMCIF_H__
15#define __SH_MMCIF_H__ 15#define __SH_MMCIF_H__
16 16
17#include <linux/platform_device.h>
18#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/platform_device.h>
19#include <linux/sh_dma.h>
19 20
20/* 21/*
21 * MMCIF : CE_CLK_CTRL [19:16] 22 * MMCIF : CE_CLK_CTRL [19:16]
@@ -31,12 +32,19 @@
31 * 1111 : Peripheral clock (sup_pclk set '1') 32 * 1111 : Peripheral clock (sup_pclk set '1')
32 */ 33 */
33 34
35struct sh_mmcif_dma {
36 struct sh_dmae_slave chan_priv_tx;
37 struct sh_dmae_slave chan_priv_rx;
38};
39
34struct sh_mmcif_plat_data { 40struct sh_mmcif_plat_data {
35 void (*set_pwr)(struct platform_device *pdev, int state); 41 void (*set_pwr)(struct platform_device *pdev, int state);
36 void (*down_pwr)(struct platform_device *pdev); 42 void (*down_pwr)(struct platform_device *pdev);
37 u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */ 43 int (*get_cd)(struct platform_device *pdef);
38 unsigned long caps; 44 struct sh_mmcif_dma *dma;
39 u32 ocr; 45 u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
46 unsigned long caps;
47 u32 ocr;
40}; 48};
41 49
42#define MMCIF_CE_CMD_SET 0x00000000 50#define MMCIF_CE_CMD_SET 0x00000000
@@ -58,19 +66,45 @@ struct sh_mmcif_plat_data {
58#define MMCIF_CE_HOST_STS2 0x0000004C 66#define MMCIF_CE_HOST_STS2 0x0000004C
59#define MMCIF_CE_VERSION 0x0000007C 67#define MMCIF_CE_VERSION 0x0000007C
60 68
61extern inline u32 sh_mmcif_readl(void __iomem *addr, int reg) 69/* CE_BUF_ACC */
70#define BUF_ACC_DMAWEN (1 << 25)
71#define BUF_ACC_DMAREN (1 << 24)
72#define BUF_ACC_BUSW_32 (0 << 17)
73#define BUF_ACC_BUSW_16 (1 << 17)
74#define BUF_ACC_ATYP (1 << 16)
75
76/* CE_CLK_CTRL */
77#define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
78#define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
79#define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
80#define CLKDIV_4 (1<<16) /* mmc clock frequency.
81 * n: bus clock/(2^(n+1)) */
82#define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */
83#define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */
84#define SRBSYTO_29 ((1 << 11) | (1 << 10) | \
85 (1 << 9) | (1 << 8)) /* resp busy timeout */
86#define SRWDTO_29 ((1 << 7) | (1 << 6) | \
87 (1 << 5) | (1 << 4)) /* read/write timeout */
88#define SCCSTO_29 ((1 << 3) | (1 << 2) | \
89 (1 << 1) | (1 << 0)) /* ccs timeout */
90
91/* CE_VERSION */
92#define SOFT_RST_ON (1 << 31)
93#define SOFT_RST_OFF 0
94
95static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
62{ 96{
63 return readl(addr + reg); 97 return __raw_readl(addr + reg);
64} 98}
65 99
66extern inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val) 100static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
67{ 101{
68 writel(val, addr + reg); 102 __raw_writel(val, addr + reg);
69} 103}
70 104
71#define SH_MMCIF_BBS 512 /* boot block size */ 105#define SH_MMCIF_BBS 512 /* boot block size */
72 106
73extern inline void sh_mmcif_boot_cmd_send(void __iomem *base, 107static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
74 unsigned long cmd, unsigned long arg) 108 unsigned long cmd, unsigned long arg)
75{ 109{
76 sh_mmcif_writel(base, MMCIF_CE_INT, 0); 110 sh_mmcif_writel(base, MMCIF_CE_INT, 0);
@@ -78,7 +112,7 @@ extern inline void sh_mmcif_boot_cmd_send(void __iomem *base,
78 sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd); 112 sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
79} 113}
80 114
81extern inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask) 115static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
82{ 116{
83 unsigned long tmp; 117 unsigned long tmp;
84 int cnt; 118 int cnt;
@@ -94,14 +128,14 @@ extern inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
94 return -1; 128 return -1;
95} 129}
96 130
97extern inline int sh_mmcif_boot_cmd(void __iomem *base, 131static inline int sh_mmcif_boot_cmd(void __iomem *base,
98 unsigned long cmd, unsigned long arg) 132 unsigned long cmd, unsigned long arg)
99{ 133{
100 sh_mmcif_boot_cmd_send(base, cmd, arg); 134 sh_mmcif_boot_cmd_send(base, cmd, arg);
101 return sh_mmcif_boot_cmd_poll(base, 0x00010000); 135 return sh_mmcif_boot_cmd_poll(base, 0x00010000);
102} 136}
103 137
104extern inline int sh_mmcif_boot_do_read_single(void __iomem *base, 138static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
105 unsigned int block_nr, 139 unsigned int block_nr,
106 unsigned long *buf) 140 unsigned long *buf)
107{ 141{
@@ -124,7 +158,7 @@ extern inline int sh_mmcif_boot_do_read_single(void __iomem *base,
124 return 0; 158 return 0;
125} 159}
126 160
127extern inline int sh_mmcif_boot_do_read(void __iomem *base, 161static inline int sh_mmcif_boot_do_read(void __iomem *base,
128 unsigned long first_block, 162 unsigned long first_block,
129 unsigned long nr_blocks, 163 unsigned long nr_blocks,
130 void *buf) 164 void *buf)
@@ -132,6 +166,17 @@ extern inline int sh_mmcif_boot_do_read(void __iomem *base,
132 unsigned long k; 166 unsigned long k;
133 int ret = 0; 167 int ret = 0;
134 168
169 /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
170 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
171 CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
172 SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
173
174 /* CMD9 - Get CSD */
175 sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
176
177 /* CMD7 - Select the card */
178 sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
179
135 /* CMD16 - Set the block size */ 180 /* CMD16 - Set the block size */
136 sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS); 181 sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
137 182
@@ -142,23 +187,22 @@ extern inline int sh_mmcif_boot_do_read(void __iomem *base,
142 return ret; 187 return ret;
143} 188}
144 189
145extern inline void sh_mmcif_boot_init(void __iomem *base) 190static inline void sh_mmcif_boot_init(void __iomem *base)
146{ 191{
147 unsigned long tmp;
148
149 /* reset */ 192 /* reset */
150 tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION); 193 sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
151 sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | 0x80000000); 194 sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
152 sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & ~0x80000000);
153 195
154 /* byte swap */ 196 /* byte swap */
155 sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, 0x00010000); 197 sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
156 198
157 /* Set block size in MMCIF hardware */ 199 /* Set block size in MMCIF hardware */
158 sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS); 200 sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
159 201
160 /* Enable the clock, set it to Bus clock/256 (about 325Khz)*/ 202 /* Enable the clock, set it to Bus clock/256 (about 325Khz). */
161 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01072fff); 203 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
204 CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
205 SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
162 206
163 /* CMD0 */ 207 /* CMD0 */
164 sh_mmcif_boot_cmd(base, 0x00000040, 0); 208 sh_mmcif_boot_cmd(base, 0x00000040, 0);
@@ -176,25 +220,4 @@ extern inline void sh_mmcif_boot_init(void __iomem *base)
176 sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000); 220 sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
177} 221}
178 222
179extern inline void sh_mmcif_boot_slurp(void __iomem *base,
180 unsigned char *buf,
181 unsigned long no_bytes)
182{
183 unsigned long tmp;
184
185 /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
186 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff);
187
188 /* CMD9 - Get CSD */
189 sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
190
191 /* CMD7 - Select the card */
192 sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
193
194 tmp = no_bytes / SH_MMCIF_BBS;
195 tmp += (no_bytes % SH_MMCIF_BBS) ? 1 : 0;
196
197 sh_mmcif_boot_do_read(base, 512, tmp, buf);
198}
199
200#endif /* __SH_MMCIF_H__ */ 223#endif /* __SH_MMCIF_H__ */