diff options
Diffstat (limited to 'include/linux/mlx4')
| -rw-r--r-- | include/linux/mlx4/cmd.h | 51 | ||||
| -rw-r--r-- | include/linux/mlx4/device.h | 80 | ||||
| -rw-r--r-- | include/linux/mlx4/qp.h | 28 |
3 files changed, 135 insertions, 24 deletions
diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h index b56e4587208d..9958ff2cad3c 100644 --- a/include/linux/mlx4/cmd.h +++ b/include/linux/mlx4/cmd.h | |||
| @@ -59,12 +59,15 @@ enum { | |||
| 59 | MLX4_CMD_HW_HEALTH_CHECK = 0x50, | 59 | MLX4_CMD_HW_HEALTH_CHECK = 0x50, |
| 60 | MLX4_CMD_SET_PORT = 0xc, | 60 | MLX4_CMD_SET_PORT = 0xc, |
| 61 | MLX4_CMD_SET_NODE = 0x5a, | 61 | MLX4_CMD_SET_NODE = 0x5a, |
| 62 | MLX4_CMD_QUERY_FUNC = 0x56, | ||
| 62 | MLX4_CMD_ACCESS_DDR = 0x2e, | 63 | MLX4_CMD_ACCESS_DDR = 0x2e, |
| 63 | MLX4_CMD_MAP_ICM = 0xffa, | 64 | MLX4_CMD_MAP_ICM = 0xffa, |
| 64 | MLX4_CMD_UNMAP_ICM = 0xff9, | 65 | MLX4_CMD_UNMAP_ICM = 0xff9, |
| 65 | MLX4_CMD_MAP_ICM_AUX = 0xffc, | 66 | MLX4_CMD_MAP_ICM_AUX = 0xffc, |
| 66 | MLX4_CMD_UNMAP_ICM_AUX = 0xffb, | 67 | MLX4_CMD_UNMAP_ICM_AUX = 0xffb, |
| 67 | MLX4_CMD_SET_ICM_SIZE = 0xffd, | 68 | MLX4_CMD_SET_ICM_SIZE = 0xffd, |
| 69 | /*master notify fw on finish for slave's flr*/ | ||
| 70 | MLX4_CMD_INFORM_FLR_DONE = 0x5b, | ||
| 68 | 71 | ||
| 69 | /* TPT commands */ | 72 | /* TPT commands */ |
| 70 | MLX4_CMD_SW2HW_MPT = 0xd, | 73 | MLX4_CMD_SW2HW_MPT = 0xd, |
| @@ -119,6 +122,26 @@ enum { | |||
| 119 | /* miscellaneous commands */ | 122 | /* miscellaneous commands */ |
| 120 | MLX4_CMD_DIAG_RPRT = 0x30, | 123 | MLX4_CMD_DIAG_RPRT = 0x30, |
| 121 | MLX4_CMD_NOP = 0x31, | 124 | MLX4_CMD_NOP = 0x31, |
| 125 | MLX4_CMD_ACCESS_MEM = 0x2e, | ||
| 126 | MLX4_CMD_SET_VEP = 0x52, | ||
| 127 | |||
| 128 | /* Ethernet specific commands */ | ||
| 129 | MLX4_CMD_SET_VLAN_FLTR = 0x47, | ||
| 130 | MLX4_CMD_SET_MCAST_FLTR = 0x48, | ||
| 131 | MLX4_CMD_DUMP_ETH_STATS = 0x49, | ||
| 132 | |||
| 133 | /* Communication channel commands */ | ||
| 134 | MLX4_CMD_ARM_COMM_CHANNEL = 0x57, | ||
| 135 | MLX4_CMD_GEN_EQE = 0x58, | ||
| 136 | |||
| 137 | /* virtual commands */ | ||
| 138 | MLX4_CMD_ALLOC_RES = 0xf00, | ||
| 139 | MLX4_CMD_FREE_RES = 0xf01, | ||
| 140 | MLX4_CMD_MCAST_ATTACH = 0xf05, | ||
| 141 | MLX4_CMD_UCAST_ATTACH = 0xf06, | ||
| 142 | MLX4_CMD_PROMISC = 0xf08, | ||
| 143 | MLX4_CMD_QUERY_FUNC_CAP = 0xf0a, | ||
| 144 | MLX4_CMD_QP_ATTACH = 0xf0b, | ||
| 122 | 145 | ||
| 123 | /* debug commands */ | 146 | /* debug commands */ |
| 124 | MLX4_CMD_QUERY_DEBUG_MSG = 0x2a, | 147 | MLX4_CMD_QUERY_DEBUG_MSG = 0x2a, |
| @@ -126,6 +149,7 @@ enum { | |||
| 126 | 149 | ||
| 127 | /* statistics commands */ | 150 | /* statistics commands */ |
| 128 | MLX4_CMD_QUERY_IF_STAT = 0X54, | 151 | MLX4_CMD_QUERY_IF_STAT = 0X54, |
| 152 | MLX4_CMD_SET_IF_STAT = 0X55, | ||
| 129 | }; | 153 | }; |
| 130 | 154 | ||
| 131 | enum { | 155 | enum { |
| @@ -135,7 +159,8 @@ enum { | |||
| 135 | }; | 159 | }; |
| 136 | 160 | ||
| 137 | enum { | 161 | enum { |
| 138 | MLX4_MAILBOX_SIZE = 4096 | 162 | MLX4_MAILBOX_SIZE = 4096, |
| 163 | MLX4_ACCESS_MEM_ALIGN = 256, | ||
| 139 | }; | 164 | }; |
| 140 | 165 | ||
| 141 | enum { | 166 | enum { |
| @@ -148,6 +173,11 @@ enum { | |||
| 148 | MLX4_SET_PORT_GID_TABLE = 0x5, | 173 | MLX4_SET_PORT_GID_TABLE = 0x5, |
| 149 | }; | 174 | }; |
| 150 | 175 | ||
| 176 | enum { | ||
| 177 | MLX4_CMD_WRAPPED, | ||
| 178 | MLX4_CMD_NATIVE | ||
| 179 | }; | ||
| 180 | |||
| 151 | struct mlx4_dev; | 181 | struct mlx4_dev; |
| 152 | 182 | ||
| 153 | struct mlx4_cmd_mailbox { | 183 | struct mlx4_cmd_mailbox { |
| @@ -157,23 +187,24 @@ struct mlx4_cmd_mailbox { | |||
| 157 | 187 | ||
| 158 | int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param, | 188 | int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param, |
| 159 | int out_is_imm, u32 in_modifier, u8 op_modifier, | 189 | int out_is_imm, u32 in_modifier, u8 op_modifier, |
| 160 | u16 op, unsigned long timeout); | 190 | u16 op, unsigned long timeout, int native); |
| 161 | 191 | ||
| 162 | /* Invoke a command with no output parameter */ | 192 | /* Invoke a command with no output parameter */ |
| 163 | static inline int mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u32 in_modifier, | 193 | static inline int mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u32 in_modifier, |
| 164 | u8 op_modifier, u16 op, unsigned long timeout) | 194 | u8 op_modifier, u16 op, unsigned long timeout, |
| 195 | int native) | ||
| 165 | { | 196 | { |
| 166 | return __mlx4_cmd(dev, in_param, NULL, 0, in_modifier, | 197 | return __mlx4_cmd(dev, in_param, NULL, 0, in_modifier, |
| 167 | op_modifier, op, timeout); | 198 | op_modifier, op, timeout, native); |
| 168 | } | 199 | } |
| 169 | 200 | ||
| 170 | /* Invoke a command with an output mailbox */ | 201 | /* Invoke a command with an output mailbox */ |
| 171 | static inline int mlx4_cmd_box(struct mlx4_dev *dev, u64 in_param, u64 out_param, | 202 | static inline int mlx4_cmd_box(struct mlx4_dev *dev, u64 in_param, u64 out_param, |
| 172 | u32 in_modifier, u8 op_modifier, u16 op, | 203 | u32 in_modifier, u8 op_modifier, u16 op, |
| 173 | unsigned long timeout) | 204 | unsigned long timeout, int native) |
| 174 | { | 205 | { |
| 175 | return __mlx4_cmd(dev, in_param, &out_param, 0, in_modifier, | 206 | return __mlx4_cmd(dev, in_param, &out_param, 0, in_modifier, |
| 176 | op_modifier, op, timeout); | 207 | op_modifier, op, timeout, native); |
| 177 | } | 208 | } |
| 178 | 209 | ||
| 179 | /* | 210 | /* |
| @@ -183,13 +214,17 @@ static inline int mlx4_cmd_box(struct mlx4_dev *dev, u64 in_param, u64 out_param | |||
| 183 | */ | 214 | */ |
| 184 | static inline int mlx4_cmd_imm(struct mlx4_dev *dev, u64 in_param, u64 *out_param, | 215 | static inline int mlx4_cmd_imm(struct mlx4_dev *dev, u64 in_param, u64 *out_param, |
| 185 | u32 in_modifier, u8 op_modifier, u16 op, | 216 | u32 in_modifier, u8 op_modifier, u16 op, |
| 186 | unsigned long timeout) | 217 | unsigned long timeout, int native) |
| 187 | { | 218 | { |
| 188 | return __mlx4_cmd(dev, in_param, out_param, 1, in_modifier, | 219 | return __mlx4_cmd(dev, in_param, out_param, 1, in_modifier, |
| 189 | op_modifier, op, timeout); | 220 | op_modifier, op, timeout, native); |
| 190 | } | 221 | } |
| 191 | 222 | ||
| 192 | struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev); | 223 | struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev); |
| 193 | void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox); | 224 | void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox); |
| 194 | 225 | ||
| 226 | u32 mlx4_comm_get_version(void); | ||
| 227 | |||
| 228 | #define MLX4_COMM_GET_IF_REV(cmd_chan_ver) (u8)((cmd_chan_ver) >> 8) | ||
| 229 | |||
| 195 | #endif /* MLX4_CMD_H */ | 230 | #endif /* MLX4_CMD_H */ |
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index 84b0b1848f17..5c4fe8e5bfe5 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h | |||
| @@ -47,6 +47,9 @@ | |||
| 47 | enum { | 47 | enum { |
| 48 | MLX4_FLAG_MSI_X = 1 << 0, | 48 | MLX4_FLAG_MSI_X = 1 << 0, |
| 49 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, | 49 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
| 50 | MLX4_FLAG_MASTER = 1 << 2, | ||
| 51 | MLX4_FLAG_SLAVE = 1 << 3, | ||
| 52 | MLX4_FLAG_SRIOV = 1 << 4, | ||
| 50 | }; | 53 | }; |
| 51 | 54 | ||
| 52 | enum { | 55 | enum { |
| @@ -58,6 +61,15 @@ enum { | |||
| 58 | }; | 61 | }; |
| 59 | 62 | ||
| 60 | enum { | 63 | enum { |
| 64 | MLX4_MAX_NUM_PF = 16, | ||
| 65 | MLX4_MAX_NUM_VF = 64, | ||
| 66 | MLX4_MFUNC_MAX = 80, | ||
| 67 | MLX4_MFUNC_EQ_NUM = 4, | ||
| 68 | MLX4_MFUNC_MAX_EQES = 8, | ||
| 69 | MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) | ||
| 70 | }; | ||
| 71 | |||
| 72 | enum { | ||
| 61 | MLX4_DEV_CAP_FLAG_RC = 1LL << 0, | 73 | MLX4_DEV_CAP_FLAG_RC = 1LL << 0, |
| 62 | MLX4_DEV_CAP_FLAG_UC = 1LL << 1, | 74 | MLX4_DEV_CAP_FLAG_UC = 1LL << 1, |
| 63 | MLX4_DEV_CAP_FLAG_UD = 1LL << 2, | 75 | MLX4_DEV_CAP_FLAG_UD = 1LL << 2, |
| @@ -77,11 +89,13 @@ enum { | |||
| 77 | MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, | 89 | MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, |
| 78 | MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, | 90 | MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, |
| 79 | MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, | 91 | MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, |
| 80 | MLX4_DEV_CAP_FLAG_WOL = 1LL << 38, | 92 | MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, |
| 93 | MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, | ||
| 81 | MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, | 94 | MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, |
| 82 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, | 95 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, |
| 83 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, | 96 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, |
| 84 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48 | 97 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, |
| 98 | MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55 | ||
| 85 | }; | 99 | }; |
| 86 | 100 | ||
| 87 | #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) | 101 | #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
| @@ -116,7 +130,11 @@ enum mlx4_event { | |||
| 116 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, | 130 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, |
| 117 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, | 131 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, |
| 118 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, | 132 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, |
| 119 | MLX4_EVENT_TYPE_CMD = 0x0a | 133 | MLX4_EVENT_TYPE_CMD = 0x0a, |
| 134 | MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, | ||
| 135 | MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, | ||
| 136 | MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, | ||
| 137 | MLX4_EVENT_TYPE_NONE = 0xff, | ||
| 120 | }; | 138 | }; |
| 121 | 139 | ||
| 122 | enum { | 140 | enum { |
| @@ -183,6 +201,7 @@ enum mlx4_qp_region { | |||
| 183 | }; | 201 | }; |
| 184 | 202 | ||
| 185 | enum mlx4_port_type { | 203 | enum mlx4_port_type { |
| 204 | MLX4_PORT_TYPE_NONE = 0, | ||
| 186 | MLX4_PORT_TYPE_IB = 1, | 205 | MLX4_PORT_TYPE_IB = 1, |
| 187 | MLX4_PORT_TYPE_ETH = 2, | 206 | MLX4_PORT_TYPE_ETH = 2, |
| 188 | MLX4_PORT_TYPE_AUTO = 3 | 207 | MLX4_PORT_TYPE_AUTO = 3 |
| @@ -215,6 +234,7 @@ static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) | |||
| 215 | 234 | ||
| 216 | struct mlx4_caps { | 235 | struct mlx4_caps { |
| 217 | u64 fw_ver; | 236 | u64 fw_ver; |
| 237 | u32 function; | ||
| 218 | int num_ports; | 238 | int num_ports; |
| 219 | int vl_cap[MLX4_MAX_PORTS + 1]; | 239 | int vl_cap[MLX4_MAX_PORTS + 1]; |
| 220 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; | 240 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
| @@ -229,6 +249,7 @@ struct mlx4_caps { | |||
| 229 | u64 trans_code[MLX4_MAX_PORTS + 1]; | 249 | u64 trans_code[MLX4_MAX_PORTS + 1]; |
| 230 | int local_ca_ack_delay; | 250 | int local_ca_ack_delay; |
| 231 | int num_uars; | 251 | int num_uars; |
| 252 | u32 uar_page_size; | ||
| 232 | int bf_reg_size; | 253 | int bf_reg_size; |
| 233 | int bf_regs_per_page; | 254 | int bf_regs_per_page; |
| 234 | int max_sq_sg; | 255 | int max_sq_sg; |
| @@ -252,8 +273,7 @@ struct mlx4_caps { | |||
| 252 | int num_comp_vectors; | 273 | int num_comp_vectors; |
| 253 | int comp_pool; | 274 | int comp_pool; |
| 254 | int num_mpts; | 275 | int num_mpts; |
| 255 | int num_mtt_segs; | 276 | int num_mtts; |
| 256 | int mtts_per_seg; | ||
| 257 | int fmr_reserved_mtts; | 277 | int fmr_reserved_mtts; |
| 258 | int reserved_mtts; | 278 | int reserved_mtts; |
| 259 | int reserved_mrws; | 279 | int reserved_mrws; |
| @@ -283,7 +303,9 @@ struct mlx4_caps { | |||
| 283 | int log_num_prios; | 303 | int log_num_prios; |
| 284 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; | 304 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
| 285 | u8 supported_type[MLX4_MAX_PORTS + 1]; | 305 | u8 supported_type[MLX4_MAX_PORTS + 1]; |
| 286 | u32 port_mask; | 306 | u8 suggested_type[MLX4_MAX_PORTS + 1]; |
| 307 | u8 default_sense[MLX4_MAX_PORTS + 1]; | ||
| 308 | u32 port_mask[MLX4_MAX_PORTS + 1]; | ||
| 287 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; | 309 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; |
| 288 | u32 max_counters; | 310 | u32 max_counters; |
| 289 | u8 ext_port_cap[MLX4_MAX_PORTS + 1]; | 311 | u8 ext_port_cap[MLX4_MAX_PORTS + 1]; |
| @@ -303,7 +325,7 @@ struct mlx4_buf { | |||
| 303 | }; | 325 | }; |
| 304 | 326 | ||
| 305 | struct mlx4_mtt { | 327 | struct mlx4_mtt { |
| 306 | u32 first_seg; | 328 | u32 offset; |
| 307 | int order; | 329 | int order; |
| 308 | int page_shift; | 330 | int page_shift; |
| 309 | }; | 331 | }; |
| @@ -465,10 +487,12 @@ struct mlx4_counter { | |||
| 465 | struct mlx4_dev { | 487 | struct mlx4_dev { |
| 466 | struct pci_dev *pdev; | 488 | struct pci_dev *pdev; |
| 467 | unsigned long flags; | 489 | unsigned long flags; |
| 490 | unsigned long num_slaves; | ||
| 468 | struct mlx4_caps caps; | 491 | struct mlx4_caps caps; |
| 469 | struct radix_tree_root qp_table_tree; | 492 | struct radix_tree_root qp_table_tree; |
| 470 | u8 rev_id; | 493 | u8 rev_id; |
| 471 | char board_id[MLX4_BOARD_ID_LEN]; | 494 | char board_id[MLX4_BOARD_ID_LEN]; |
| 495 | int num_vfs; | ||
| 472 | }; | 496 | }; |
| 473 | 497 | ||
| 474 | struct mlx4_init_port_param { | 498 | struct mlx4_init_port_param { |
| @@ -487,14 +511,32 @@ struct mlx4_init_port_param { | |||
| 487 | 511 | ||
| 488 | #define mlx4_foreach_port(port, dev, type) \ | 512 | #define mlx4_foreach_port(port, dev, type) \ |
| 489 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | 513 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ |
| 490 | if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \ | 514 | if ((type) == (dev)->caps.port_mask[(port)]) |
| 491 | ~(dev)->caps.port_mask) & 1 << ((port) - 1)) | ||
| 492 | 515 | ||
| 493 | #define mlx4_foreach_ib_transport_port(port, dev) \ | 516 | #define mlx4_foreach_ib_transport_port(port, dev) \ |
| 494 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | 517 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ |
| 495 | if (((dev)->caps.port_mask & 1 << ((port) - 1)) || \ | 518 | if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ |
| 496 | ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) | 519 | ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) |
| 497 | 520 | ||
| 521 | static inline int mlx4_is_master(struct mlx4_dev *dev) | ||
| 522 | { | ||
| 523 | return dev->flags & MLX4_FLAG_MASTER; | ||
| 524 | } | ||
| 525 | |||
| 526 | static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) | ||
| 527 | { | ||
| 528 | return (qpn < dev->caps.sqp_start + 8); | ||
| 529 | } | ||
| 530 | |||
| 531 | static inline int mlx4_is_mfunc(struct mlx4_dev *dev) | ||
| 532 | { | ||
| 533 | return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); | ||
| 534 | } | ||
| 535 | |||
| 536 | static inline int mlx4_is_slave(struct mlx4_dev *dev) | ||
| 537 | { | ||
| 538 | return dev->flags & MLX4_FLAG_SLAVE; | ||
| 539 | } | ||
| 498 | 540 | ||
| 499 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, | 541 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
| 500 | struct mlx4_buf *buf); | 542 | struct mlx4_buf *buf); |
| @@ -560,6 +602,10 @@ int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_waterm | |||
| 560 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); | 602 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
| 561 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); | 603 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
| 562 | 604 | ||
| 605 | int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | ||
| 606 | int block_mcast_loopback, enum mlx4_protocol prot); | ||
| 607 | int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | ||
| 608 | enum mlx4_protocol prot); | ||
| 563 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | 609 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
| 564 | int block_mcast_loopback, enum mlx4_protocol protocol); | 610 | int block_mcast_loopback, enum mlx4_protocol protocol); |
| 565 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | 611 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
| @@ -570,9 +616,11 @@ int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); | |||
| 570 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | 616 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); |
| 571 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); | 617 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); |
| 572 | 618 | ||
| 573 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn, u8 wrap); | 619 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); |
| 574 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int qpn); | 620 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); |
| 575 | int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac, u8 wrap); | 621 | int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); |
| 622 | int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn); | ||
| 623 | void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn); | ||
| 576 | 624 | ||
| 577 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); | 625 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
| 578 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); | 626 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h index 48cc4cb97858..bee8fa231276 100644 --- a/include/linux/mlx4/qp.h +++ b/include/linux/mlx4/qp.h | |||
| @@ -97,6 +97,33 @@ enum { | |||
| 97 | MLX4_QP_BIT_RIC = 1 << 4, | 97 | MLX4_QP_BIT_RIC = 1 << 4, |
| 98 | }; | 98 | }; |
| 99 | 99 | ||
| 100 | enum { | ||
| 101 | MLX4_RSS_HASH_XOR = 0, | ||
| 102 | MLX4_RSS_HASH_TOP = 1, | ||
| 103 | |||
| 104 | MLX4_RSS_UDP_IPV6 = 1 << 0, | ||
| 105 | MLX4_RSS_UDP_IPV4 = 1 << 1, | ||
| 106 | MLX4_RSS_TCP_IPV6 = 1 << 2, | ||
| 107 | MLX4_RSS_IPV6 = 1 << 3, | ||
| 108 | MLX4_RSS_TCP_IPV4 = 1 << 4, | ||
| 109 | MLX4_RSS_IPV4 = 1 << 5, | ||
| 110 | |||
| 111 | /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */ | ||
| 112 | MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24, | ||
| 113 | /* offset of being RSS indirection QP within mlx4_qp_context.flags */ | ||
| 114 | MLX4_RSS_QPC_FLAG_OFFSET = 13, | ||
| 115 | }; | ||
| 116 | |||
| 117 | struct mlx4_rss_context { | ||
| 118 | __be32 base_qpn; | ||
| 119 | __be32 default_qpn; | ||
| 120 | u16 reserved; | ||
| 121 | u8 hash_fn; | ||
| 122 | u8 flags; | ||
| 123 | __be32 rss_key[10]; | ||
| 124 | __be32 base_qpn_udp; | ||
| 125 | }; | ||
| 126 | |||
| 100 | struct mlx4_qp_path { | 127 | struct mlx4_qp_path { |
| 101 | u8 fl; | 128 | u8 fl; |
| 102 | u8 reserved1[2]; | 129 | u8 reserved1[2]; |
| @@ -183,6 +210,7 @@ struct mlx4_wqe_ctrl_seg { | |||
| 183 | * [4] IP checksum | 210 | * [4] IP checksum |
| 184 | * [3:2] C (generate completion queue entry) | 211 | * [3:2] C (generate completion queue entry) |
| 185 | * [1] SE (solicited event) | 212 | * [1] SE (solicited event) |
| 213 | * [0] FL (force loopback) | ||
| 186 | */ | 214 | */ |
| 187 | __be32 srcrb_flags; | 215 | __be32 srcrb_flags; |
| 188 | /* | 216 | /* |
