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-rw-r--r--include/linux/mlx4/cmd.h6
-rw-r--r--include/linux/mlx4/cq.h16
-rw-r--r--include/linux/mlx4/device.h117
-rw-r--r--include/linux/mlx4/qp.h29
-rw-r--r--include/linux/mlx4/srq.h2
5 files changed, 160 insertions, 10 deletions
diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h
index 260695186256..adf6e0648f20 100644
--- a/include/linux/mlx4/cmd.h
+++ b/include/linux/mlx4/cmd.h
@@ -34,6 +34,7 @@
34#define MLX4_CMD_H 34#define MLX4_CMD_H
35 35
36#include <linux/dma-mapping.h> 36#include <linux/dma-mapping.h>
37#include <linux/if_link.h>
37 38
38enum { 39enum {
39 /* initialization and general commands */ 40 /* initialization and general commands */
@@ -232,6 +233,11 @@ struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev);
232void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox); 233void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox);
233 234
234u32 mlx4_comm_get_version(void); 235u32 mlx4_comm_get_version(void);
236int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac);
237int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos);
238int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting);
239int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf);
240
235 241
236#define MLX4_COMM_GET_IF_REV(cmd_chan_ver) (u8)((cmd_chan_ver) >> 8) 242#define MLX4_COMM_GET_IF_REV(cmd_chan_ver) (u8)((cmd_chan_ver) >> 8)
237 243
diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h
index 6f65b2c8bb89..98fa492cf406 100644
--- a/include/linux/mlx4/cq.h
+++ b/include/linux/mlx4/cq.h
@@ -64,6 +64,22 @@ struct mlx4_err_cqe {
64 u8 owner_sr_opcode; 64 u8 owner_sr_opcode;
65}; 65};
66 66
67struct mlx4_ts_cqe {
68 __be32 vlan_my_qpn;
69 __be32 immed_rss_invalid;
70 __be32 g_mlpath_rqpn;
71 __be32 timestamp_hi;
72 __be16 status;
73 u8 ipv6_ext_mask;
74 u8 badfcs_enc;
75 __be32 byte_cnt;
76 __be16 wqe_index;
77 __be16 checksum;
78 u8 reserved;
79 __be16 timestamp_lo;
80 u8 owner_sr_opcode;
81} __packed;
82
67enum { 83enum {
68 MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29, 84 MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29,
69 MLX4_CQE_QPN_MASK = 0xffffff, 85 MLX4_CQE_QPN_MASK = 0xffffff,
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index 811f91cf5e8c..a51b0134ce18 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -40,6 +40,8 @@
40 40
41#include <linux/atomic.h> 41#include <linux/atomic.h>
42 42
43#include <linux/clocksource.h>
44
43#define MAX_MSIX_P_PORT 17 45#define MAX_MSIX_P_PORT 17
44#define MAX_MSIX 64 46#define MAX_MSIX 64
45#define MSIX_LEGACY_SZ 4 47#define MSIX_LEGACY_SZ 4
@@ -140,6 +142,7 @@ enum {
140 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 142 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
141 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 143 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
142 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 144 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
145 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
143 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 146 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
144 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 147 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
145 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 148 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
@@ -151,7 +154,10 @@ enum {
151 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 154 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
152 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 155 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
153 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, 156 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
154 MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN = 1LL << 4 157 MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN = 1LL << 4,
158 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
159 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
160 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7
155}; 161};
156 162
157enum { 163enum {
@@ -443,6 +449,7 @@ struct mlx4_caps {
443 u8 eqe_factor; 449 u8 eqe_factor;
444 u32 userspace_caps; /* userspace must be aware of these */ 450 u32 userspace_caps; /* userspace must be aware of these */
445 u32 function_caps; /* VFs must be aware of these */ 451 u32 function_caps; /* VFs must be aware of these */
452 u16 hca_core_clock;
446}; 453};
447 454
448struct mlx4_buf_list { 455struct mlx4_buf_list {
@@ -837,7 +844,7 @@ void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
837 844
838int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 845int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
839 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 846 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
840 unsigned vector, int collapsed); 847 unsigned vector, int collapsed, int timestamp_en);
841void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 848void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
842 849
843int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); 850int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
@@ -896,11 +903,12 @@ static inline int map_hw_to_sw_id(u16 header_id)
896} 903}
897 904
898enum mlx4_net_trans_promisc_mode { 905enum mlx4_net_trans_promisc_mode {
899 MLX4_FS_PROMISC_NONE = 0, 906 MLX4_FS_REGULAR = 1,
900 MLX4_FS_PROMISC_UPLINK, 907 MLX4_FS_ALL_DEFAULT,
901 /* For future use. Not implemented yet */ 908 MLX4_FS_MC_DEFAULT,
902 MLX4_FS_PROMISC_FUNCTION_PORT, 909 MLX4_FS_UC_SNIFFER,
903 MLX4_FS_PROMISC_ALL_MULTI, 910 MLX4_FS_MC_SNIFFER,
911 MLX4_FS_MODE_NUM, /* should be last */
904}; 912};
905 913
906struct mlx4_spec_eth { 914struct mlx4_spec_eth {
@@ -929,7 +937,7 @@ struct mlx4_spec_ipv4 {
929}; 937};
930 938
931struct mlx4_spec_ib { 939struct mlx4_spec_ib {
932 __be32 r_qpn; 940 __be32 l3_qpn;
933 __be32 qpn_msk; 941 __be32 qpn_msk;
934 u8 dst_gid[16]; 942 u8 dst_gid[16];
935 u8 dst_gid_msk[16]; 943 u8 dst_gid_msk[16];
@@ -962,6 +970,92 @@ struct mlx4_net_trans_rule {
962 u32 qpn; 970 u32 qpn;
963}; 971};
964 972
973struct mlx4_net_trans_rule_hw_ctrl {
974 __be16 prio;
975 u8 type;
976 u8 flags;
977 u8 rsvd1;
978 u8 funcid;
979 u8 vep;
980 u8 port;
981 __be32 qpn;
982 __be32 rsvd2;
983};
984
985struct mlx4_net_trans_rule_hw_ib {
986 u8 size;
987 u8 rsvd1;
988 __be16 id;
989 u32 rsvd2;
990 __be32 l3_qpn;
991 __be32 qpn_mask;
992 u8 dst_gid[16];
993 u8 dst_gid_msk[16];
994} __packed;
995
996struct mlx4_net_trans_rule_hw_eth {
997 u8 size;
998 u8 rsvd;
999 __be16 id;
1000 u8 rsvd1[6];
1001 u8 dst_mac[6];
1002 u16 rsvd2;
1003 u8 dst_mac_msk[6];
1004 u16 rsvd3;
1005 u8 src_mac[6];
1006 u16 rsvd4;
1007 u8 src_mac_msk[6];
1008 u8 rsvd5;
1009 u8 ether_type_enable;
1010 __be16 ether_type;
1011 __be16 vlan_tag_msk;
1012 __be16 vlan_tag;
1013} __packed;
1014
1015struct mlx4_net_trans_rule_hw_tcp_udp {
1016 u8 size;
1017 u8 rsvd;
1018 __be16 id;
1019 __be16 rsvd1[3];
1020 __be16 dst_port;
1021 __be16 rsvd2;
1022 __be16 dst_port_msk;
1023 __be16 rsvd3;
1024 __be16 src_port;
1025 __be16 rsvd4;
1026 __be16 src_port_msk;
1027} __packed;
1028
1029struct mlx4_net_trans_rule_hw_ipv4 {
1030 u8 size;
1031 u8 rsvd;
1032 __be16 id;
1033 __be32 rsvd1;
1034 __be32 dst_ip;
1035 __be32 dst_ip_msk;
1036 __be32 src_ip;
1037 __be32 src_ip_msk;
1038} __packed;
1039
1040struct _rule_hw {
1041 union {
1042 struct {
1043 u8 size;
1044 u8 rsvd;
1045 __be16 id;
1046 };
1047 struct mlx4_net_trans_rule_hw_eth eth;
1048 struct mlx4_net_trans_rule_hw_ib ib;
1049 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1050 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1051 };
1052};
1053
1054/* translating DMFS verbs sniffer rule to the FW API would need two reg IDs */
1055struct mlx4_flow_handle {
1056 u64 reg_id[2];
1057};
1058
965int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1059int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
966 enum mlx4_net_trans_promisc_mode mode); 1060 enum mlx4_net_trans_promisc_mode mode);
967int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1061int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
@@ -1011,6 +1105,11 @@ void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1011int mlx4_flow_attach(struct mlx4_dev *dev, 1105int mlx4_flow_attach(struct mlx4_dev *dev,
1012 struct mlx4_net_trans_rule *rule, u64 *reg_id); 1106 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1013int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1107int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1108int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1109 enum mlx4_net_trans_promisc_mode flow_type);
1110int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1111 enum mlx4_net_trans_rule_id id);
1112int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1014 1113
1015void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1114void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1016 int i, int val); 1115 int i, int val);
@@ -1028,4 +1127,6 @@ int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int
1028void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1127void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1029__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1128__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1030 1129
1130cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1131
1031#endif /* MLX4_DEVICE_H */ 1132#endif /* MLX4_DEVICE_H */
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h
index 67f46ad6920a..352eec9df1b8 100644
--- a/include/linux/mlx4/qp.h
+++ b/include/linux/mlx4/qp.h
@@ -126,7 +126,7 @@ struct mlx4_rss_context {
126 126
127struct mlx4_qp_path { 127struct mlx4_qp_path {
128 u8 fl; 128 u8 fl;
129 u8 reserved1[1]; 129 u8 vlan_control;
130 u8 disable_pkey_check; 130 u8 disable_pkey_check;
131 u8 pkey_index; 131 u8 pkey_index;
132 u8 counter_index; 132 u8 counter_index;
@@ -141,11 +141,32 @@ struct mlx4_qp_path {
141 u8 sched_queue; 141 u8 sched_queue;
142 u8 vlan_index; 142 u8 vlan_index;
143 u8 feup; 143 u8 feup;
144 u8 reserved3; 144 u8 fvl_rx;
145 u8 reserved4[2]; 145 u8 reserved4[2];
146 u8 dmac[6]; 146 u8 dmac[6];
147}; 147};
148 148
149enum { /* fl */
150 MLX4_FL_CV = 1 << 6,
151 MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2
152};
153enum { /* vlan_control */
154 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6,
155 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2,
156 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */
157 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0
158};
159
160enum { /* feup */
161 MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */
162 MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */
163 MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */
164};
165
166enum { /* fvl_rx */
167 MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */
168};
169
149struct mlx4_qp_context { 170struct mlx4_qp_context {
150 __be32 flags; 171 __be32 flags;
151 __be32 pd; 172 __be32 pd;
@@ -185,6 +206,10 @@ struct mlx4_qp_context {
185 u32 reserved5[10]; 206 u32 reserved5[10];
186}; 207};
187 208
209enum { /* param3 */
210 MLX4_STRIP_VLAN = 1 << 30
211};
212
188/* Which firmware version adds support for NEC (NoErrorCompletion) bit */ 213/* Which firmware version adds support for NEC (NoErrorCompletion) bit */
189#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) 214#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
190 215
diff --git a/include/linux/mlx4/srq.h b/include/linux/mlx4/srq.h
index 799a0697a383..192e0f7784f2 100644
--- a/include/linux/mlx4/srq.h
+++ b/include/linux/mlx4/srq.h
@@ -39,4 +39,6 @@ struct mlx4_wqe_srq_next_seg {
39 u32 reserved2[3]; 39 u32 reserved2[3];
40}; 40};
41 41
42struct mlx4_srq *mlx4_srq_lookup(struct mlx4_dev *dev, u32 srqn);
43
42#endif /* MLX4_SRQ_H */ 44#endif /* MLX4_SRQ_H */